EECS 141: Digital Integrated Circuits - Fall 2008
Report Cover Sheet
TERM PROJECT: 32x64 SRAM Design
Report 3 – Putting it all Together and Optimization
Due Monday, December 8, 2008 by 5:00pm in the drop box.
Names
Description of Optimization Objectives
(You should describe what your optimization goals were here: e.g., minimum power,
maximum speed, good balance of speed/area, etc.)
Parameter Value Units
Cell Area µm2
Calculated Adder/Subtractor ps
Delay
Simulated Adder/Subtractor ps
Delay
Calculated Decoder Delay ps
Simulated Decoder Delay ps
Simulated WL-Out Delay ps
Total Simulated Delay ps
Calculated Power Dissipation µW
Simulated Power Dissipation µW
Total Area µm2
GRADE
Approach, result and correctness (65%)
Report (35%)
TOTAL
Complete SRAM Design
(Annotated schematic or block diagram and layout of the complete array.
Simulation showing functional read with worst-case delay and timing of critical
signals, including any clocks you used. You should provide highlights of the key
optimizations/design decisions you made here - e.g., using domino logic in the
adder/subtractor, reducing the supply voltage for the SRAM, etc.)
SRAM Cell Design
(Schematic and layout of the SRAM cell. Read and write margins/butterfly plots.
You can skip this section if you did not modify the SRAM cell we gave you, but
otherwise you should explain any changes you made from the design given to you in
phase 1. )
Decoder Design
(Annotated schematics with gate sizes and layout of the decoder. Simulation
showing worst-case propagation delay, hand calculation of decoder delay and
power. Explain your design decisions and approach. You do not need to provide
transistor level schematics of any standard gates you used, but you should provide
schematics of any new/non-obvious gates.)
Adder/Subtractor Design
(Annotated schematics with gate sizes and layout of the adder/subtractor. Identify
the critial path and show hand calculation of delay and power. Worst-case delay
simulation showing the critical signals. Explain your design decisions and
approach. Schematics of any new and non-obvious gates.)
Appendix
(This space has been provided for you to include relevant information that did not
fit into the previous sections. This is a good place to put any additional analyses you
did that didn’t fit or you weren’t sure where to put. For example, you might provide
a more detailed power break-down/estimate of each of the major blocks, logical
effort sizing calculations of the complete adder/subtractor/decoder path, output
buffer/multiplexor sizing, etc.)