8 – Bit Gray Code
Converter
Murad Amer
Umair Sophie
Raymond Vengersammy
Advisor: Dr. David Parent
May 11, 2005
1
Agenda
• Abstract
• Introduction
– Why 8-bit gray code?
– Theory of 8-bit gray code encoder
– Background Information
• Summary of Results
• Project (Experimental) Details
• Results
• Cost Analysis
• Conclusions
2
Abstract
• 8 bit Gray Code Converter converts regular binary number to Gray
code numbers
• Binary Gray
• Operates at a clock frequency of 200 MHz
• Power: 6mW
• Area: 265mm x 150mm
• DFF
MS-Latch: Wn = 1.50, 1.65um, Wp = 2.55, 2.70 um
SL-Latch: Wn = 1.95, 1.65 um, Wp = 1.65, 2.70 um
• XOR
AOI: Wn = 1.5um, Wp = 2.7um
INV: Wn = 1.5um, Wp = 2.7um
3
Introduction
Why the Binary Gray Code Converter???
• First of all, it applies many of the concepts
from the class and lecture (EE-166)
• BGCC, is applied in many applications
• This project converts a series of binary
numbers to gray code numbers with the use
of XOR gates and DFF’s
4
Project Summary
• Picked an initial load capacitance (Cload)
• Partitioned the circuit into different
propagation delay times according to
gate/device requirements
• Created the schematic, symbol and layout
for each type of gate (XOR, MUX-DFF)
• Limits the amount of error that can occur
when several bits change between numbers
5
Conversion
• Decimal Binary Gray Code
0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
6
Project Details
• Binary to Gray
• Uniform cell heights of 30 μm
– 7 XOR gates
– 16 Mux based D-Flip Flops
7
Longest Path Calculations
Logic Gate Cg #CDNs #CDPs #LNs #LPs WN WP WN WP WN WP Cg
Level to (H.C) (H.C) (S) (S) (L) (L) of
Drive gate
1 NAND2 20 1 2 2 1 1.59 1.9 1.5 1.5 1.65 1.95 5.8
2 Driver 5.8 1 3 2 2 1.63 2.67 1.5 1.5 1.65 2.7 7.3
MUX
3 XOR 7.3 4 6 2 2 1.53 2.63 1.5 1.5 1.5 2.7 7
AOI
4 XOR 7 1 1 1 1 1.53 2.75 1.5 1.5 1.5 2.7 7.4
INV
5 MS- 7.4 1 2 2 1 1.47 2.5 1.5 1.5 1.5 2.65 13
NAND2
6 Driver 13 1 3 2 2 1.62 2.71 1.5 1.5 1.65 2.7 7
5ns
PHL .83ns Note: All widths are in microns
6 and capacitances in fF
8
Schematic (DFF)
9
Layout ( DFF)
10
Simulations (DFF)
11
Schematic (XOR)
12
Layout ( XOR)
13
Gray Code Schematic
14
Gray Code Layout
15
Verification
16
Gray Code Simulation
17
Cost Analysis
• We Spent Many Hours on this Project
– Verifying logic = 10 hrs
– Verifying timing = 30 hrs
– Layout = 25 hrs
– Post extracted timing = 5 hrs
18
Lessons Learned
• START EARLY!
• FOCUS in class
• START EARLY!!
• Utilize other students in the class
• START EARLY!!!
• Work as a TEAM efficiently
• START EARLY!!!!
19
Summary
• This Project explained the Fundamentals of
EE-166
• Taught us the Ins - and - Outs of basic
Design
• Less Power Used, Less Area Used
• Met Specifications
20
Acknowledgements
• Thanks to our families for putting up with
us for not being home.
• Thanks to Cadence Design Systems for the
VLSI lab
• Thanks to Synopsys for Software donation
• Dr. David Parent
• Thanks to the janitors/security for letting us
spend late hours in the labs.
21