ENGR 2720 Chapter 9

Document Sample
ENGR 2720 Chapter 9 Powered By Docstoc
					 ENGR 2720 Chapter 9
Counters and Shift Registers



                               1
  Counters and Shift Registers

• Counter: A Sequential Circuit that counts pulses.
  Used for Event Counting, Frequency Division,
  Timing, and Control Operations.
• Shift Register: A Sequential Circuit that moves
  stored data bits in a specific direction. Used in
  Serial Data Transfers, Arithmetic, and Delays.



                                                  2
              Counter Terminology
• A Counter is a digital circuit whose outputs progress in a
  predictable repeating pattern. It advances one state for
  each clock pulse.
• State Diagram: A graphical diagram showing the
  progression of states in a sequential circuit such as a
  counter.
• Count Sequence: The specific series of output states
  through which a counter progresses.
• Modulus: The number of states a counter sequences
  through before repeating (mod-n).
• Counter directions:
   – DOWN - count high to low (MSB to LSB)
   – UP - count low to high (LSB to MSB).
                                                           3
           Counter Modulus
• Modulus of a counter is the number of states
  through which a counter progresses.
• A Mod-12 UP Counter counts 12 states from
  0000 to 1011 (0 to 11 decimal). The process
  then repeats.
• A Mod-12 DOWN counter counts from 1011 (to
  0000 (11 to 0 decimal), then repeats.



                                                 4
             State Diagram
• A diagram that shows the progressive states of a
  sequential circuit.
• The progression from one state to the next state
  is shown by an arrow.
  – (0000  0001 0010).
• Each state progression is caused by a pulse on
  the clock to the sequential circuit.



                                                   5
     MOD 12 Counter State Diagram
• With each clock pulse the counter progresses by one
  state from its present position on the state diagram to the
  next state in the sequence.
• This close system of counting and adding is known as
  modulo arithmetic.




                                                            6
           Full-sequence Counter
• An n-bit counter that counts the maximum modulus (2n) is
called a full-sequence counter such as Mod 2, Mod 4,
Mod 8, etc.
• A 4-bit mod 16 UP counter that counts up from 0000 to
1111 is an example of a full-sequence counter.




                                                        7
           Truncated Counter
• An n-bit counter whose modulus is less than the
maximum possible is called a truncated sequence
counter, such as mod 3 (n = 2), mod 12 (n = 4).
• A 4-bit mod 12 UP counter that counts from 0000
to 1011 is an example of a truncated counter




                                                    8
           Counter Timing Diagram
        (Mod-16 Full-sequence Counter)
• Shows the timing relationships between the input clock
  and the outputs Q3, Q2, Q1, …Qn of a counter.
• For a 4-bit mod 16 counter, the output Q0 changes for
  every clock pulse, Q1 changes on every two clock
  pulses, Q2 on four, and Q3 on 8 clocks.
• The outputs (Q0  Q3) of the counter can be used as
  frequency dividers with Q0 = clock  2, Q1 = clock  4, Q2
  = clock  8, and Q3 = clock  16.




                                                           9
       Counter Timing Diagram
      (Mod-12 Truncated Counter
The outputs (Q0  Q3) of the counter can be
used as frequency dividers with Q0 = clock  2,
Q1 = clock  4, Q2 = clock  12, and Q3 = clock
 12.




                                                  10
            Synchronous Counters
• A counter whose flip-flops are all clocked by the same
  source and change state in synchronization.
• The memory section keeps track of the present state.
• The control section directs the counter to the next state
  using command and status lines.

                                    Directs to next state




                                     Present state

                                                              11
Designing a Synchronous Counter
1.   Define the problem. The circuit must
     count in binary sequence from 0000 to
     1011.
2.   Draw a state diagram




                                             12
Step 3 Designing a Synchronous Counter


                      Q            Q
                 Present State Next State   J   K       Coments
                      0            0        0   X   No change or reset
                      0            1        1   X    Nochange or set
                      1            0        X   1     Toggle or set
                      1            1        X   0    Toggle or reset




                                                                     13
   Designing a Synchronous Counter
Simplify the Boolean expression for each input




                                                 14
MOD-12 Synchronous Counter




                             15
 Analysis of Synchronous Counters
        (Unknown Modulus)
• Set equations for the (JK, D, T) inputs in terms of the
  Q outputs for the counter.
• Set up a table similar to the one in Table 9.5 and
  place the first initial state in the present state column
  (usually all 000).
• Use the initial state to fill in the Inputs that will cause
  this state on a clock pulse.
• Determine the result on each FF in the counter and
  place this in the next state.
• Enter the next state on the present state line 2 and
  repeat the process until you cycle back to the first
  initial state.
                                                                16
Analysis of Synchronous Counters
           (Unknown Modulus)




1.   Set equations for the (JK, D, T) inputs in
     terms of the Q outputs for the counter.
     J2 = Q1Q0 J1 = Q0 J0 = Q2’
     K2 = 1       K1 = Q0 K0 = 1

                                                  17
         Analysis of Synchronous Counters
                     (Unknown Modulus)


2.   Set up the state table. Place the first initial state in
     the present state column (usually all 000).
3.   Use the initial state to fill in the Inputs that will cause
     this state on a clock pulse.
4.   Determine the result on each FF in the counter and
     place this in the next state.
5.   Enter the next state on the present state line 2 and
     repeat the process until you cycle back to the first
     initial state.


                                                                   18
State Table (Steps 2-5)
 J 2 = Q 1 Q0   J 1 = Q0   J 0 = Q2 ’
  K2 = 1        K1 = Q0    K0 = 1




                                        19
  Analysis of Synchronous Counters
          (Unknown Modulus)


6. Draw the timing and state diagrams.




                                         20
            LPM Counters

LPM (Library of Parameterized Modules) Counters:
Refer to Chapter 9, Entering Simple LPM Counters
with the Quartus II Block Editor.




                                              21
     Shift Register (SR) Terminology
• Shift Register: A synchronous sequential circuit that
  will store and move n-bit data either serially or in
  parallel in a n-bit Register (FF).
• Left Shift: A movement of data from right to left in
  the shift register (toward the MSB). One bit shift per
  clock pulse.
• Right Shift: A movement of data from left to right in
  the shift register (toward the LSB). One bit shift per
  clock pulse.
• Rotation: Serial shifting (right or left) with the output
  of the last FF connected to the input of the first.
  Results in continuous circulation of SR data.
                                                              22
Shift Register Terminology




                             23
  4-bit Shift Register
(Configured to Shift Right)




                              24
Right Shifting a “1” Through a Shift Register




                                                25
Right Shifting “1s” to Fill a Shift Register




                                               26
Left Shifting a “1” Through a Shift Register




                                               27
Left Shifting “1s” to Fill a Shift Register




                                              28
           Bi-Directional Shift Register
• Uses a control input signal called direction to change
  circuit function from shift right to shift left.
• When DIR = 0, the path of Left_Shift_In is selected.
• When DIR = 1, it selects the Right_ Shift_In Path.




                                                           29
                      SR with Parallel Load
•   Similar to a Parallel Load Counter, the Shift Register is shown in Figure
    9.93.
•   Uses a 2-to-1 Mux (AND/OR) to control inputs to the FF in the SR. The
    input choice is from the previous FF Output or the Parallel Input.
•   When Load = 1, Parallel Data is loaded in on the next clock pulse.




                                                                                30
                    Universal SR
• Combines the basic functions of a Parallel Load SR with a
  Bi-Directional SR.
• Uses Two Control Inputs (S1,S0) to select the function




                                                        31
Universal SR Truth Table (S1/S0)

S 1 S 0 Function               D3      D2      D1         D0
 0    0 Hold                   Q3     Q2      Q1     Q0
 0    1 Shif t Left
           Shift Right       RSI *    Q3      Q2     Q1
 1           t Right
      0 Shif Shift Left        Q2     Q1      Q0    LSI **
 1    1 Load                   P3     P2      P1     P0
* RSI = Right-Shif t Input / ** LSI = Left-Shif t Input




                                                               32
     LPM Shift Registers

• Allows the use of a Programmable LPM
  shift register called lpm_shiftreg.
• Has various required and optional
  parameters that are defined, such as
  LPM_WIDTH… (Table 9.16 in text).
• Design approach is the same as for
  Counters using Structured VHDL.

                                     33
      Shift Register Counters
• Two types: Ring and Johnson
• Ring Counter: A serial Shift Register with
  feedback from the output of the last FF to
  the input of the first FF.
• Counter sequences are based on a
  continuous rotation of data through the
  SR.


                                               34
           4- Bit Ring Counters
• A basic Ring Counter is constructed of D-FF with a
  Feedback Loop.
• Data is initially loaded into the SR by using either Resets
  or Presets.
• The counter can circulate a 0 or 1 by loading a 1000 or
  0111.
• The Modulus of a Ring Counter is defined as the maximum
  number of unique states.
• Modulus is dependent on the initial load value {1000, 0100,
  0010, 0001} = Mod4 while {1010, 0101} = Mod2.
• Typically an N-FF Ring Counter has
  N-States, not 2N like a binary counter.




                                                                35
Circulating a “1” in a Ring Counter




                                      36
Circulating a “0” in a Ring Counter




                                      37
                  Johnson Counters
• Johnson Counter: A serial shift register with the complemented
  feedback from the output of the last FF to the input of the first
  FF.
• Same as the Ring Counter sequences based on a continuous
  rotation of data through the SR.
• Same as a Ring except that Q’ (Complement) is fed back to D3,
  not to Q0.
• Adds a complement or “twist” to the data and is called a Twisted
  Ring Counter.
• Usually Initialized with 0000 by a Clear.




                                                                      38
        Johnson Counters
• Typically has more states than a ring
  counter.
• Sequence of states = {0000, 1000,
  1100, 1110, 1111, 0111, 0011, 0001}.
• Maximum Modulus is 2n for a circuit with
  n flip-flops.



                                         39
Data Circulating in a 4-bit Johnson Counter




                                              40

				
DOCUMENT INFO
Shared By:
Categories:
Tags:
Stats:
views:7
posted:11/29/2011
language:English
pages:40