An introduction to PCI bridges
Modern PCI systems employ a workstation approach that puts the PCI
controller between the CPU and the caching subsystem. Thus the PCI controller
has a direct access to the CPU host bus. Very first advantage of the same is that
a faster path is available to the system designer, which can be run at almost the
CPU’s speed.
Integration of PCI into a Pentium based system design requires an all-in-
one controller to manage the transfer of address, control and data signals to and
from the CPU and other host devices. But while doing this, many factors have to
be considered, if a system has to be compatible with the previous designs and
peripheral subsystems. Lots of cache coherency issues arise, which must be
tackled to maintain a coherent system.
Intel has provided a solution to this by providing integrated host-to-PCI
bridges. These chipsets are directly connected to the host CPU and all other
subsystems are bridged to the CPU using the same IC. Following simplified block
diagram shows what typical functions are integrated in a typical host-to-PCI
bridge compatible with Pentium 60/66, P54C and P55C designs
Blocks of a PCI bridge
Host interface
The bridge must support direct interconnection to a specific CPU. For
example Pentium CPU has following signals as bus interface signals
Address bus a[31:0]
Byte enables be[7:0]#
Data bus d[63:0]
Address status ADS#
Burst transfer signal BRDY#
Bus hold signal AHOLD
In the absence of the bridge, the CPU would use these signals to
communicate with the external world. Now the bridge must be connected to
these signals and it must forward the same signals to the external devices as and
when required. The bridge should understand the timings used by the CPU and
the same should be preserved so that the devices connected after the CPU do
not see the difference.
PCI interface
This is the most obvious block present on a PCI bridge. The bridge
supports all the PCI signals and acts as the PCI bus controller for the CPU.
Efficiency of the complete system depends upon the efficiency of the bridge.
Nowadays, PCI bridges support PCI revisions 2.0 and 2.1 to achieve full
bandwidth of the PCI bus
Typical functions provided by the bridges are as follows…
PCI bus arbitration
PCI transfer buffering
Delayed transactions
Cache interface
With the introduction of the PCI Bridge as a separate bus master in
conventional CPU cache organization, cache coherency becomes complex affair.
This is because now the cache can be incoherent because of operations by
following blocks
CPU
I/o bus master
PCI controller
Other CPUs in the system
To make the things simple, the bridges put the l2 cache subsystem on
itself. This allows the cache to be modified in a coherent manner since the cache
management in behalf of l2 cache controller and the PCI controller is handled by
a single device. Now the entire bus references pass through the bridge and the
cache coherency is maintained.
Dram interface
Since the bridge is the common gate for the CPU and the other devices to
connect. The PCI Bridge also handles dram interface. For this to be done, the
bridge interprets the CPU interface signals and generates corresponding timing
and control signals to the memory subsystems. Typical signals required to
perform dram management are
Column and row strobe signals (CAS, RAS)
Data bus d[31:0]
Memory clock signals
ISA interface
ISA bus peripherals are widely being used till date. Introduction of a
complete PCI based system is hence an important business issue. To provide
compatibility, modern bridges have support to the ISA bus through another
chipset called b Intel as PCI ISA/IDE axelerators (PIIX). These chipsets provide
interface to ISA devices and also provide on chip controllers to interface IDE
devices and other standard ports like RS-232, Centronics and USB. Almost all
modern Pentium motherboards have a pair of host-to-PCI bridge and a PIIX chip.
These two can be prominently seen on the board. The pair is affectionately called
Northbridge and Southbridge.
Miscellaneous interface
Apart from the above stated major blocks, the bridge has to support other
functions so that the external peripherals can be accessed without problems.
These signals include various clock signals, reset signals, smm signals etc.
Study of Intel 430TX chipset
Following points discuss the set of features provided by an i430TX chipset
for Pentium CPU
Supports Pentium family of CPU running at 60/66 bus speed
Integrated data path for all components
PCI 2.1 compliant PCI interface running at fully synchronous, min
latency 30/33 MHz
Supports five PCI bus masters
Integrated dram controller for upto 256MB system dram
Supports FPM, EDO an SDRAM
Integrated l2 controller that can cache upto 64mb dram
Direct mapped write-back caching policy
Supports 256kb or 512kb pipeline burst SRAM cache
Power management features
Stops clock when no transaction on the PCI bus
Suspend-To-Disk and Suspend-To-Ram support
ACPI compatible SMM mode
324 pin MBGA design with integrated data paths and drivers for direct
interconnection with the peer devices
Paper by: Kiran Ghag