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					            QUESTION BANK

Digital Logic
Objective: Main Objective is to know
about properties of Logic gates, positive and
negative logic, basic gates and universal
gates, HDL
1.
Define Binary operator.                         02
2. out different postulate used for algebric
List                                            02
structure.
3.
Explain the commutative & Associative law       02
4.
Discuss the following theorems with             02
example
i) x+x=x ii) x.x=0 iii) x+1=1 iv) x.0=0 v)
x+xy=x vi) x(x+y) =x
Explain Duality principle with an example.
5.                                              02
Explain complement of function with an
6.                                              02
example
Define truth table
7.                                              02
Why NAND & NOR gates are called
8.                                              02
universal gates
Discuss canonical & standard forms of
9.                                              04
Boolean functions with an example
10.
Convert the following Boolean function to      04
Sum of Minterms for F=A+B1C
11.
Convert the following Boolean function         04
F=xy+x1z to product of Maxterm
Bring
12. out the difference between Canonical       04
& Standard forms
What
13. are logical gates,mention different        04
types of Logic gates
Explain the operation of different Logic
14.                                            04
gates with neat diagram
Demonstrate by means of Truth table the
15.                                            06
validity of following theorem of Boolean
algebra
i)Associative law ii) Demorgans law for
Validity iii) Distributive law
Simplify the following Boolean function to
16.                                            06
minimum no. of literals
i) xy+xy1 ii) (x+y) (x+y1) iii) xyz+x1y+xyz1
iv) y(wz1+wz)+xy v) (A+B)1 ((A1+B1)1
Reduce the Boolean Expression to required
17.                                            06
number of literal
i) BC+AC1+AB+BCD ii) [(CD1) + A
]1+A+CD+AB iii) [(A+C+D) (A+C+D1)
(A+C1+D) (A+B1)
Obtain Truth table for function
18.                                           06
F=xy+xy1+y1z
Convert the following to other canonical
19.
form                                          06
i) F(x,y,z) =(1,3,7) ii) F(A,B,C,D)=
(0,2,6,11,13,14) iii) F(x,y,z)
=(0,1,2,3,4,6,12)
Show
20. that dual of Exclusive-OR is equal to     06
its complement
Implement the following function
21.                                           *05
F=(CD+E) (A+B’) using Nand gates only.
Simplify the Boolean function F using don’t
22.                                           *10
care conditions d, in SOP and POS form
F=A’B’C + A’CD + A’BC
D=A’BC’D + ACD + AB’D’
Implement the following function with no
23.                                           *10
more than 2 NOR gates. Assume both
normal and complement inputs are available
F=A’B’C’+ AB’D + A’B’CD’
D=ABC+AB’D’
Simplify the following and then
24.                                           *08
complement using logic gates
 AB+ A(B+C)+B(B+C)
 [ AB’ ( C+BD) + A’B’] C
Realize using NAND and NOR gates only
25.                                           *08
AB’C + A’BC’ + AB
XYZ + XY’Z + X’Y’
Prove
26. the following using Boolean               *05
identities
 A+A’B = A+B
( A + B ) ( A + B’ ) ( A’ + C ) =AC
Simplify the following Boolean expression
27.                                           *10
using NAND gates only.
A’B’C’ + A’B’C’ + B’C’
( A + B’ + C ) ( A’ + B’ + C’ ) ( A’ + B )
 What are Universal gates ? Realize NOT,
28.                                           *06
OR, AND functions using Universal Gates.
Mention two categories of Boolean
29.                                           *08
expressions based on their structure. Write
these forms for any three variable
expression T ( x,y,z ).
Using
30. algebraic procedure realize the           *06
Boolean expression
F(w,x,y,z) = w z + w z ( x + y )
Determine the Minterm canonical formula
31.                                            *04
of the following:
  T ( x,y,z ) = x y + z + x y z
Prove
32. the Demorgan’s law x+y = x . y
using Boolean postulates and theorems.         *06
Implement the given Boolean function
33.
                                               08
using NAND gate (A+B1)(CD+E).
Implement the given Boolean function
34.
                                               08
using NOR gate A(B+CD)+BC1
Obtain the minimal sum for the following
35.
Boolean function
                                               *08
F(w,x,y,z) =m(0,1,3,5,7,9,11,14) + d(2, 8 ,
10, 12)
Simplify the Boolean function F using the
36.
don’t care conditions d, in 1. SOP 2. POS
                                               *10
F= A’B’C’ + A’CD + A’BC
D = ABC + AB’D’
Implement the following function with no
37.
more than two NOR gates. Assume that
both normal and complement inputs are
                                               *10
available.
F= A’B’C’+AB’D+A’B’CD’
D=ABC + AB’D’
Using
38. graphical procedure , obtain a nor-
gate realization of the Boolean expression   *06
F(w,x,y,z) = w’z + wz’( x + y’)
Prove
39. that if w’x+yz’=0 then
                                             *06
Wx+y’(w’+z’)= wx +xz +w’z’+w’y’z
Prove
40. the following laws using Boolean
expression
Xy+yz+x’z=xy+x’z
(x+y)(y+z)x’+z) = (x+y)(x’+z)
Implement the following function with no
41.
more than two nor gates. Assume that both
normal and complement inputs are
                                             10
available.
F=A’B’C’+AB’D+A’B’CD’
 d=ABC+AB’D’
Implement a full subtractor with two half
42.
                                             10
subtractors and an OR gate
Prove
43. the following consensus laws using
Boolean postulates
                                              4
       i) xy+yz+x’z = xy+x’z
       ii) (x+y)(y+z)(x’+z) = (x+y)(x’+z)
Prove
44. that if w’x+yz’ = 0 then
                                              6
Wx+y’(w’+z’) = wx+xz+x’z’+w’y’z
Mention the different methods available for
45.
manipulating Boolean formulas. Explain      10
any three in detail
Using
46. graphical procedure, obtain a nor-
gate realization of the Boolean expression   6
f(w,x,y,z) = w’z+wz’(x+y’)
Show
47. that A B C D
                                             4
=∑m(0,3,5,6,9,10,12,15)
Write
48. short notes on: Implies and subsumes 5
State
49. and explain with examples shannon’s
expansion and reduction theorems in          4
Boolean algebra
Simplify the following using Boolean
50.
theorems:
       i) f(x,y,z)=(x+y)[(x’(y’+z’)]’ +
                                             8
           (xy)’ +(xz)’
       ii) f(A,B,C) =
           (A+B+C)(A’+B+C)(A’+B+C’)
Transform each of the following canonical
51.
expressions into other canonical form in
decimal notation and express in simplified   8
form in decimal notation
       i) f(x,y,z)= =m(0,1,3,4,6,7)
      ii) F(w,x,y,z) = ΠM(0,1,2,3,4,6,12)
What
52. is don’t care condition? What are its
                                            4
advantages?
Obtain a NOR-gate realization of the
53.
Boolean function
      i) f(w,x,y,z)                         8
          =m(0,3,5,6,9,10,12,15)

Obtain a NAND-gate realization of the
54.
Boolean function                            8
f(A,B,C) = (A+B’+C)(A’+B’+C’)(A’+B)
Explain the importance of enable input
55.
                                            6
signal
Design and implement full subtractor using
56.
                                           10
NAND gates only
What
57. is high speed adder? Design and
                                            8
explain 2 bit carry lookahead adder

COMBINATIONAL LOGIC CIRCUITS
Objective: In this chapter we learn about
different methods of simplifying Boolean
functions, Postulates of theorems &
Boolean algebra. The laws such as
commutative,Associative
law,Identity,Inverse & Distributive Laws
will be known. Canonical & standard forms
of Boolean functions will be known.
Advantage Of using K-map method for 2,3
& 4 variables, Quine McCluskey method by
Determining Prime implicants (Tabulation
method) . Simplification of Product of
sums, Simplification of Boolean function
which includes don’t care conditions .

1.Given the function T (w,x,y,z) =           *
  m(1,3,4,5,7,8,9,11,14,15). Use K-Map      0
  to determine the set of the prime          8
  implicants. Indicate the essential prime
  implicants. Find three distinct minimal
  expressions for T.
2.Determine the set of prime implicants      *
  for the given function:-                   1
  F(v,w,x,y,z)                               6
  =m(13,15,17,18,19,20,21,23,25,27,29,
  31)+ Ф (1,2,12,24) and obtain the
  minimal expression.
3.Mention one advantage and one             *
  disadvantage of the Quine-McCluskey       1
  method for obtaining the prime            2
  implicants of a given Boolean function.
  Obtain all the prime implicants of the
  function.
  F(v,w,x,y,z) =
  m(4,5,9,11,12,14,15,27,30) +
  dc(1,7,25,26,31)
  Use Quine McCluskey method. Do you
  have any Essential Prime Implicants.
4.Mention different methods of              0
  simplifying Boolean functions             2
5.Discuss K-map & Quine McCluskey           0
  methods for simplification of Boolean     2
  expressions
6.Discuss K-map & Quine McCluskey           0
  methods                                   2
7.Write advantages of K-map over Quine      0
  McCluskey method                          2
8.Define term Don’t care condition          0
                                            2
9.Explain K-map representation in detail   *
  & discuss the merits & demerits          0
                                           6
 Explain the tabulation procedure in
10.                                        *
 detail & discuss merits & demerits        0
                                           6
 Compare K-map & Quine-Mcclusky
11.                                        *
 methods for simplification of Boolean     0
 Expression                                6
 Obtain the simplified expression in sum
12.                                        0
 of products for the following:            6
 i) F(A,B,C,D,E)                        =
      (0,1,4,5,16,17,21,25,29)
 ii) BDE+B1C1D+CDE+A1B1CE+A1B1
      C+B1C1D1E1
 iii) F(x,y,z)= x1z + w1xy1+w(x1y+xy1)
 Obtain simplified expression in SOP & 0
13.
 POS form                                  6
 i)
      x1z1+y1z1+yz1+xyz                ii)
      w1yz1+vw1z1+vw1x+v1wz+v1w1y1z1
          and draw gate implementation
 using AND & OR gates
 Using K-map simplify following 1
14.
 Boolean      expression     &      give   0
 implementation of same using
 i) NAND gates only
 ii) AND,OR & Invert gates for
 F(A,B,C,D)             =(2,4,8,16,31)+
 D(0,3,9,12,15,18)
 Using K-map obtain Simplified
15.                                        1
 expression in SOP & POS form of           0
 function
 F(A,B,C,D)=(A1+B1+C1+D1)
 (A1+B1+C+D1)             (A+B1+C+D1)
 (A+B+C+D1)(A+B+C+D)
 Simplify Boolean function using don’t
16.                                        1
 care condition for SOP & POS              0
 i) F=w1(x1y+x1y1+xyz)+x1z1(Y+w),
      d=w1x(y1z+yz1)+wyz
 ii) F=ACE+A1CD1E1+A1C1DE,            d=
      DE1+A1D1E+AD1E1
 Simplify the following Boolean function
17.                                        1
 using K-map method                        4
 i) xy+x1y1z1+x1yz1
 ii) x1yz+xy1z+xyz+xyz1
 iii) F=A1C+A1B+AB1C+BC
 iv) f                          (w,x,y,z)=
     (0,1,2,4,5,6,8,9,12,13,14)
 Simplify
18.            Boolean     function     by   1
 Tabulation method                           4
 i) F(A,B,C,D,E,F,G)= (20,28,52,60)
 ii) F(A,B,C,D,E,F,G)=
     (20,28,38,39,52,60,102,103,127)
  Give two simplified irredundant
19.                                          *
 expression         for       F(w,x,y,z)=    1
 (0,4,5,7,8,9,13,15)                        4
  Determine set of Prime implicants for
20.                                          *
 function                     F(w,x,y,z)=    1
 (0,1,2,5,7,8,9,10,13,15)                   4
 Implement following function with
21.                                          1
 NAND & NOR gates.use only four              4
 gates
 F=w1xz+w1yz+x1yz1+wxy1z,
 d=wxy+wyz
 Minimize the following function with
22.                                          1
 don’t care terms using Q.M. method          4
 i) f(A,B,C,D)=
     m(5,7,11,12,27,29)+d(14,20,21,22,
     23)
 ii) f(A,B,C,D)=
     m(1,4,6,9,14,17,22,27,28,)+d(12,1
     5,20,30,31)
 Implement the following function using
23.                                        1
 NAND gates f(X,Y,Z)= (0,6)               4
 Implement the following function using
24.                                        1
 NOR gates F(x+y1) (x1+y)z1                4
  Explain the Tabulation procedure in
25.                                        *
 detail & discuss the merits & demerits    1
                                           4
 Determine the set of Prime implicants *
26.
 for          function         F(w,x,y,z)= 1
 (0,1,2,5,7,8,9,10,13,15)                 4
 Find the minimal two level NOR 1
27.
 realization for each following function   4
 i) f(A,B,C)= m(1,4,6,8)
 ii) f(A,B,C,D,E)=
      m(3,5,7,12,23,27,28,30)
 Find the minimal two level NAND 1
28.
 realization for each following function   4
 iii) f(A,B,C)= m(0,2,3,7)
 iv) f(A,B,C,D,E)=
     m(4,5,6,7,25,27,29,31)
 Expand the following function into
29.                                        0
 canonical SOP form f( x1,x2,x3 ) = x1     6
 x3 + x2 x3 + x1 x2 x3
 Expand the following function into
30.                                        0
 canonical POS form F( W, X, Q) = (        6
 Q+W’ )
  ( X+Q’)
 With
31.       K-map       obtain  simplified   *
 expression in SOP                         0
  F              (A,B,C,D)             =   8
 Σ(7,99,10,11,12,13,14,15)
 Simplify the following Boolean function
32.                                        *
 using the tabulation method               1
 F(A,B,C,D)= Σ( 0,1,2,8,10,11,14,15)       2
 Determine the minimal SOP using the
33.                                        *
 tabulation method using only one          1
 decimal notation                          0
 F(A,B,C,D,E)                          =
 Σm(13,15,17,18,19,20,21,23,25,27,29,3
 1)+ Σd(1,2,12,24)
 Implement using K-map
34.                                        *
 F(A,B,C,D)                              =   1
 Σm(0,2,4,6,8,16,18,20,22,24,26,28,30+Σ      0
 Ø(3,7,11,15,19,23,27,31)
 Using K-map obtain the minimal SOP
35.                                          *
 and the minimal POS form of the             0
 function                                    8
 f(a, b, c, d) = Σm(1,2,3,5,6,7,8,13)
 What code is used to label the row
36.                                          *
 headings and the column headings of a       0
 K-map and why?                              4
 Mention one advantage and one
37.                                          *
 disadvantage of the Quine-McClusky          1
 method for obtaining the prime              2
 implicants of a given Boolean function.
 Obtain all the prime implicants of the
 function.
 F(v,w,x,y,z)                            =
 Σm(4,5,9,11,12,14,15,27,30)+dc(1,17,25
 ,26,31)
 Use Quine Mc Clusky method. Do you
 have any essential prime implicants.
 Using K-map simplify the following
38.                                          *
 Boolean        expression    and     give   1
 implementation of the same using the      0
 Nand gates only(SOP form) and Nor
 gates only(POS form).
 F(A,B,C,D) = Σ (0,1,2,4,5,12,14)+
 d(8,10)
 Explain the procedure for loading a K
39.                                        *
 map using MEV technique. Write the        1
 MEV K Map for the Boolean function        0
 F(w,x,y,z) = Σm(2,9,10,11,13,14,15)
 Using K-Maps, determine the minimal
40.                                        *
 sums and the minimal products for         0
 F(w,x,y,z) = пM(1,4,5,6,11,12,13,14,15)   8
 Is the answer unique?
 Explain the grouping and simplification
41.                                        *
 process in K map using 3-variable and 4   0
 variable map                              6

 Using K-map method simplify
42.
 following Boolean expression and give     *
 implementation of the same by using       1
 NAND and NOR gates only.                  0

   (i) The SOP form -
       F(a,b,c,d)= Σ (0,1,4,5,6,8,14,12)

   (ii) The POS expression is given by

         F(a,b,c,d)= π(2,3,6, 7,9,11,15)
 Minimize the following using K-maps:- *
43.
    (iii)The SOP expression is given by: - 1
                                           4
         F(a,b,c,d)= Σ
         m(0,1,2,3,5,9,14,15)+ΣΦ
         (4,8,11,12)
    (iv) The POS expression is given by

       F(a,b,c,d)= πM(0,1,5,8,9,10)
       Implement the minimal
       expressions thus obtained using
       basic gates(both normal and
       inverted inputs can be used)
 List
44. the differences between                *
 combinational and sequential logic        0
 circuits.                                 4
 Determine the set of prime implicates
45.                                        *
 for the given function                    1
 F(v,w,x,y,z)= Σ                           6
 m(13,15,17,18,19,20,21,23,25,27,29,31)
 + ΣΦ (1,2,12,4) and obtain minimal
 expression
 Simplify the given function by
46.                                        *
 tabulation method and list the prime      1
 implicants. Use decimal notation          0
 F(A,B,C,D)= Σm(0,1,4,5,8,10,11,12,14)
 + d(2,6)

 Obtain the minimal sum for the
47.                                        *
 following Boolean function using          1
 Tabulation method                         4
 F(a,b,c,d,e)=
 Σm(0,1,3,4,7,9,10,12,15,16,17,20,23,25,
 28,29,30,31)
 Using K-map, obtain simplified
48.                                        *
 expression in sum of products             0
 F(A, B, C, D)= Σ(7,9,10,11,12,13,14,15)   8
 Simplify the following Boolean function
49.                                        *
 by tabulation method                      !
 F(A, B, C, D)= Σ(0,1,2,8,10,11,14,15)     2
 Using K-map obtain the minimal sum
50.                                         *
 and the minimal Product for the function   1
 f(a, b, c, d) = Σm(0,1,3,7,8,12) +         0
 dc(5,10,13,14) is your answer unique?
 Using quine Mccluskey method and
51.                                         1
 prime implicant table reductions,          0
 determine the minimal sums for the
 incomplete Boolean function
 f(v,w,x,y,z)=
 Σm(4,5,9,11,12,14,15,27,30)            +
 dc(1,17,25,26,31)
 Explain the procedure for loading a k-
52.                                         1
 map using map entered variable             0
 technique. Write the map entered
 variable K-map for the Boolean function
 f(w,x,y,z)= Σm(2,9,10,13,14,15)
 Determine minimal SOP expression for
53.                                         8
 f(w,x,y,z)=           Σm(0,2,4,9,12,15)+
 Σd(1,5,7,10)
 Using quine Mccluskey method and
54.                                         8
 prime implicant table reductions,
 determine the minimal POS expression
 for the following using decimal notation
 f(v,w,x,y,z)= Σm(1,2,3,5,9,12,14,15) +
 dc(4,8,11)
 Reduce the given switching function 4
55.
 using variable map technique
 F(A, B, C, D)= Σm(0,1,4,7,10,14)
 Obtain minimal sum for the following
56.                                       1
 boolean function using tabulation        4
 method
 f(a,b,c,d,e)=m(0,1,3,4,7,9,10,12,15,16,
 17,20,23,25,28,29,30,31)

Data-Processing Circuits
Objective: To study about multiplexers,
demultiplexers, decoders, encoders, ROM,
PLA , PAL, PL. Also this chapter deals with
how errors can be detected and corrected
while transferring as well as receiving data.
Also HDL implementation of the above
circuits
 1.Discuss enable control inputs.         04

2.Explain the code conversion             04
  procedure.
3.Define parity generator and parity       06
  checker.

4.Give the main steps for designing        06
  combinational circuits.
5.Mention the limitations of designing     06
  logic circuit in practical design
  method
6.Explain code conversion , give           06
  Boolean function for converting BCD
  TO EXCESS-3 converter
  Give the logic diagram for the same.
7.Discuss about the analysis procedure     06
  for designing logic circuit.
8.Mention the steps to obtain output       06
  Boolean function, truth table from the
  logic diagram.
9.Discuss odd & even parity generation,    06
  checking with an example.
  Give the logic diagram for 3-bit odd
10.                                        06
  parity generator & checking.
  Design BCD to 7 segment decoder
11.                                        06
  using NAND gates only
 Design combinational circuit to check
12.                                         08
 for even parity of four bits. A logic 1
 output is required when four bits do
 not constitute an even parity.
 Using
13.         decoder    implement      the   10
 following Logic functions.
 i) Active High decoder with OR
      gate.
 ii) Active Low decoder with NAND
      gate.
 iii) Active High decoder with NOR
      gate.
 iv) Active Low decoder with AND
      gate.
 Design 2-4 decoder with enable input
14.                                         10
 E.
 Design 3-8 decoder
15.                                         10
 Design 4-16 decoder
16.                                         10
 Mention the application of decoder.
17.                                         10
 Design a code converter that converts
18.                                         10
 4-bit number from Grey code to
 binarycode.
 Given 3x8 decoder , show that
19.                                         *05
 construction of 4x16 decoder
 Give the truth table for half adder and
20.                                        *10
 full adder, develop the simplified
 expression for sum & carry of a full
 adder & realize the full adder using
 only half adder
  Design a EXCESS-3 code to BCD
21.                                        *10
 code using NAND gates only.
  Design a full adder & full subtractor
22.                                        *20
 ,give their truth table,simplified
 expression and circuit diagrams
  What is decoder,what are it’s
23.                                        *20
 advantages.Design a decimal decoder
 which converts information From
 BCD to DECIMAL.

 With a neat diagram explain the *10
24.
 internal logic construction of a 32X4
 ROM
 List the PLA table for the BCD to *10
25.
 Excess-3 Code converter.
 Explain the 4-bit parallel adder with *10
26.
 the carry look ahead scheme. Clearly
 indicate how this scheme improves the
 performance of the operation.
 Write short notes on Binary Full
27.                                       *05
 Subtractor.
 Implement a full adder circuit with a
28.                                       *05
 decoder and two OR gates
 Design a circuit that compares two 4-
29.                                       *05
 bit numbers A and B, to check if they
 are equal. The circuit has one output
 x, so that x=1 if A=B and x=0 if A ≠
 B.
 How does the architecture of PAL
30.                                       *10
 differ from ROM.
 What are the steps involved in design,
31.                                       10
 programming and testing of the PLD
 Implement the following Boolean
32.                                       *06
 expression using a PROM.
 F1( x2,x1,x0) = Σm(0,1,2,5,7)
 F2(x2,x1,x0) = Σm(1,2,4,6)
 Mention the different types of ROM
33.                                       10
 and explain each of them.
 With the help of block diagrams
34.                                       *04
 distinguish between a decoder and
 encoder.
 Give a 4-to-1 MUX implementation of
35.                                     *06
 the three variable function.
 F = Σm(1,4,5,7)
 Illustrate how a PLA can be used for
36.                                     *10
 the combinational logic design with
 reference to the functions
 F1(a,b,c) = Σm(0,1,3,4)
 F2(a,b,c) = Σm(1,2,3,4,5)
 Realize the same assuming that a
 3X4X2 PLA is available.
 Implement the Boolean expressions.
37.                                     *06
 F1(x2,x1,x0) = Σm(1,2,4,5) and
 f2(x2,x1,x0) = Σm(1,5,7) with a
 decoder and two OR gates.
 Implement the Boolean function
38.                                     *06
 f(w,x,y,z) = Σm(0,1,5,6,7,9,12,15)
 using 8-to-1 multiplexer.
 Write short notes on Programmable
39.                                     *05
 Read Only Memories (PROMS)
 Implement the following Boolean
40.                                     *08
 function with a multiplexer.
 F(a,b,c,d) = Σm(0,1,3,4,8,9,15)
 Implement the following Boolean
41.                                       *06
 expression using a PROM.
 F1(x2,x1,x0) = Σ m(0,1,2,5,7)
 F2(x2,x1,x0) = Σ m(1,2,4,6)
 Give a detailed short notes on PLAs
42.                                       *05
 Implement the following function,
43.                                       *10
 with an 8X1 Mux, with A,B and D
 connected to selection lines S2, S1
 and S0 respectively.
 F(A,B,C,D) = Σ(0,1,3,4,8,9,15)
 Design 8-bit magnitude comparator
44.                                       *06
 using          4-bit         magnitude
 comparator(7485)
 What is an encoder? Explain an 8-to-3
45.                                       4
 line encoder
 What is a PLA? Describe with a logic
46.                                       8
 diagram the the principle of operation
 of a PLA. What are its advantages?
 Implement the following function,
47.                                       6
 with an 8X1 Mux,
 F(A,B,C,D)
 =A’BD’+ACD+B’CD+A’C’D
 Design 8-bit magnitude comparator
48.                                       6
 using 4-bit magnitude comparator
 What is an encoder? Explain an 8-to-3 4
49.
 line encoder.

Arithmetic circuits

Objective: To learn about full adder, half
adder, half and full subtractor , binary
addition , subtraction, multiplication and
division. Also HDL implementation of the
above circuits
1 Discuss the full adder with an        04
    example.
2 Discuss the Half adder with an        04
    example.
3 Explain the code conversion           04
    procedure.
4 Define full adder & half adder,       06
    explain the working of it with an
    example.
5 Mention the difference between full 06
    and half adder.
6 Implement the full subtractor with       08
  two half adder and OR gate
7 Design a combinational circuit that      10
  converts 4-bit reflected code number
  to a four bit binary
  number,implement the circuit with
  EX-OR gates.
8 Design 2-bit adder circuit using two     10
  level NAND gate circuit for each
  output. the inputs are 2- bit binary
  number’s a1a0 & b1b0,the output’s
  are the 2-bit binary sum s1s0 & carry
  output c1 only.
9 Using only half adder , draw a circuit   10
     xi     yi     zi     Ci    Si




   that will add 3-bits xi, yi and zi
   together,
   producing carry & sum bits Si, Ci as
   shown in following table:
        0      0      0     0      0
        0      0      1     0      1
        0      1      0     0      1
        0      1      1     1      0
        1      0      0     0      1
        1      0      1     1      0
        1      1      0     1      0
        1      1      1     1      1
10   Give the truth table for half adder      *10
     and full adder, develop the simplified
     expression for sum & carry of a full
     adder & realize the full adder using
     only half adder
11    Design a full adder & full subtractor   *20
     ,give their truth table,simplified
     expression and circuit diagrams
12   Explain the 4-bit parallel adder with    *10
     the carry look ahead scheme. Clearly
     indicate how this scheme improves
     the performance of the operation.
13   Write short notes on Binary Full         *05
     Subtractor.
14   Implement a full adder circuit with a    *05
     decoder and two OR gates
15   Implement a Full subtractor with two     *10
     half subtractor and an OR gate.
16   Implement a full adder circuit with a    *05
     decoder and two OR gates.
17   Explain a 4-bit parallel adder with      10
     carry lookahead scheme.
18   Implement a full adder circuit with a    6
     3-to-8 line decoder and two OR gates
19   With a block diagram explain the         6
     principle of operation of a carry look
     ahead adder
20   Explain a 4-bit parallel adder with      10
     carry lookahead scheme


CLOCKS AND TIMING CIRCUITS
Objective: To study clock waveforms, TTL
clock, Schmitt trigger, pulse forming
circuits.

FLIPS FL0PS
Objective: The main objective of this
chapter is to design sequential circuits( i.e.
circuits which include memory elements).
Study of different flip-flops, Master slave
JK flip-flops. Study of different state
diagrams & state equations. Also HDL
implementation of flip flop.
 1. Mention the difference between
    combinational & sequential circuits with 0
    block diagram                             4
 2. Mention the difference between
    asynchronous & synchronous circuits 0
    with example.                             4
 3. Difference between Latch & Flip flop
    give example                              0
                                              4
 4. Define clocked sequential circuit.
                                              0
                                              4
 5. Difference between Characteristic &
    Excitation table.                         0
                                              4
 6. Clearly        distinguish      between 1
   synchronous & asynchronous circuits,     0
   Combinational & sequential ckts, Latch   *
   & flip-flop
7. Design mod-3 counter using Jk flip-      2
   flops sketch waveforms for outputs       0
   when clock is       Applied & verify     *
   it’s operations.
8. Show that clocked D flip-flop can be 0
   reduced by one gate                  5
9. Design BCD counter with JK flip flops1
                                        0
  Discuss why condition S=R=1 leads to 1
10.
  unstable condition for SR latch 0
  construct state diagram for following
  table, what is the logic equation for
  output variable Z.

               0   1

                    A       D/1     B/0
                        B           D/1
  C/0
                        C            D/1
  A/0
                      D              B/1
  C/0
  Examine 7476 Jk flip flop, discuss why 0
11.
  PRE1 & CLR1 inputs are refereed to as 5
  asynchronous inputs. While JK are
  called synchronous inputs.

  Discuss how unstable condition S=R=1 0
12.
  is avoided in storage latch of the 5
  following
               a) D latch b) JK flip flop
  c) T flip flop

  Give a block diagram of sequential
13.                                         0
  circuit employing register as a part of   8
  sequential circuit.
  Design synchronous BCD counter using
14.                                         0
  JK flip flops.                            8
  Construct Mod 12 counter using MSI
15.                                         1
  chip.                                     0
  Design a serial adder using sequential
16.                                         1
  logic procedure                           0
  Explain bi-directional shift register with
17.                                            1
  parallel load                                0
  Discuss asynchronous up/down counter
18.                                            1
  & explain presettable counter                0
  Explain Schmitt trigger
19.                                            1
                                               0
  Explain the operation of one shot
20.                                            0
  (Monostable multivibrator)                   8
  Write short notes on
21.                                            *
  a. Schmitt trigger, b. Race around           1
  condition c. Johnson counter                 2
  Distinguish between level triggering and
22.                                            *
  edge     triggering    explaining     the    0
  advantages.                                  5
  Write short notes on
23.                                            *
  a. Triggering of Flip-Flops, b. Sequence     0
  detector                                     8
  Give the details of a master slave S-R
24.                                            *
  flip flop . Draw the logic diagram.          1
  Explain the flip-flop action during the      0
  control signal. Also give the function
  table.
  Design the mod-6 synchronous binary *
25.
  counter having the following repeated        1
  binary sequence using clocked JK flip        0
  flops.
  0,4,2,1,6,0,4,………….
  Explain the different types of flip flops
26.                                            *
  along with their truth table. Also explain   0
  the Race-around condition in a flip-flop.    8
  Using the logic circuit, truth table and
27.                                            *
  the timing diagram explain the               1
  operation of a J-K flip flop . Show the      0
  excitation table and the Characteristic
  equation.
  Design a MOD-12 asynchronous
28.                                            *
  (ripple) up-counter using J-K flip flops.    1
  Explain the operation briefly using the      0
  timing-diagrams.
  Explain the 4-bit binary ripple counter
29.                                            *
  with the state diagram, timing diagram       1
  and logic diagram using J-K, flip flop       0
  that triggers on negative edge.
  Using T flip flops design Mod-10
30.                                            *
  synchronous up counter.                      1
                                               2
   Explain the operation of clocked JK
 31.                                           *
   Flip-Flop with AND and NOR gates            1
   with relevant characteristics table and     0
   equation                                    `
   Explain the different types of flip flops   8
4 along with their truth table. Also explain
9. the race around condition in a flip flop.
   With a neat logic diagram and timing        6
5 waveforms describe the operation of a
1 master-slave JK flip flop
   Using T flip flops design mod-10            1
5 synchronous up counter                       2
2

REGISTERS

Objective: The main objective is to know
the types of registers and applications. Also
register implementation in HDL.
 1.Explain registers                        08
 2.Design Universal 4 bit shift register   *10
 3.Write short note on universal shift       5
   register
4.Explain how the shift registers can be     08
  used as counters.
5.Mention the capabilities of shift          08
  register
  Explain universal shift register(74194)
6.Discuss shift registers.                   08
7.Discuss serial transfer of information     08
  from one register to other.
8.Give logic diagram of 4 bit bi-            10*
  directional shift register with parallel
  capability & briefly explain it’s
  operation.

9.Explain bi-directional shift register 10
  with parallel load


COUNTERS

Objective: The main objective is to know
the types of counters and applications. Also
counter design in HDL.
1 Design the binary counters having 10*
     following repeated binary sequence.
     Use IC flip flops Only              :
     0,4,2,1,6.
2    Design mod-3 counter using JK flip-     20*
     flops sketch waveforms for outputs
     when clock is applied & verify it’s
     operations.
3    Design a counter with following         10
     binary sequence
                  a) 0,1,2 b) 0,1,2,3,4 c)
     0,1,2,3,4,5,6
4    Mention the difference between          08
     ripple & synchronous counters.
5    Give logic diagram of 4-bit binary      10
     ripple counter & BCD Ripple counter
6    Give logic diagram of ring counter &    10
     Johnson counter
7    Discuss binary up/down counters         10
8    Construct mod –6 counter using MSI      10
     chip.
9    Design synchronous BCD counter          08
     using JK flip flops.
10   Construct Mod 12 counter using MSI      10
     chip.
11   Discuss     asynchronous     up/down    10
     counter & explain presettable counter
12   Design the mod-6 synchronous binary     *10
     counter having the following repeated
     binary sequence using clocked JK flip
     flops.
     0,4,2,1,6,0,4,………….
13   Design mod-12 down ripple counter       *06
14   Using T flip flops design Mod-10        *12
     synchronous up counter.
15   Using T flip flops design mod-10        12
     synchronous up counter


DESIGN OF SEQUENTIAL CIRCUIT

Objective: The main objective is to learn
how to design a sequential circuit-model
selection, design equations and circuit
diagrams and analysis and design of
asynchronous circuit.
D/A  CONVERSION               and      A/D
CONVERSION

Objective: The main objective is to learn
about conversion, accuracy, resolution in
A/D and D/A.

DIGITAL INTEGRATED CIRCUITS

Objective: The main objective of this
chapter is to study switching circuits, about
TTL , CMOS and interface between TTL
and CMOS.
 1. Explain with ckt diagram the working of a   *1
    four input Schottky TTL NAND gate           0
 2. Explain the terms as applied to TTL and     *1
    indicate their typical values.              0
    Noise Margin, Propagation Delay, Fan-out,
    Vtg parameters
 3. Bring out the advantages and dis-           *0
    advantages of CMOS over TTL                 6
 4. What do you understand by Schottky TTL      *1
    gate? Draw a std TTL gate and explain its   0
   working.
5. With a neat diag explain the operation of a   *1
   CMOS NOT, NAND and NOR gates.                 0
6. Mention the members of the TTL logic          *0
   family, compare their typical power           5
   dissipation per gate and propagation delay.
7. Illustrate the concept of fan-out by taking   *0
   loading consideration of the TTL gate.        5
8. Explain the principle of the enhancement      *0
   mode MOSFET                                   8
9. Draw the ckt diag and explain the operation   *1
   of the 2 input TTL NAND gate with             0
   Totempole output
10.With ckt explain a) NMOS NAND b)            *1
   NMOS NOR                                    0
11.Enumerate the different TTL subfamilies.    *0
                                               6
  Discuss how a resistor could be constructed *0
12.
  using MOSFET. Give the resistor              6
  characteristics.
  Explain the 2 utilities of an open collector *0
13.
  output of a TTL gate                         5
  Explain the operation of a two input TTL *0
14.
  nand gate with totem pole output with a       8
  neat circuit diagram.
  Explain with help of the a circuit diagram
15.                                             *0
  the operation of a two input CMOS nor-        6
  gate.
  What is the principle of operation of
16.                                             8
  schottky TTL? Explain with circuit
  diagram the operation of a schottky TTL
  A
17. TTL gate is generated to sink 10mA          6
  without exceeding an output voltage
  VOL=0.4V and to source 5mA without
  dropping below VOH=2.4V. If Iih=100mA
  at 2.4V and Iih=1 mA at 0.4V, calculate the
  0-state fan-outs
  Write short notes on i)comparison of logic
18.                                             5
  families. ii) CMOS inverter
  Explain with the help of a circuit diagram
19.                                             6
  the operation of a two input CMOS nor-
  gate

				
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