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					  EE207: Digital Systems I,
  Semester I 2003/2004



           CHAPTER 3 -ii:
    Combinational Logic Design –
Design Procedure, Encoders/Decoders
         (Sections 3.4 – 3.6)
                   Overview
n   Design Procedure
n   Code Converters
n   Binary Decoders
    n   Expansion
    n   Circuit implementation
n   Binary Encoders
n   Priority Encoders
Combinational Circuit Design
n   Design of a combinational circuit is the
    development of a circuit from a
    description of its function.
n   Starts with a problem specification and
    produces a logic diagram or set of
    boolean equations that represent the
    circuit.
            Design Procedure
1.   Determine the required number of inputs
     and outputs and assign variables to them.
2.   Derive the truth table that defines the
     required relationship between inputs and
     outputs.
3.   Obtain and simplify the Boolean function (K-
     maps, algebraic manipulation, CAD tools, …).
     Consider any design constraints (area, delay,
     power, available libraries, etc).
4.   Draw the logic diagram.
5.   Verify the correctness of the design.
            Design Example
n   Design a combinational circuit with 4
    inputs that generates a 1 when the # of
    1s equals the # of 0s. Use only 2-input
    NOR gates

                     …
More Examples - Code Converters

n   Code Converters transform/convert
    information from one code to another:
    n BCD-to-Excess-3       Code Converter
      n   Useful in some cases for digital arithmetic
    n BCD-to-Seven-Segment         Converter
      n   Used to display numeric info on 7 segment
          displays
BCD-to-Excess-3 Code Converter
 n   Design a circuit that converts a binary-
     coded-decimal (BCD) codeword to its
     corresponding excess-3 codeword.
 n   Excess-3 code: Given a decimal digit n, its
     corresponding excess-3 codeword (n+3)2
     Example:
        n=5 à n+3=8 à 1000excess-3
        n=0 à n+3=3 à 0011excess-3
 n   We need 4 input variables (A,B,C,D) and 4
     output functions W(A,B,C,D), X(A,B,C,D),
     Y(A,B,C,D), and Z(A,B,C,D).
BCD-to-Excess-3 Converter (cont.)
The truth table relating the input and output variables is shown below
Note that the outputs for inputs 1010 through 1111 are don't cares (n
shown here).
   Maps for BCD-to-Excess-3 Code Converter
The K-maps for are constructed using the don't care terms
BCD-to-Excess-3 Converter (cont.
Another Code Converter Example:
BCD-to-Seven-Segment Converter
n   Seven-segment display:
    n7  LEDs (light emitting diodes), each one
      controlled by an input             a
    n 1 means “on”, 0 means “off”
                                   f          b
    n Display digit “3”?
                                         g
      n Set a, b, c, d, g to 1
      n Set e, f to 0             e         c

                                      d
BCD-to-Seven-Segment Converter

n   Input is a 4-bit BCD code à 4 inputs (w,
    x, y, z).
n   Output is a 7-bit code (a,b,c,d,e,f,g) that
    allows for the decimal equivalent to be
    displayed.                  a
n   Example:                f    g   b
    n Input:0000BCD
    n Output: 1111110        e       c
      (a=b=c=d=e=f=1, g=0)
                                 d
BCD-to-Seven-Segment (cont.)
        Truth Table
Digit   wxyz   abcdefg   Digit   wxyz   abcdefg
 0      0000   1111110    8      1000    1111111
 1      0001   0110000    9      1001   111X011
 2      0010   1101101           1010   XXXXXXX
 3      0011   1111001           1011   XXXXXXX
 4      0100   0110011           1100   XXXXXXX
 5      0101   1011011           1101   XXXXXXX
 6      0110   X011111           1110   XXXXXXX
 7      0111   11100X0           1111   XXXXXXX
 ??
                Decoders
n   A combinational circuit that converts
    binary information from n coded inputs
    to a maximum 2n decoded outputs
    à n-to- 2n decoder
n   n-to-m decoder, m = 2n
n   Examples: BCD-to-7-segment decoder,
    where n=4 and m=7
ecoders (cont.)
to-4 Decoder
to-4 Active Low Decoder
                  data
                  data
3-to-8 Decoder
                 address
                 address
      3-to-8 Decoder (cont.)
n   Three inputs, A0, A1, A2, are decoded into
    eight outputs, D0 through D7
n   Each output Di represents one of the
    minterms of the 3 input variables.
n   Di = 1 when the binary number A2A1A0 = i
n   Shorthand: Di = mi
n   The output variables are mutually exclusive;
    exactly one output has the value 1 at any time,
    and the other seven are 0.
Implementing Boolean functions
       using decoders
n   Any combinational circuit can be constructed
    using decoders and OR gates! Why?
n   Here is an example:
    Implement a full adder circuit with a decoder
    and two OR gates.
n   Recall full adder equations, and let X, Y, and Z
    be the inputs:
    n   S(X,Y,Z) = X+Y+Z = Σm(1,2,4,7)
    n   C (X,Y,Z) = Σm(3, 5, 6, 7).
n   Since there are 3 inputs and a total of 8
    minterms, we need a 3-to-8 decoder.
Implementing a Binary Adder
      Using a Decoder
             S(X,Y,Z) = Sm(1,2,4,7)
             C(X,Y,Z) = Sm(3,5,6,7)
       Decoder Expansions
Larger decoders can be constructed using
a number of smaller ones.
     -> HIERARCHICAL design!
Example:
A 6-to-64 decoder can be designed using
four 4-to-16 and one 2-to-4 decoders.
How? (Hint: Use the 2-to-4 decoder to
generate the enable signals to the four 4-
to-16 decoders).
3-to-8 decoder using two 2-to-4 decoders
4-input tree decoder
                 Encoders
n   An encoder is a digital circuit that
    performs the inverse operation of a
    decoder. An encoder has 2n input lines
    and n output lines.
n   The output lines generate the binary
    equivalent of the input line whose value
    is 1.
Encoders (cont.)
             Encoder Example
n   Example: 8-to-3 binary encoder (octal-to-binary)




               A0 = D1 + D 3 + D5 + D7
               A1 = D2 + D 3 + D6 + D7
               A2 = D4 + D 5 + D6 + D7
Encoder Example (cont.)
Simple Encoder Design Issues
n    There are two ambiguities associated with
     the design of a simple encoder:
    1.   Only one input can be active at any given time. If
         two inputs are active simultaneously, the output
         produces an undefined combination (for example,
         if D3 and D6 are 1 simultaneously, the output of
         the encoder will be 111.
    2.   An output with all 0's can be generated when all
         the inputs are 0's,or when D0 is equal to 1.
          Priority Encoders
n   Solves the ambiguities mentioned above.
n   Multiple asserted inputs are allowed;
    one has priority over all others.
n   Separate indication of no asserted
    inputs.
Example: 4-to-2 Priority Encoder
          Truth Table
4-to-2 Priority Encoder (cont.)
n   The operation of the priority encoder is
    such that:
n   If two or more inputs are equal to 1 at
    the same time, the input in the highest-
    numbered position will take precedence.
n   A valid output indicator, designated by
    V, is set to 1 only when one or more
    inputs are equal to 1. V = D3 + D2 + D1 +
    D0 by inspection.
Example: 4-to-2 Priority Encoder
            K-Maps
Example: 4-to-2 Priority Encoder
         Logic Diagram
8-to-3 Priority Encoder
A Matrix of switches = Keypad
       C0   C1   C2   C3




      1     2    3    F    R0

      4     5    6    E    R1

      7     8    9    D    R2

      0     A    B    C    R3
Keypad Decoder IC - Encoder

                 COL.
                 4-bit

                           4-bit
                           Binary
1   2   3   F
                         (encoded
4   5   6   E   ROW
                4-bit
7   8   9   D

0   A   B   C
    Priority Interrupt Encoder
             Schematic
Interrupting   Interrupt
                                      Microprocessor
  Devices       Encoder
   Device A


   Device B                Req(1:0)


   Device C


   Device D
                           IntRq
Priority Encoding - Interrupt
           Requests
 Interrupting Device
 A     B     C    D    Req (1:0) IntRq
 0     0     0    0       00       0
 0     0     0    1       00       1
 0     0     1    0       01       1
 0     0     1    1       01       1
 0     1     0    0       10       1
Exercise: Complete this table?

				
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posted:11/27/2011
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