"Nano-Electronics: Top-Down Fabrication"
Nano-Electronics: Top-Down Fabrication Sanjay Banerjee, Ph.D. Director Microelectronics Research Center The University of Texas at Austin 1 Topics • Definition and History • Semiconductors • Semiconductor Manufacturing • Fabricating Semiconductors • Applications • Challenges and Possibilities • Summary 2 Definition and History Why Nano-Electronics? • Nano-electronics refers to man-made devices between 1-100 billionth (10-9) of a meter. • “Nano” is from Greek word nanus meaning dwarf. • Micro- and nano-electronics is based on semiconductors. • $250 billion global industry, feeding a $2 trillion electronics market in 2007; U.S. controls about 40% of the market. • Employs about 6 million in U.S.; about 600 thousand high-tech jobs are in Texas; ~20% of jobs in Austin are in high tech! • Median high-tech wages are ~$60k/yr, 2X average. • Supports information technology, defense, biosciences, and energy. 3 Definition and History, Continued Nano-Electronics • Nano-electronics generally refers to semiconductor or micro-electronic devices that have been shrunk to the nanoscale. Figure 2.1b: Integrated circuit of Atmel Figure 2.1: An etched silicon wafer. Diopsis 740 System on Chip showing memory blocks, logic, and input/output pads around the periphery. 4 Definition and History, Continued Moore‟s Law • Micro-electronics evolved into nano-electronics in accordance with Moore‟s Law. Figure 2.2: Moore‟s Law. 5 Semiconductors Electricity Flow Electricity flow in solids Conductors Semiconductors Insulators (metals) (silicon) (glass) High Medium/ controllable Low • Flow of charges gives rise to electrical current. • Current = (Voltage ÷ Resistance) or (~ Electric field X Conductance). • Opposite charges attract each other; like charges repel. • Charges can be stored in a capacitor. • Semiconductors have two types of current carriers: negatively charged electrons and positively charged “holes” (missing electrons). 6 Semiconductors, Continued Electrons and Holes: Doping in Semiconductors • If all chemical bonds are unbroken, semiconductors do not conduct current. • Thermal energy or chemical Figure 2.3a: Silicon lattice. “dopants” used to create extra electrons or missing electrons (holes). Figure 2.3b: Schematic of doped silicon. 7 Semiconductors, Continued Electrons and Holes: Doping in Semiconductors, Continued • Holes are like bubbles in filled bottle; electrons are like drops in empty bottle. Bubbles oo ● ● go up; drops fall down. oo o ● ● ● • Similarly, holes move in direction of electric field, electrons opposite to field. Figure 2.4: Electric field movement. 8 Semiconductor Manufacturing Manufacturing Environment To keep factory environment for fabricating semiconductors as sterile as possible: • HEPA filters are used in the recirculation of air. • All individuals entering „fab‟ must wear “bunny suits.” • Filtration of chemicals and gasses is required. • Strict manufacturing protocols are followed. Figure 2.5: Cleanroom. 9 Semiconductor Manufacturing, Continued Contamination Reduction • This photo shows an example of process equipment in the fab for wafer cleaning. • Wafer handling is automated using robots. Once again, cleanliness is critical in top-down fabrication of nano-electronic devices. Figure 2.6: Wafer cleaning equipment. 10 Fabricating Semiconductors Silicon Crystal Growth • Nanoelectronic circuits are made on 12” or 300 mm Si wafers, projected to increase to 450 mm wafers. • Czochralski process - most widely used technique for making single-crystal silicon. – A seed of single-crystal silicon contacts the top of molten silicon. – Seed slowly raised and atoms of molten silicon solidify in pattern of Figure 2.7a: Czochralski process. seed and extend single-crystal structure. • Silicon ingot sliced into thin wafers for further processing into PV cells. Figure 2.7b: Silicon ingot. 11 Fabricating Semiconductors, Continued Integrated Circuit Fabrication Rendering of a small standard cell with three metal layers (dielectric has been removed). • The sand-colored structures are metal interconnect, with the vertical pillars being contacts, typically plugs of tungsten. • The reddish structures are polysilicon gates, and the solid at the bottom is the crystalline silicon bulk. Figure 2.8: Integrated Circuit (IC) fabrication. 12 Fabricating Semiconductors, Continued Doping by Ion Implantation • One changes the electrical conductivity of semiconductors by shooting high-energy ions at thousands of electron volts of energy using implanters. Figure 2.9: Ion implantation setup with mass separator. 13 Fabricating Semiconductors, Continued Photolithography • The term “photolithography” comes from a Greek word meaning writing patterns on stone with light. Figure 2.10: Flash imprint lithography. 14 Fabricating Semiconductors, Continued Steps for PN Diode Junction Fabrication 1. Oxididize the Si sample. 2. Apply a layer of positive photoresist (PR) 3. Expose PR through Mask A. 4. Remove exposed PR. 5. Use reactive ion etch (RIE) to remove SiO2 in windows. 6. Implant boron through windows in the PR and SiO2 layers. 7. Remove PR and sputter Al onto surface. 8. Using PR and Mask B, repeat steps 2-4; etch away Al except in p-contact areas. Fig 2.11: PN diode junction fabrication schematic. 15 Fabricating Semiconductors, Continued Transistor Scaling Gate Poly Gate Sidewall Gate Oxide (dielectric) Source Drain Fig 2.12: Transistor schematic. • Increase switching speed (and profit/wafer ) decrease Lgate. • Decrease Lgate shrink all other dimensions (scaling). • New materials needed to meet requirements. 16 Applications MOSFETS • A three-terminal switch or device capable of voltage and/or current gain. n+ -poly G iD Source Drain + vD 1 kΩ Metal Contact Metal + - Gate (Source) Contact vG 15V (Drain) - S n+ -poly D SiO2 iD(mA) 1.0 V n+ n+ 20 P-well Isolation 15 Si 0.5 ID 10 Gate Oxide vG=0 5 5 10 15 20 vD(V) VD Figure 2.13: MOSFET. 17 Applications, Continued MOSFETs, Continued • Fabrication Steps Poly-Si gate Silicide SiO2 Gate oxide n- n- Lightly doped source & drain (a) p P (e) Glass (TEOS) n- n- (b) Metal P Glass (dialectic) Sidewall spacer SiO2 n- n- p (c) n- n- (f) n+ P n+ N+ implant S/D n- n- n+ n+ (d) p Figure 2.14: Fabrication steps of MOSFETs. 18 Applications, Continued 3-D Transistor Structures • Complicated MOSFET structures with gates on both sides of conducting channel. Top gate G 100 nm IBM ‘97 S D Drain Source Drain Bottom gate SiGe gate Nitride spacer Poly-SiGe Si fin Poly-SiGe SiO2 drain source Berkeley ‘99 S G D Buried oxide S Lucent ’99 Source G Poly-Si Epi Si 1000 A Gate Channel D Drain Figure 2.15: 3-D transistor structures. 19 Applications, Continued Complementary Metal Oxide Semiconductor (CMOS) • Modern nano-electronic circuits are based on CMOS. • Two types of transistors are used in tandem: n-type and p-type. Figure 2.16: CMOS schematic. 20 Applications, Continued CMOS, Continued • Output characteristics for complementary MOSFETs (CMOS). Figure 2.17: Illustration of cell phone size reduction from 1992 - 2004. 21 Applications, Continued CMOS, Continued • Inverter circuit: when input voltage is high, output voltage is low. input output Figure 2.18: CMOS inverter circuit. 22 Applications, Continued DRAMs and SRAMs • Semiconductor memory chips such as dynamic or static Random Access Memory (DRAMS, SRAMS) have different types of device structures for storing charges. • They are arranged in well- organized patterns of “rows” and “columns.” Figure 2.19: Principle of operation of DRAM read for simple 4 by 4 array. 23 Applications, Continued Non-Volatile Flash Memory Conventional Floating Gate Nanoparticle Floating Gate Soe • “Floating” gate used to store electrons for over 10 years without battery. • Presence or absence of electrons correspond to “1” or “0.” • Nanoparticle Floating Gate memory is much more reliable than Conventional Figure 2.20: Non-volatile flash memory. Floating Gate memory. •A defect discharges only one dot. 24 Challenges and Possibilities Desirable Attributes of Nanoswitches • Energy efficiency. • Speed (performance, noise). • Room T operation (non-equilibrium devices?). • Size (device/ wafer): capacitance, fan-out. • Gain; uni-directional signal flow (I/O isolation). • Reliability, manufacturability, cost. • CMOS compatibility (process, topology). 25 Challenges and Possibilities, Continued Nano Isn‟t Just Small, It Is Different! • Coulomb behavior leads to “multi-level” logic instead of simple binary logic. I (e/2RtC) 4 Without 3 2 Including 1 charging effects 2 4 6 8 Figure 2.21a: Coulomb blockade. Va (e/2C) Figure 2.22b: Coulomb staircase. 26 Challenges and Possibilities, Continued Nanotransistors Figure 2.23: Nano-sized transistors. 27 Challenges and Possibilities, Continued Taxonomy for Nano-Computing • New variables such as electron‟s quantum mechanical properties may be used for computations. Figure 2.24: Taxonomy for nano-computing schematic. 28 Challenges and Possibilities, Continued International Technology Roadmap for Semiconductors • Industry-wide view of future technology needs in specific areas. Figure 2.25: Distribution of ATP awards in ITRS technologies. 29 Challenges and Possibilities, Continued Emerging Technology Sequence • For new nanotechnologies to come into production by end of CMOS roadmap in 2020, investments in R&D are critical. Figure 2.26: Emerging technology sequence. 30 Challenges and Possibilities, Continued Fiber Optic Transmission Systems • Optical interconnects can overcome bandwidth limitations. Figure 2.27: Fiber optic network. 31 Challenges and Possibilities, Continued Organic Light Emitting Diodes (OLEDs) • Organic plastic materials can also have semiconducting properties. Figure 2.28: OLED screen. 32 Challenges and Possibilities, Continued Quantum Cellular Automata (QCA) • QCA are units of four dots at the corners of a square building block. Figure 2.29: QCA schematic. 33 Challenges and Possibilities, Continued Spintronics “Datta-Das Transistor” • Electrons quantum mechanically can be viewed as a spinning top which can point “up” or “down!” Figure 2.30: Spintronics. 34 Challenges and Possibilities, Continued Phasetronics • Electrons have “wave” character in quantum physics. • May exploit the “constructive” and “destructive” interference of waves for new types of transistors. Constructive Interference Destructive Interference Figure 2.31: Interference of waves. 35 Summary Nanoelectronics Frontiers • Nanoelectronics will impact - Information Technology - Health Industry - Defense - Energy - Plus more! Figure 2.32a: Nano-medicine. Figure 2.32b: Space transport utilizing nanotecnologies. 36