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					1. Project Title:                  Belle - II
2. WBS element No.:                1.3
3. WBS Owner:                      G. Varner - University of Hawaii
4. WBS Element Title:              Readout Systems
5. Task/Element Description:       Provide general scope statement of the WBS.
                               --> Design, prototype, fabrication, test, integration and assembly into final detector readout modules of
                                   high-performance, waveform-sampling (WFS) ASIC-based readout.




11/25/2011                                                   WBS Description                                                           1 of 19
A. Technical Objective
                            A statement of project objectives and goals is needed to clearly and concisely translate project mission and
                            expectations into corresponding project commitments and deliverables. Objectives are statements that describe
                            what this WBS will achieve and deliver. Objectives should be “SMART”: S pecific, M easurable, A chievable,
                            R ealistic, and T ime-Based. To be specific and tangible, objectives should be deliverable-based. The completion
                            of an objective should be evident through the creation of one or more deliverables. If the statement is at a high
                            level and does not imply the creation of a deliverable, it may be a goal instead. If the statement is too low-level
                            and describes features and functions, then it may be a requirement statement instead.


                         --> First generation R&D prototypes of iTOP, KLM, and beam monitoring readout have been produced. The remaining
                             R&D/prototyping work consists of 2 more phases. In Rev. B, the final form-factors of the readout PCBs and ASICs
                             will be fabricated and evaluated. In Rev. C, pre-production prototypes will be assembled, using candidate final
                             versions of all commercial and custom components, and evaluated versus all final engineering specifications.
                             Successful completion of Phase C prototyping is necessary prior to commitment for production fabrication. Due to
                             the use of Ball Grid Array and other difficult to assemble parts (for space reasons), all production boards will be
                             assembled in industry and checked/debugged at Belle II member institute laboratories. Subcomponents will be
                             individually tested and characterized prior to integration into Sub-detector Readout Modules (SRMs). SRMs are
                             the units that are directly integrated with opto-detector front-ends to form the (iTOP or eKLM) detector
                             instrumentation.
                             Integration of the SRMs and backend readout (FINESSE/COPPER) into fully-assembled detector sub-modules,
                             wherein cosmic ray calibration data can be taken completes this WBS element.
                             First generation R&D prototypes of iTOP, KLM, and beam monitoring readout have been produced. The remaining
                             R&D/prototyping work consists of 2 more phases. In Rev. B, more refined readout PCBs and ASICs will be
                             fabricated and evaluated. In Rev. C, pre-production prototypes will be assembled, using candidate final versions of
                             all commercial and custom components, and evaluated versus all final engineering specifications.
                             Successful completion of Phase C prototyping is necessary prior to commitment for production fabrication. Due to




11/25/2011                                                      A. Tech Objective                                                         2 of 19
B. Assumptions        Project assumptions are circumstances and events that need to occur for the project to be successful but are
                      outside the total control of the project team. They are listed as assumptions if there is a HIGH probability that they
                      will in fact happen. The assumptions provide a historical perspective when evaluating project performance and
                      determining justification for project-related decisions and direction.

                      In order to identify and estimate the required tasks and timing for the project, certain assumptions and premises
                      need to be made. Based on the current knowledge today, the project assumptions are listed below. If an
                      assumption is invalidated at a later date, then the activities and estimates in the project plan should be adjusted
                      accordingly

                  1   Funding for needed manpower will not limit provided schedule.
                  2   ASIC foundries will maintain a consistent production schedule.
                  3   Beam monitoring schedule depends on test beam availability.
                  4   Estimates for electromechanical development depend upon maintaining current detector envelope.
                  5
                  6
                  7
                  8
                  9
                 10




11/25/2011                                                 B. Assumption(s)                                                            3 of 19
C. Scope of Work Statement
                               In this section, you should clearly define the logical boundaries of the WBS element. Scope statements are used to
                               define what is within the boundaries of the project and what is outside those boundaries. Examples of areas that could
                               be examined include: facility design, construction, readiness assessment/startup, staff & equipment transition, etc.
                               The following types of information can be helpful:

                               • The types of deliverables that are in scope and out of scope (program requirements, current state assessment)
                               • The major life-cycle processes that are in scope and out of scope (analysis, design, testing)
                               • The types of data that are in scope and out of scope (quantity of work, performance criteria, safety and security
                               requirements)
                               • The data sources that are in scope and out of scope (labor, subcontract, travel, materials)
                               • The organizations that are in scope and out of scope ( support organizations, R&D organizations, DOE, state &
                               federal regulators)
                               • The major functionality that is in scope and out of scope (decision support, data entry, management reporting)

                               The scope section may be broken into parts dependent on the size and complexity of the scope.




                         WBS
                        1.3.01 Development (iTOP)
                           --> Finalize specifications for production boards being fabricated in iTOP WBS elements, 1.3.04. Does not include
                               development of KLM or beam monitoring systems, WBS 1.3.05-1.3.07. First generation R&D prototypes of iTOP
                               readout have been produced. The remaining R&D/prototyping work consists of 2 more phases. In Rev. B, fully
                               functional readout PCBs and ASICs will be fabricated and evaluated in cosmic and beam tests. In Rev. C, pre-
                               production prototypes will be assembled, using candidate final versions of all commercial and custom components, and
                               evaluated versus all final engineering specifications.
                               Successful completion of Phase C prototyping is necessary prior to commitment for production fabrication. Due to the
                               use of Ball Grid Array and other difficult to assemble parts (for space reasons), all production boards will be assembled
                               in industry and checked/debugged at Belle II member institute laboratories. Subcomponents will be individually tested
                               and characterized prior to integration into Sub-detector Readout Modules (SRMs). SRMs are the units that are directly
                               integrated with opto-detector front-ends to form the iTOP detector instrumentation.
                               Integration of the SRMs and backend readout (FINESSE/COPPER) into fully-assembled detector sub-modules,
                               Cosmic cosmic beam test (1/16th system): Construction and integration of a full
                      1.3.01.1 wherein ray and ray calibration data can be taken completes this WBS element. bar readout
                    1.3.01.1.1 Electromechanical design and engineering
                    1.3.01.1.2 HV board : PMT high voltage distribution
                    1.3.01.1.3 Front board: PMT-to-ASIC electromechanical interface
                    1.3.01.1.4 ASIC carrier: daughter card signal distribution interface for 4x ASIC daughter cards
                    1.3.01.1.5 BLAB3A (first revision ASIC) daughter card: single ASIC and services


11/25/2011                                                        C. Scope of Work                                                                   4 of 19
              1.3.01.1.6   Interface board: power regulation and clock jitter cleaning
              1.3.01.1.7   SCROD control and data collection module
              1.3.01.1.8   cPCI_DSP: Back-end data receiver and fast feature extraction module
              1.3.01.1.9   Prototype clock and JTAG programming distribution
             1.3.01.1.10   Prototype back-end trigger receiver and logic module
                1.3.01.2   ASIC Development (BLAB3B) : Integration of DACs and tri-state bus output
                1.3.01.3   Pre-production prototyping
              1.3.01.3.1   Electromechanical design and engineering
              1.3.01.3.2   HV board : PMT high voltage distribution
              1.3.01.3.3   Front board: PMT-to-ASIC electromechanical interface
              1.3.01.3.4   ASIC carrier: daughter card signal distribution interface for 4x ASIC daughter cards
              1.3.01.3.5   BLAB3B daughter card: single ASIC and services
              1.3.01.3.6   Interface board: power regulation and clock jitter cleaning
              1.3.01.3.7   SCROD control and data collection module
              1.3.01.3.8   DSP_FIN: Back-end FINESSE data receiver and fast feature extraction module for COPPER system
              1.3.01.3.9   TRIG_FIN: Back-end trigger receiver and logic module
             1.3.01.3.10   Test Fixtures
                  1.3.02   Development (barrel KLM: B-KLM, endcap KLM: E-KLM)
                     -->   Finalize specifications for production boards being fabricated in KLM scintillator-based systems (endcap KLM and layer
                           0,1 barrel KLM) WBS elements, 1.3.05 and 1.3.06.1-1.3.06.3. Does not include development of barrel KLM RPC
                           readout or beam monitoring systems, WBS 1.3.06.4 and 1.3.07. First generation R&D prototypes of KLM scintillator
                           readout have been produced. The remaining R&D/prototyping work consists of 2 more phases. In Rev. B, VME crate-
                           based readout PCBs and deeper sampling ASICs will be fabricated and evaluated in cosmic tests. In Rev. C, pre-
                           production prototypes will be assembled, using candidate final versions of all commercial and custom components, and
                           evaluated versus all final engineering specifications.
                           Successful completion of Phase C prototyping is necessary prior to commitment for production fabrication. Due to the
                           use of Ball Grid Array and other difficult to assemble parts (for space reasons), all production boards will be assembled
                           in industry and checked/debugged at Belle II member institute laboratories. Subcomponents will be individually tested
                           and characterized prior to integration into front-end integrated readout modules. These are the units that are directly
                           integrated with opto-detector front-ends to form the scintillator KLM detector instrumentation.
                           Integration of the detector front-ends and and backend readout (FINESSE/COPPER) into fully-assembled detector sub-
                1.3.02.1   modules, wherein cosmic ray calibration data can be taken, completes this WBS element.
                           Cosmic ray quadrant test, 150 channel system
              1.3.02.1.1   Electromechanical design and engineering
              1.3.02.1.2   Preamplifier cards: MPPC amplification
              1.3.02.1.3   Carrier board: 15x preamplifiers and voltage regulation
              1.3.02.1.4   TARGET daughter card: single 16 channel TARGET ASIC and services
              1.3.02.1.5   KLM motherboard: 9U VME module with 10x TARGET daughter cards and SCROD
                1.3.02.2   ASIC development (TARGET3): deep sampling readout



11/25/2011                                                    C. Scope of Work                                                                 5 of 19
               1.3.02.3   Pre-production prototyping
             1.3.02.3.1   Electromechanical design and engineering
             1.3.02.3.2   Preamplifier cards: MPPC amplification
             1.3.02.3.3   Carrier board: 15x preamplifiers and voltage regulation
             1.3.02.3.4   TARGET3 daughter card: single 16 channel TARGET3 ASIC and services
             1.3.02.3.5   KLM motherboard: 9U VME module with 10x TARGET3 daughter cards and SCROD
             1.3.02.3.6   Test Fixtures
                 1.3.03   Development (beam monitoring readout)
                    -->   Finalize specifications for production boards being fabricated for realtime beam parameter (size and collision timing)
                          monitoring, WBS element 1.3.07. First generation R&D prototypes of coded aperture imaging x-ray readout have been
                          produced. The remaining R&D/prototyping work consists of 2 more phases. In Rev. B, cPCI-based readout PCBs and
                          higher throughput sampling ASICs will be fabricated and evaluated at an ATF2 beamline. In Rev. C, pre-production
                          prototypes will be assembled, using candidate final versions of all commercial and custom components, and evaluated
                          versus all final engineering specifications.
                          Successful completion of Phase C prototyping is necessary prior to commitment for production fabrication. Due to the
                          use of Ball Grid Array and other difficult to assemble parts (for space reasons), all production boards will be assembled
                          in industry and checked/debugged at Belle II member institute laboratories. Subcomponents will be individually tested
                          and characterized prior to integration into beam diagnostic modules. These are the units that are directly integrated
                          with x-ray and optical detectors.
                          Integration of the detector front-ends and backend readout into fully-assembled beam diagnostic modules, wherein
                          verification data can be taken at the KEK Photon Factory, completes this WBS element.
               1.3.03.1   ATF2 x-ray monitor test, 64 channel system
             1.3.03.1.1   Electromechanical design and engineering
             1.3.03.1.2   Preamplifier cards: photodetector amplification
             1.3.03.1.3   STURM2 daughter card: single 8 channel STURM2 ASIC and services
             1.3.03.1.4   Beam monitor motherboard: standalone module with 8x STURM2 daughter cards and SCROD
               1.3.03.2   ASIC development (STURM3): higher throughput
               1.3.03.3   Pre-production prototyping
             1.3.03.3.1   Electromechanical design and engineering
             1.3.03.3.2   Preamplifier cards: photodetector amplification
             1.3.03.3.3   STURM3 daughter card: single 8 channel STURM3 ASIC and services
             1.3.03.3.4   Beam monitor motherboard: standalone module with 16x STURM3 daughter cards and SCROD
             1.3.03.3.5   Test Fixtures

                1.3.04 iTOP Readout System
                   --> Procurement of electronic components, assembly of boards and testing the boards prior to delivery to KEK.
                       Integration, testing and installation will occur in WBS 1.2.
              1.3.04.1 Front-end (subdetector readout module: SRM) board stack production



11/25/2011                                                   C. Scope of Work                                                                  6 of 19
             1.3.04.2   Back-end receiver and feature extraction (FINESSE DSP: DSP_FIN)
             1.3.04.3   Back-end trigger receiver and logic (FINESSE Trigger: TRIG_FIN)
               1.3.05   E-KLM Readout System
                  -->   Procurement of electronic components, assembly of boards and testing the boards prior to delivery to KEK.
                        Integration, testing and installation will occur in WBS 1.4.
             1.3.05.1   Front-end integrated readout modules
             1.3.05.2   Back-end receiver and feature extraction (FINESSE DSP: DSP_FIN)
             1.3.05.3   Back-end trigger receiver and logic (FINESSE Trigger: TRIG_FIN)
               1.3.06   B-KLM Readout System
                  -->   Procurement of electronic components, assembly of boards and testing the boards prior to delivery to KEK.
                        Integration, testing and installation will occur in WBS 1.5.
             1.3.06.1   Front-end integrated readout modules
             1.3.06.2   Back-end receiver and feature extraction (FINESSE DSP: DSP_FIN)
             1.3.06.3   Back-end trigger receiver and logic (FINESSE Trigger: TRIG_FIN)
             1.3.06.4   RPC front-end integrated modules (Indiana University)
               1.3.07   Beam Monitor Readout System
                  -->   Procurement of electronic components, assembly of boards and testing the boards prior to delivery to KEK.
                        Integration, testing and installation will occur in WBS 1.6. Not contained in estimate provided for March 15 review.

             1.3.07.1 Front-end integrated readout modules
             1.3.07.2 Back-end receiver and feature extraction (cPCI DSP: DSP_cPCI)




11/25/2011                                                 C. Scope of Work                                                                7 of 19
D. Deliverables/Schedule
                               In this section, you should identify the deliverables and steps or activities that lead up to the
                               completion of the deliverable. Using the WBS as the structure, work is assigned to responsible
                               individuals or organizations. For each lower level WBS element, partition the scope into major
                               activities, and then subdivide the major activities into lower level schedule activities and events.
                               Milestones have no duration. They are established to flag the start or completion of an important
                               activity or group of activities and represent the deliverables of the WBS element.


                                                                                                                                                  Finish
                      WBS                                               Activity/Milestone                                            Start Date
                                                                                                                                                   Date
                      1.3.01 Development (iTOP)                                                                                       3/25/2011 9/1/2012
                    1.3.01.1 Cosmic ray and beam test (1/16th system): Construction and integration of a full bar readout             3/25/2011 9/15/2011

                  1.3.01.1.1   Electromechanical design and engineering                                                               3/25/2011    9/15/2011
                  1.3.01.1.2   HV board : PMT high voltage distribution                                                               3/25/2011    4/30/2011
                  1.3.01.1.3   Front board: PMT-to-ASIC electromechanical interface                                                   3/25/2011    4/30/2011
                  1.3.01.1.4   ASIC carrier: daughter card signal distribution interface for 4x ASIC daughter cards                   3/25/2011    4/15/2011
                  1.3.01.1.5   BLAB3A (first revision ASIC) daughter card: single ASIC and services                                   3/25/2011    4/15/2011
                  1.3.01.1.6   Interface board: power regulation and clock jitter cleaning                                            3/25/2011    4/15/2011
                  1.3.01.1.7   SCROD control and data collection module                                                               3/25/2011    3/25/2011
                  1.3.01.1.8   cPCI_DSP: Back-end data receiver and fast feature extraction module                                    3/25/2011    3/25/2011
                  1.3.01.1.9   Prototype clock and JTAG programming distribution                                                      3/25/2011    3/25/2011
                 1.3.01.1.10   Prototype back-end trigger receiver and logic module                                                   3/25/2011    3/25/2011
                    1.3.01.2   ASIC Development (BLAB3B) : Integration of DACs and tri-state bus output                               11/1/2011    6/1/2012
                    1.3.01.3   Pre-production prototyping                                                                             11/1/2011    9/1/2012
                  1.3.01.3.1   Electromechanical design and engineering                                                               11/1/2011    9/1/2012
                  1.3.01.3.2   HV board : PMT high voltage distribution                                                               11/1/2011    1/1/2012
                  1.3.01.3.3   Front board: PMT-to-ASIC electromechanical interface                                                   11/1/2011    1/1/2012
                  1.3.01.3.4   ASIC carrier: daughter card signal distribution interface for 4x ASIC daughter cards                   4/1/2012     5/1/2012
                  1.3.01.3.5   BLAB3B daughter card: single ASIC and services                                                         4/1/2012     5/1/2012
                  1.3.01.3.6   Interface board: power regulation and clock jitter cleaning                                            11/1/2011    2/15/2012
                  1.3.01.3.7   SCROD control and data collection module                                                               11/1/2011    2/1/2012
                  1.3.01.3.8   DSP_FIN: Back-end FINESSE data receiver and fast feature extraction module for COPPER                  11/1/2011    3/1/2012
                               system
                  1.3.01.3.9   TRIG_FIN: Back-end trigger receiver and logic module                                                   11/1/2011    3/1/2012
                 1.3.01.3.10   Test Fixtures                                                                                          11/1/2011    3/1/2012
                      1.3.02   Development (barrel KLM: B-KLM, endcap KLM: E-KLM)                                                     3/25/2011    9/1/2011
                    1.3.02.1   Cosmic ray quadrant test, 150 channel system                                                           7/1/2011     9/1/2011
                  1.3.02.1.1   Electromechanical design and engineering                                                               3/25/2011    3/25/2011


11/25/2011                                                              D. Deliverables                                                                 8 of 19
             1.3.02.1.2   Preamplifier cards: MPPC amplification                                                 3/25/2011   3/25/2011
             1.3.02.1.3   Carrier board: 15x preamplifiers and voltage regulation                                3/25/2011   3/25/2011
             1.3.02.1.4   TARGET daughter card: single 16 channel TARGET ASIC and services                       3/25/2011   3/25/2011
             1.3.02.1.5   KLM motherboard: 9U VME module with 10x TARGET daughter cards and SCROD                3/25/2011   4/30/2011
               1.3.02.2   ASIC development (TARGET3): deep sampling readout                                      1/1/2012    8/1/2012
               1.3.02.3   Pre-production prototyping                                                             9/1/2011    10/1/2012
             1.3.02.3.1   Electromechanical design and engineering                                               1/1/2012    10/1/2012
             1.3.02.3.2   Preamplifier cards: MPPC amplification                                                 9/1/2011    11/1/2011
             1.3.02.3.3   Carrier board: 15x preamplifiers and voltage regulation                                9/1/2011    11/1/2011
             1.3.02.3.4   TARGET3 daughter card: single 16 channel TARGET3 ASIC and services                     2/1/2012    5/1/2012
             1.3.02.3.5   KLM motherboard: 9U VME module with 10x TARGET3 daughter cards and SCROD               3/1/2012    6/1/2012
             1.3.02.3.6   Test Fixtures                                                                          9/1/2011    6/1/2012
                 1.3.03   Development (beam monitoring readout)                                                  3/25/2011   5/1/2012
               1.3.03.1   ATF2 x-ray monitor test, 64 channel system                                             3/25/2011   11/1/2011
             1.3.03.1.1   Electromechanical design and engineering                                               3/25/2011   8/30/2011
             1.3.03.1.2   Preamplifier cards: photodetector amplification                                        3/25/2011   5/1/2011
             1.3.03.1.3   STURM2 daughter card: single 8 channel STURM2 ASIC and services                        4/15/2011   5/15/2011
             1.3.03.1.4   Beam monitor motherboard: standalone module with 8x STURM2 daughter cards and SCROD    6/1/2011    7/15/2011

               1.3.03.2   ASIC development (STURM3): higher throughput                                           10/1/2011   5/1/2012
               1.3.03.3   Pre-production prototyping                                                             10/1/2011   5/1/2012
             1.3.03.3.1   Electromechanical design and engineering                                               12/1/2011   5/1/2012
             1.3.03.3.2   Preamplifier cards: photodetector amplification                                        10/1/2011   12/1/2011
             1.3.03.3.3   STURM3 daughter card: single 8 channel STURM3 ASIC and services                        2/1/2012    4/1/2012
             1.3.03.3.4   Beam monitor motherboard: standalone module with 16x STURM3 daughter cards and SCROD   3/1/2012    5/1/2012

             1.3.03.3.5 Test Fixtures                                                                            12/1/2011 4/1/2012

                1.3.04    iTOP Readout System                                                                    9/1/2012    10/1/2013
              1.3.04.1    Front-end (subdetector readout module: SRM) board stack production                     9/1/2012    10/1/2013
              1.3.04.2    Back-end receiver and feature extraction (FINESSE DSP: DSP_FIN)                        9/1/2012    8/1/2013
              1.3.04.3    Back-end trigger receiver and logic (FINESSE Trigger: TRIG_FIN)                        9/1/2012    8/1/2013

                1.3.05    E-KLM Readout System                                                                   10/1/2012   8/1/2013
              1.3.05.1    Front-end integrated readout modules                                                   10/1/2012   4/1/2013
              1.3.05.2    Back-end receiver and feature extraction (FINESSE DSP: DSP_FIN)                        10/1/2012   8/1/2013
              1.3.05.3    Back-end trigger receiver and logic (FINESSE Trigger: TRIG_FIN)                        10/1/2012   8/1/2013

                1.3.06 B-KLM Readout System                                                                      10/1/2012 8/1/2013


11/25/2011                                                      D. Deliverables                                                   9 of 19
             1.3.06.1   Front-end integrated readout modules                              10/1/2012   4/1/2013
             1.3.06.2   Back-end receiver and feature extraction (FINESSE DSP: DSP_FIN)   10/1/2012   8/1/2013
             1.3.06.3   Back-end trigger receiver and logic (FINESSE Trigger: TRIG_FIN)   10/1/2012   8/1/2013
             1.3.06.4   RPC front-end integrated modules (Indiana University)             10/1/2012   8/1/2013

               1.3.07 Beam Monitor Readout System                                         5/1/2012    11/1/2012
             1.3.07.1 Front-end integrated readout modules                                5/1/2012    11/1/2012
             1.3.07.2 Back-end receiver and feature extraction (cPCI DSP: DSP_cPCI)       5/1/2012    11/1/2012




11/25/2011                                                  D. Deliverables                               10 of 19
E. Relationships/Interfaces        In this section, you should identify the deliverables from others that this WBS element
                                   needs to complete its work (inputs)and the deliverables that this element is preparing to
                                   meet a need in another area of the project (outputs). Identify the deliverable and the WBS
                                   element it goes to or comes from.

                                                                                                                                   Date
                       Inputs                                           Deliverable/Item                                                       From WBS
                                                                                                                                  Needed
                               1 Final iTOP quartz bar box mechanics                                                            11/1/2011    1.2.03
                               2
                               3
                               4
                               5
                               6
                               7
                               8
                               9
                              10

                                                                                                                                    Date
                      Outputs                                           Deliverable/Item                                                         To WBS
                                                                                                                                 Completed
                               1   iTOP SRMs                                                                                    10/1/2013    1.2.05
                               2   Endcap KLM front-end integrated readout modules                                              8/1/2013     1.4.04
                               3   Barrel KLM scintillator-based front-end integrated readout modules                           8/1/2013     1.5.06
                               4   Beam monitoring system front-end integrated readout modules                                  11/1/2012    1.6.07
                               5
                               6
                               7
                               8
                               9
                              10




11/25/2011                                                                E. Interfaces                                                               11 of 19
F. Cost Estimate

                                                                                       Non-Labor                                                      Labor
                                                                                                                                                                                       Grant
    WBS                        Title                 Description of Activity     Element           Cost          Name         Institution      Function        Hours       Cost
                                                                                                                                                                                      Funded?
        1.3.01 Development (iTOP)                                                           $ 111,500.00                                                               $ 149,080.44
      1.3.01.1 Cosmic ray and beam test (1/16th
               system): Construction and
               integration of a full bar readout

    1.3.01.1.1 Electromechanical design and         1) Complete first readout   Electromec 4000                                                                                                 Hourlies
               engineering                          module, validate and        hanical
                                                    produce three more.         and
                                                                                optical
                                                                                mounting
                                                                                hardware
                                                    2) Design                                              Marc Rosen      Hawaii           Sr. Engineer      80       $   5,188.00             Sr. Engineer    $ 64.85
                                                    3) Fabrication/Assembly                                Louis Ridley    Hawaii           Instr. Technician 120      $   1,568.40             Instr. Tech
                                                                                                                                                                                                                $ 13.07
    1.3.01.1.2 HV board : PMT high voltage          1) Design                                              TBD             Hawaii           Jr. Engineer      80       $   3,719.20             Jr. Engineer
               distribution                                                                                                                                                                                     $ 46.49
                                                    2) Fabrication              PCB Fab     500                                                                                                 Student Tech    $ 11.44
                                                    3) Assembly                 Pick-and-   500            Robin Caplett   Hawaii           Student Tech.     20       $     228.80             Postdoc
                                                                                Place                                                                                                                           $ 24.04
                                                    4) Evaluation                                          Kurtis Nishimura Hawaii          Postdoc           40       $     961.60             DSP Engineer
                                                                                                                                                                                                                $ 25.60
    1.3.01.1.3 Front board: PMT-to-ASIC             1) Design                                              TBD             Hawaii           Jr. Engineer      60       $   2,789.40             Software Engr
               electromechanical interface                                                                                                                                                                      $ 22.54
                                                    2) Fabrication              PCB Fab     500                                                                                                 Faculty         $ 62.46
                                                    3) Assembly                 Pick-and-   500            Robin Caplett   Hawaii           Student Tech.     20       $     228.80             Grad Student
                                                                                Place                                                                                                                           $ 11.14
                                                    4) Evaluation                                          Kurtis Nishimura Hawaii          Postdoc           20       $     480.80

    1.3.01.1.4 ASIC carrier: daughter card signal   1) Design                                              Gary Varner     Hawaii           Faculty           20       $   1,249.20 Yes
               distribution interface for 4x ASIC
               daughter cards
                                                    2) Fabrication              PCB Fab     1000
                                                    3) Assembly                 Pick-and-   500            Robin Caplett   Hawaii           Student Tech.     10       $     114.40
                                                                                Place
                                                    4) Evaluation                                          Kurtis Nishimura Hawaii          Postdoc           10       $     240.40

    1.3.01.1.5 BLAB3A (first revision ASIC)         1) Design                                              Louis Ridley    Hawaii           Instr. Technician 40       $     522.80
               daughter card: single ASIC and
               services
                                                    2) Fabrication              PCB Fab     1500
                                                    3) Assembly                 Pick-and-   1000           Robin Caplett   Hawaii           Student Tech.     10       $     114.40
                                                                                Place
                                                    4) Evaluation                                          Kurtis Nishimura Hawaii          Postdoc           10       $     240.40

    1.3.01.1.6 Interface board: power regulation    1) Design                                              Louis Ridley    Hawaii           Instr. Technician 60       $     784.20
               and clock jitter cleaning
                                                    2) Fabrication              PCB Fab     1000
                                                    3) Assembly                 Pick-and-   500            Robin Caplett   Hawaii           Student Tech.     20       $     228.80
                                                                                Place
                                                    4) Evaluation                                          Kurtis Nishimura Hawaii          Postdoc           20       $     480.80

    1.3.01.1.7 SCROD control and data collection    1) Design                                              TBD             Hawaii           Jr. Engineer      120      $   5,578.80
               module
                                                    2) Fabrication              PCB Fab     3000




11/25/2011                                                                                                     F. Cost                                                                                           12 of 19
                                                     3) Assembly                Pick-and-   1500    Robin Caplett   Hawaii    Student Tech.    20    $     228.80
                                                                                Place
                                                     4) Firmware                                    TBD             Hawaii    Jr. Engineer     640   $   29,753.60
                                                     5) Software                                    Andrew Wong     Hawaii    Software         80    $    1,803.20
                                                                                                                              Engineer
                                                     6) Evaluation                                  Kurtis Nishimura Hawaii   Postdoc          40    $     961.60

    1.3.01.1.8 cPCI_DSP: Back-end data receiver      1) Design                                      TBD             Hawaii    Jr. Engineer     40    $    1,859.60
               and fast feature extraction module

                                                     2) Fabrication             PCB Fab     4500
                                                     3) Assembly                Pick-and-   2000    Robin Caplett   Hawaii    Student Tech.    20    $     228.80
                                                                                Place
                                                     4) Firmware                                    TBD             Hawaii    Jr. Engineer     120   $    5,578.80
                                                     5) Software                                    Andrew Wong     Hawaii    Software         90    $    2,028.60
                                                                                                                              Engineer
                                                     6) Evaluation                                  TBD             Hawaii    Jr. Engineer     60    $    2,789.40
    1.3.01.1.9 Prototype clock and JTAG              1) Design                                      TBD             Hawaii    Jr. Engineer     40    $    1,859.60
               programming distribution
                                                     2) Fabrication             PCB Fab     1000
                                                     3) Assembly                Pick-and-   500     Robin Caplett   Hawaii    Student Tech.    10    $     114.40
                                                                                Place
                                                     4) Evaluation                                  Kurtis Nishimura Hawaii   Postdoc          16    $     384.64

   1.3.01.1.10 Prototype back-end trigger receiver   1) Design                                      TBD             Hawaii    Jr. Engineer     40    $    1,859.60
               and logic module
                                                     2) Fabrication             PCB Fab     2500
                                                     3) Assembly                Pick-and-   1500    Robin Caplett   Hawaii    Student Tech.    10    $     114.40
                                                                                Place
                                                     4) Firmware                                    Xin Gao         Hawaii    Grad Student     160   $    1,782.40
                                                     5) Software                                    TBD             Hawaii    Grad Student     160   $    1,782.40
                                                     6) Evaluation                                  TBD             Hawaii    Postdoc          80    $    1,923.20
      1.3.01.2 ASIC Development (BLAB3B) :           1) Design                                      Gary Varner     Hawaii    Faculty          80    $    4,996.80 Yes
               Integration of DACs and tri-state
               bus output
                                                     2) Fabrication             MOSIS       50000
                                                     3) Evaluation Board        Fab/Asse    4000    TBD             Hawaii    Jr. Engineer     40    $    1,859.60
                                                                                mbly
                                                     4) Evaluation                                  Kurtis Nishimura Hawaii   Postdoc          80    $    1,923.20

      1.3.01.3 Pre-production prototyping
    1.3.01.3.1 Electromechanical design and          1) Finalize thermal model Thermal      3000    Marc Rosen      Hawaii    Sr. Engineer     60    $    3,891.00
               engineering                           and create mockup.        model

                                                     2) Move from prototype     Model final 5000    Marc Rosen      Hawaii    Sr. Engineer     160   $   10,376.00
                                                     to production-grade        assembly
                                                     fabrication.
                                                     3) Assembly of prototype                       Louis Ridley    Hawaii    Instr. Technician 80   $    1,045.60




    1.3.01.3.2 HV board : PMT high voltage           1) Design                                      TBD             Hawaii    Jr. Engineer     40    $    1,859.60
               distribution
                                                     2) Fabrication             PCB Fab     1000
                                                     3) Assembly                Pick-and-   500     Robin Caplett   Hawaii    Student Tech.    10    $     114.40
                                                                                Place
                                                     4) Evaluation                                  Kurtis Nishimura Hawaii   Postdoc          20    $     480.80

    1.3.01.3.3 Front board: PMT-to-ASIC              1) Design                                      TBD             Hawaii    Jr. Engineer     20    $     929.80
               electromechanical interface



11/25/2011                                                                                              F. Cost                                                          13 of 19
                                                    2) Fabrication   PCB Fab     500
                                                    3) Assembly      Pick-and-   500    Robin Caplett   Hawaii    Student Tech.    10    $    114.40
                                                                     Place
                                                    4) Evaluation                       Kurtis Nishimura Hawaii   Postdoc          10    $    240.40

    1.3.01.3.4 ASIC carrier: daughter card signal   1) Design                           TBD             Hawaii    Instr. Technician 20   $    261.40
               distribution interface for 4x ASIC
               daughter cards
                                                    2) Fabrication   PCB Fab     1000
                                                    3) Assembly      Pick-and-   500    Robin Caplett   Hawaii    Student Tech.    10    $    114.40
                                                                     Place
                                                    4) Evaluation                       Kurtis Nishimura Hawaii   Postdoc          10    $    240.40

    1.3.01.3.5 BLAB3B daughter card: single ASIC 1) Design                              Louis Ridley    Hawaii    Instr. Technician 40   $    522.80
               and services
                                                 2) Fabrication      PCB Fab     1000
                                                 3) Assembly         Pick-and-   500    Robin Caplett   Hawaii    Student Tech.    10    $    114.40
                                                                     Place
                                                    4) Evaluation                       Kurtis Nishimura Hawaii   Postdoc          20    $    480.80

    1.3.01.3.6 Interface board: power regulation    1) Design                           Louis Ridley    Hawaii    Instr. Technician 40   $    522.80
               and clock jitter cleaning
                                                    2) Fabrication   PCB Fab     1000
                                                    3) Assembly      Pick-and-   500    Robin Caplett   Hawaii    Student Tech.    10    $    114.40
                                                                     Place
                                                    4) Evaluation                       Kurtis Nishimura Hawaii   Postdoc          20    $    480.80

    1.3.01.3.7 SCROD control and data collection    1) Design                           TBD             Hawaii    Jr. Engineer     80    $   3,719.20
               module
                                                    2) Fabrication   PCB Fab     3000
                                                    3) Assembly      Pick-and-   1500   Robin Caplett   Hawaii    Student Tech.    10    $    114.40
                                                                     Place
                                                    4) Firmware                         TBD             Hawaii    Jr. Engineer     80    $   3,719.20
                                                    5) Software                         Andrew Wong     Hawaii    Software         20    $     450.80
                                                                                                                  Engineer
                                                    6) Evaluation                       Kurtis Nishimura Hawaii   Postdoc          40    $    961.60

    1.3.01.3.8 DSP_FIN: Back-end FINESSE data 1) Design                                 TBD             Hawaii    Jr. Engineer     80    $   3,719.20
               receiver and fast feature extraction
               module for COPPER system

                                                    2) Fabrication   PCB Fab     2500
                                                    3) Assembly      Pick-and-   1500   Robin Caplett   Hawaii    Student Tech.    20    $    228.80
                                                                     Place
                                                    4) Firmware                         TBD             Hawaii    Jr. Engineer     160   $   7,438.40
                                                    5) Software                         Andrew Wong     Hawaii    Software         40    $     901.60
                                                                                                                  Engineer
                                                    6) DSP Code                         Lili Zhang      Hawaii    DSP Engineer     320   $   8,192.00
                                                    7) Evaluation                       TBD             Hawaii    Postdoc          80    $   1,923.20
    1.3.01.3.9 TRIG_FIN: Back-end trigger           1) Design                           TBD             Hawaii    Jr. Engineer     40    $   1,859.60
               receiver and logic module
                                                    2) Fabrication   PCB Fab     2500
                                                    3) Assembly      Pick-and-   1000   Robin Caplett   Hawaii    Student Tech.    10    $    114.40
                                                                     Place
                                                    4) Firmware                         Xin Gao         Hawaii    Grad Student     160   $   1,782.40
                                                    5) Software                         TBD             Hawaii    Grad Student     160   $   1,782.40
                                                    6) Evaluation                       TBD             Hawaii    Postdoc          80    $   1,923.20
   1.3.01.3.10 Test Fixtures                        1) Design                           TBD             Hawaii    Jr. Engineer     80    $   3,719.20
                                                    2) Fabrication   PCB Fab     5000




11/25/2011                                                                                  F. Cost                                                     14 of 19
                                                    3) Assembly           Pick-and-   1500    Robin Caplett   Hawaii   Student Tech.    40    $     457.60
                                                                          Place
                                                    4) Software                               Andrew Wong     Hawaii   Software         40    $     901.60
                                                                                                                       Engineer
                                                    5) Evaluation                             TBD             Hawaii   Postdoc          40    $      961.60
        1.3.02 Development (barrel KLM: B-KLM,                                        76000                                                   $   33,818.20
               endcap KLM: E-KLM)
      1.3.02.1 Cosmic ray quadrant test, 150
               channel system
    1.3.02.1.1 Electromechanical design and         1) Design                                 TBD             Hawaii   Jr. Engineer     40    $    1,859.60
               engineering
                                                    2) Prototypes         Jigs/Brack 2000
                                                                          ets
    1.3.02.1.2 Preamplifier cards: MPPC             1) Design                                 TBD             Hawaii   Instr. Technician 20   $     261.40
               amplification
                                                    2) Fabrication        PCB Fab     1000
                                                    3) Assembly                               Robin Caplett   Hawaii   Student Tech.     80   $     915.20
                                                    4) Evaluation                             Robin Caplett   Hawaii   Student Tech.     20   $     228.80
    1.3.02.1.3 Carrier board: 15x preamplifiers and 1) Design                                 Louis Ridley    Hawaii   Instr. Technician 40   $     522.80
               voltage regulation
                                                    2) Fabrication        PCB Fab     500
                                                    3) Assembly                               Robin Caplett   Hawaii   Student Tech.     20   $     228.80
                                                    4) Evaluation                             Robin Caplett   Hawaii   Student Tech.     20   $     228.80
    1.3.02.1.4 TARGET daughter card: single 16      1) Design                                 Louis Ridley    Hawaii   Instr. Technician 40   $     522.80
               channel TARGET ASIC and
               services
                                                    2) Fabrication        PCB Fab     1000
                                                    3) Assembly                               Travis          Hawaii   Student Tech.    40    $     457.60
                                                                                              Hishinuma
                                              4) Evaluation                                   TBD             Hawaii   Postdoc           40   $      961.60
    1.3.02.1.5 KLM motherboard: 9U VME module 1) Design                                       Louis Ridley    Hawaii   Instr. Technician 80   $    1,045.60
               with 10x TARGET daughter cards
               and SCROD
                                              2) Fabrication              PCB Fab     2000
                                              3) Assembly                                     Robin Caplett   Hawaii   Student Tech.    40    $      457.60
                                              4) Firmware                                     TBD             Hawaii   Jr. Engineer     80    $    3,719.20
                                              5) Software                                     Andrew Wong     Hawaii   Software         40    $      901.60
                                                                                                                       Engineer
                                                    6) Evaluation                             TBD             Hawaii   Postdoc          40    $      961.60
      1.3.02.2 ASIC development (TARGET3):          1) Design                                 Gary Varner     Hawaii   Faculty          80    $    4,996.80 Yes
               deep sampling readout
                                                    2) Fabrication        MOSIS       50000
                                                    3) Evaluation Board   Fab/Asse    4000    TBD             Hawaii   Jr. Engineer     40    $    1,859.60
                                                                          mbly
                                                    4) Evaluation                             TBD             Hawaii   Postdoc          80    $    1,923.20
      1.3.02.3 Pre-production prototyping
    1.3.02.3.1 Electromechanical design and         1) Design                                 TBD             Hawaii   Jr. Engineer     20    $     929.80
               engineering
                                                    2) Prototypes         Jigs/Brack 2000
                                                                          ets
    1.3.02.3.2 Preamplifier cards: MPPC             1) Design                                 TBD             Hawaii   Instr. Technician 20   $     261.40
               amplification
                                                    2) Fabrication        PCB Fab     1000
                                                    3) Assembly           Pick-and-   500
                                                                          Place
                                                    4) Evaluation                             Robin Caplett   Hawaii   Student Tech.     20   $     228.80
    1.3.02.3.3 Carrier board: 15x preamplifiers and 1) Design                                 Louis Ridley    Hawaii   Instr. Technician 20   $     261.40
               voltage regulation
                                                    2) Fabrication        PCB Fab     500




11/25/2011                                                                                        F. Cost                                                         15 of 19
                                                   3) Assembly                Pick-and-   500
                                                                              Place
                                                   4) Evaluation                                  Robin Caplett   Hawaii   Student Tech.     20   $     228.80
    1.3.02.3.4 TARGET3 daughter card: single 16    1) Design                                      Louis Ridley    Hawaii   Instr. Technician 20   $     261.40
               channel TARGET3 ASIC and
               services
                                                   2) Fabrication             PCB Fab     1000
                                                   3) Assembly                Pick-and-   500
                                                                              Place
                                               4) Evaluation                                      TBD             Hawaii   Postdoc          40    $      961.60
    1.3.02.3.5 KLM motherboard: 9U VME module 1) Design                                           TBD             Hawaii   Jr. Engineer     40    $    1,859.60
               with 10x TARGET3 daughter cards
               and SCROD
                                               2) Fabrication                 PCB Fab     2000
                                               3) Assembly                    Pick-and-   1000
                                                                              Place
                                                   4) Firmware                                    TBD             Hawaii   Jr. Engineer     40    $    1,859.60
                                                   5) Software                                    Andrew Wong     Hawaii   Software         20    $      450.80
                                                                                                                           Engineer
                                                   6) Evaluation                                  TBD             Hawaii   Postdoc          40    $      961.60
    1.3.02.3.6 Test Fixtures                       1) Design                                      TBD             Hawaii   Jr. Engineer     40    $    1,859.60
                                                   2) Fabrication             PCB Fab     5000
                                                   3) Assembly                Pick-and-   1500    Robin Caplett   Hawaii   Student Tech.    20    $     228.80
                                                                              Place
                                                   4) Software                                    Andrew Wong     Hawaii   Software         20    $     450.80
                                                                                                                           Engineer
                                                   5) Evaluation                                  TBD             Hawaii   Postdoc          40    $      961.60
        1.3.03 Development (beam monitoring                                               56500                                                   $   48,466.20   hardware =
               readout)                                                                                                                                           Nichibei
      1.3.03.1 ATF2 x-ray monitor test, 64 channel
               system
    1.3.03.1.1 Electromechanical design and        1) Design                                      Louis Ridley    Hawaii   Instr. Technician 80   $    1,045.60
               engineering
                                                   2) Prototypes              Evaluation 5000
                                                                              Board
    1.3.03.1.2 Preamplifier cards: photodetector   1) Design                                      Xi Zhao         Hawaii   Jr. Engineer     80    $    3,719.20
               amplification
                                                   2) Fabrication             PCB Fab     500
                                                   3) Assembly                                    Travis          Hawaii   Student Tech.    40    $     457.60
                                                                                                  Hishinuma
                                                   4) Simulation/Evaluation                       Xi Zhao         Hawaii   Jr. Engineer     120   $    5,578.80

    1.3.03.1.3 STURM2 daughter card: single 8      1) Design                                      Louis Ridley    Hawaii   Instr. Technician 40   $     522.80
               channel STURM2 ASIC and
               services
                                                   2) Fabrication             PCB Fab     1000
                                                   3) Assembly                                    Travis          Hawaii   Student Tech.    40    $     457.60
                                                                                                  Hishinuma
                                                   4) Evaluation                                  TBD             Hawaii   Postdoc           40   $     961.60
    1.3.03.1.4 Beam monitor motherboard:           1) Design                                      Louis Ridley    Hawaii   Instr. Technician 40   $     522.80
               standalone module with 8x
               STURM2 daughter cards and
               SCROD
                                                   2) Fabrication             PCB Fab     2000
                                                   3) Assembly                                    Robin Caplett   Hawaii   Student Tech.    40    $      457.60
                                                   4) Firmware                                    TBD             Hawaii   Jr. Engineer     80    $    3,719.20
                                                   5) Software                                    Andrew Wong     Hawaii   Software         20    $      450.80
                                                                                                                           Engineer
                                                   6) Evaluation                                  TBD             Hawaii   Postdoc          40    $     961.60




11/25/2011                                                                                            F. Cost                                                                  16 of 19
      1.3.03.2 ASIC development (STURM3):          1) Design                                              Gary Varner     Hawaii    Faculty          80    $    4,996.80 Yes
               higher throughput
                                                   2) Fabrication              MOSIS       30000
                                                   3) Evaluation Board         Fab/Asse    3000           TBD             Hawaii    Jr. Engineer     40    $    1,859.60
                                                                               mbly
                                                   4) Evaluation                                          TBD             Hawaii    Postdoc          40    $     961.60
      1.3.03.3 Pre-production prototyping
    1.3.03.3.1 Electromechanical design and        1) Design                                              TBD             Hawaii    Jr. Engineer     40    $    1,859.60
               engineering
                                                   2) Prototypes               Carrier     5000
                                                                               PCB
    1.3.03.3.2 Preamplifier cards: photodetector   1) Design                                              Xi Zhao         Hawaii    Jr. Engineer     40    $    1,859.60
               amplification
                                                   2) Fabrication              PCB Fab     500
                                                   3) Assembly                                            Travis          Hawaii    Student Tech.    20    $     228.80
                                                                                                          Hishinuma
                                                   4) Simulation/Evaluation                               Xi Zhao         Hawaii    Jr. Engineer     60    $    2,789.40

    1.3.03.3.3 STURM3 daughter card: single 8      1) Design                                              Louis Ridley    Hawaii    Instr. Technician 40   $     522.80
               channel STURM3 ASIC and
               services
                                                   2) Fabrication              PCB Fab     1000
                                                   3) Assembly                                            Travis          Hawaii    Student Tech.    40    $     457.60
                                                                                                          Hishinuma
                                                   4) Evaluation                                          TBD             Hawaii    Postdoc           40   $     961.60
    1.3.03.3.4 Beam monitor motherboard:           1) Design                                              Louis Ridley    Hawaii    Instr. Technician 40   $     522.80
               standalone module with 16x
               STURM3 daughter cards and
               SCROD
                                                   2) Fabrication              PCB Fab     2000
                                                   3) Assembly                                            Robin Caplett   Hawaii    Student Tech.    40    $      457.60
                                                   4) Firmware                                            TBD             Hawaii    Jr. Engineer     80    $    3,719.20
                                                   5) Software                                            Andrew Wong     Hawaii    Software         20    $      450.80
                                                                                                                                    Engineer
                                                   6) Evaluation                                          TBD             Hawaii    Postdoc          80    $    1,923.20
    1.3.03.3.5 Test Fixtures                       1) Design                                              TBD             Hawaii    Jr. Engineer     80    $    3,719.20
                                                   2) Fabrication              PCB Fab     5000
                                                   3) Assembly                 Pick-and-   1500           TBD             Hawaii    Student Tech.    40    $     457.60
                                                                               Place
                                                   4) Software                                            TBD             Hawaii    Software         40    $     901.60
                                                                                                                                    Engineer
                                                   5) Evaluation                                          TBD             Hawaii    Postdoc          40    $     961.60

        1.3.04 iTOP Readout System                                                         $ 612,400.00                                                    $   38,456.00
      1.3.04.1 Front-end (subdetector readout      1) Fabrication and          Complete    528000
               module: SRM) board stack            Assembly (PCBs and          SRMs
               production                          ASICs)
                                                   2) Production                                          Marc Rosen      Hawaii    Sr. Engineer     80    $    5,188.00
                                                   engineering (mechanics)


                                                   3) Production                                          TBD             Hawaii    Jr. Engineer     80    $    3,719.20
                                                   engineering (electronics)


                                                   4) Quality Control                                     TBD             Hawaii    Jr. Engineer     160   $    7,438.40

                                                   5) Verification                                        Kurtis Nishimura Hawaii   Postdoc          320   $    7,692.80




11/25/2011                                                                                                    F. Cost                                                          17 of 19
      1.3.04.2 Back-end receiver and feature         1) Fabrication and          Full back-   60800
               extraction (FINESSE DSP:              Assembly                    end
               DSP_FIN)
                                                     2) Production engineering                               TBD             Hawaii    Jr. Engineer   40    $    1,859.60

                                                     3) Quality Control                                      TBD              Hawaii   Jr. Engineer   80    $    3,719.20
                                                     4) Verification                                         Kurtis Nishimura Hawaii   Postdoc        80    $    1,923.20

      1.3.04.3 Back-end trigger receiver and logic   1) Fabrication and          Full back- 23600
               (FINESSE Trigger: TRIG_FIN)           Assembly                    end trigger

                                                     2) Production engineering                               TBD             Hawaii    Jr. Engineer   40    $    1,859.60

                                                     3) Quality Control                                      TBD             Hawaii    Jr. Engineer   80    $    3,719.20
                                                     4) Verification                                         TBD             Hawaii    Grad Student   120   $    1,336.80

        1.3.05 E-KLM Readout System                                                           $ 250,000.00                                                  $   21,608.00
      1.3.05.1 Front-end integrated readout          1) Fabrication and          Full         156000
               modules                               Assembly (PCBs and          integrated
                                                     ASICs)                      front-end
                                                                                 modules
                                                     2) Production engineering                               TBD             Hawaii    Jr. Engineer   40    $    1,859.60

                                                     3) Quality Control                                      TBD             Hawaii    Jr. Engineer   120   $    5,578.80
                                                     4) Verification                                         TBD             Hawaii    Postdoc        120   $    2,884.80
      1.3.05.2 Back-end receiver and feature         1) Fabrication and        Full back-     53200
               extraction (FINESSE DSP:              Assembly (PCBs and        end
               DSP_FIN)                              FPGAs)
                                                     2) Production engineering                               TBD             Hawaii    Jr. Engineer   40    $    1,859.60

                                                     3) Quality Control                                      TBD             Hawaii    Jr. Engineer   40    $    1,859.60
                                                     4) Verification                                         TBD             Hawaii    Postdoc        80    $    1,923.20
      1.3.05.3 Back-end trigger receiver and logic   1) Fabrication and        Full back- 40800
               (FINESSE Trigger: TRIG_FIN)           Assembly (PCBs and        end trigger
                                                     FPGAs)
                                                     2) Production engineering                               TBD             Hawaii    Jr. Engineer   40    $    1,859.60

                                                     3) Quality Control                                      TBD             Hawaii    Jr. Engineer   40    $    1,859.60
                                                     4) Verification                                         TBD             Hawaii    Postdoc        80    $    1,923.20



        1.3.06 B-KLM Readout System                                                           $ 91,500.00                                                   $   35,333.40
      1.3.06.1 Front-end integrated readout          1) Fabrication and          Full         31000
               modules                               Assembly (PCBs and          integrated
                                                     ASICs)                      front-end
                                                                                 modules
                                                     2) Production engineering                               TBD             Hawaii    Jr. Engineer   20    $     929.80

                                                     3) Quality Control                                      TBD             Hawaii    Jr. Engineer   40    $    1,859.60
                                                     4) Verification                                         TBD             Hawaii    Postdoc        40    $      961.60
      1.3.06.2 Back-end receiver and feature         1) Fabrication and        Full back-     10800
               extraction (FINESSE DSP:              Assembly (PCBs and        end
               DSP_FIN)                              FPGAs)
                                                     2) Production engineering                               TBD             Hawaii    Jr. Engineer   20    $     929.80

                                                     3) Quality Control                                      TBD             Hawaii    Jr. Engineer   20    $     929.80
                                                     4) Verification                                         TBD             Hawaii    Postdoc        40    $     961.60




11/25/2011                                                                                                       F. Cost                                                    18 of 19
      1.3.06.3 Back-end trigger receiver and logic   1) Fabrication and        Full back- 9700
               (FINESSE Trigger: TRIG_FIN)           Assembly (PCBs and        end trigger
                                                     FPGAs)
                                                     2) Production engineering                               TBD         Hawaii        Jr. Engineer   20    $     929.80

                                                     3) Quality Control                                      TBD         Hawaii        Jr. Engineer   20    $     929.80
                                                     4) Verification                                         TBD         Hawaii        Postdoc        40    $     961.60

      1.3.06.4 RPC front-end integrated modules                                               40000          TBD         Indiana       Sr. Engineer   400   $   25,940.00
               (Indiana University)

       1.3.07 Beam Monitor Readout System                                                     $ 189,000.00                                                  $   19,466.80   hardware =
                                                                                                                                                                            Nichibei
      1.3.07.1 Front-end integrated readout          1) Fabrication and          Full         132000
               modules                               Assembly (PCBs and          integrated
                                                     ASICs)                      front-end
                                                                                 modules
                                                     2) Production engineering                               TBD         Hawaii        Jr. Engineer   40    $    1,859.60

                                                     3) Quality Control                                      TBD         Hawaii        Jr. Engineer   80    $    3,719.20
                                                     4) Verification                                         TBD         Hawaii        Postdoc        120   $    2,884.80
      1.3.07.2 Back-end receiver and feature         1) Fabrication and          Full back-   57000
               extraction (cPCI DSP: DSP_cPCI)       Assembly                    end

                                                     2) Production engineering                               TBD         Hawaii        Jr. Engineer   40    $    1,859.60

                                                     3) DSP Code                                             TBD         Hawaii        Jr. Engineer   80    $    3,719.20
                                                     4) Quality Control                                      TBD         Hawaii        Jr. Engineer   40    $    1,859.60
                                                     5) Verification                                         TBD         Wayne State   Grad Student   320   $    3,564.80




11/25/2011                                                                                                     F. Cost                                                                   19 of 19

				
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