Design and System Driver Chapters
ITRS Conference
July 2004
San Francisco, CA
Europe Ralf Brederlow, Wolfgang Ecker
Japan Ichiro Yamamoto, Tamotsu Hiwatashi,
Koichiro Ishibashi, Yoshimi Asada
Taiwan Charlie Chen
U.S. Juan-Antonio Carballo, Andrew Kahng, Valeria
Bertacco
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference 1
Overview
Why design
– Design cost is still a threat to economic viability
– Design is a key lever to address power challenge
– Design is the missing link in manufacturability
Major focus areas
– Derive quantitative, detailed design technology
requirements and solutions
• Detailed tables
– Address Design-Manufacturing interface challenges
• New section and model
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference 2
Design TWG Chapters
Productivity
Design Chapter Power
– Crosscutting challenges (design cost) DFM
– DT challenges Interference
• Design Process Reliability
• System-level Design
• Logical, Circuit, and Physical Design
• Design verification
• Design Test
– Additional / Cross-cut issues
System Driver Chapter
– Market Drivers
– System on Chip Driver
• SOC Multi-technology
• SOC High-performance
• SOC Low-cost, Low-power
– Microprocessor (MPU) Driver
– Mixed-signal Driver
– Embedded Memory Driver
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference 3
2004-2005 ITRS Design Goals
Goal 2004 2005
Develop -General requirements and - Detailed tables, by grand
color tables solutions tables challenge
Revise tables -Addition of DFM section -DFM variability model,
and content (content) detailed table
-SW cost approach outlined -SW cost model and data
-eRAM tasks outlined -Revised e-RAM content, table
-Revised content – in ORTC
verification -Further SIP, DSP/MCU
content
Application / -Approach for alignment with -New System Drivers content
product NEMI outlined
alignment
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference 4
Design Chapter Tables
General Design Requirements Table (2004)
– Updated numbers
– New rows (area density improvement)
– Detailed explanation of each row (footnote)
General Design Solutions Table (2004)
– New table
– New solutions after 2008
Outline future (2005) decomposition for detailed tables
– Currently design process-based
– Size ~ 50 requirements, 50 solutions
– Will map to grand challenges
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference 5
Design Helps – Not Enough
Improvement beyond scaling
– Still reaching a power management crisis
Dynamic Power
100000%
improvement beyond
scaling
10000%
Static power
1000% improvement beyond
scaling
100%
Area improvement
10% beyond scaling
1%
2000 2005 2010 2015 2020 Power (Static power
improvement beyond
scaling)
Expon. (Static power
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference 6
Design cost ($M)
Next?
$1
$10
$100
$1,000
What’s
$10,000
In-house P&R
Tall thin engineer
Small block reuse
Large block reuse
IC implem. tools
Intelligent testbench
DRAFT - NOT FOR PUBLICATION
Design Cost Reuse/ESL Are Critical
ES Level Methodology
Very large block reuse
14 July 2004 – ITRS Summer Conference
7
New General Design Solutions Table
2004 2007 2010 2013 2016 2019
2003 2005 2006 2008 2009 2011 2012 2014 2015 2017 2018
Technology Node hp90 hp65 hp45 hp32 hp22 hp16
Intelligent testbenches
ESL Design
Very large block reuse
System power mgt.
DFM (DFY)
Ultra large system
(HW+SW) reuse
Research Required Development Underway Qualification/Pre-Production Continuous Im provement
This legend indicates the time during which research, development, and qualification/pre -production should be taking place for the solution.
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference 8
SW Cost needs to be Included
Chip/circuit/physical design
Chip integration
Product cost Labor Verification, test
SW development
Development R&D EDA integration & support
EDA licenses
Manufacturing Infrastructure Test chips
Marketing, sales Depreciation/amortization
General, administrative Key:
Maintenance, service design/development costs
other costs
Financial Source: ITRS cost tree
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference 9
Software “Design” Versus Other Costs
More embedded software designers needed, and used
400
World’s designers (thousands)
350
300 software
250 hardware
200
150
100
Source: VDC
50
0
1998 1999 2000 2001 2002 2003 2004 2005 2006 2007
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference 10
SW Cost Model - Methodology
Identify target SoC for cost model analysis
– SoC for mobile platform must be a good target
Get and collect information for target SoC
– Required functions, performance
– Roadmap for the target application
Develop SW roadmap for the target SoC
– Define the layer of SW to be discussed as a SoC Cost model
– Identify required SW associated with the required functions
and performance for the target SoC
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference 11
New DFM Section –Outline
INTRO
DFM CHALLENGES -- NEAR TERM (>45 NM)
– MASK COST
– DATA EXPLOSION
– LIMITATIONS OF LITHOGRAPHY HARDWARE RESOLUTION
– VOLTAGE SUPPLY AND THRESHOLD VARIABILITY
– BEOL PLANARIZATION AND DIMENSIONAL VARIABILITY
– HETEROGENEOUS COMPONENTS (AMS, MEMS, ERAM)
– LEAKAGE AS A LIMITER OF MANUFACTURABILITY
– VARIABILITY
DFM CHALLENGES -- LONG TERM ( 10W
Module power
Current (average)
Environmental Temperature ranges Chip temperature
conditions System voltage ranges Chip voltage supply
Test BIST % of logic with BIST
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference 20
Verification Current landscape
Technology
Formal Verification
Semi-formal
verification
Simulation-based
methods
Emulation/
rapid prototyping
Real chip
Module Sub-system System Application
software
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference 21
Verification Challenges considered
Near Term Current 2004 ed. Long Term Current 2004 ed.
Capacity Simulation add emulation and General DFV
prototyping
Abstraction Lack from FV Simulation is robust
Robustness Lack from FV Simulation is robust Specification Human factors “specification for
Metrics Behavior cov. Outline metrics – verifiability”
Bug coverage Bug finding rate non-digital software verif. Tying with digital ver.
Software software verif. General challenges of
SoC verification
Heteroge- model abstraction of ifc
Reuse abstraction for Ver. IPs bundled with neous
verification design IPs Soft-failures new reliable in face of errors
Independent ver. IPs
Redundancy new reliable in face of errors
Methodology predictability Overview of methodology verification
Specialized MPU ad-hoc systematic per-domain-
DFV DFV based DFV adoption
Concurrency mpu intra- Inter and intra-mpu
concur.
Hybrid syst. move to long term
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference 22
Other Content (2005)
SiP to-be-added content
– Alignment with Assembly/Packaging
– Definition of tool and flow challenges
DSP / MCU
– Not much content at this time
– DSP / MCU have their own particular requirements
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference 23
Summary
Major 2004-2005 focus areas
– Derive quantitative, detailed design technology
requirements and solutions
• Detailed tables
– Address Design-Manufacturing interface challenges
• New section and model
Expected results
– New color tables
– New content
– Better alignment with other chapters and roadmaps
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference 24