Instruction Set Architecture
ECE 0909-443/444
Y. Tang
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Computer Architecture Concepts
Machine language: The language a particular
processor understands
Assembly language: machine-specific
language with a one-to-one correspondence with
the machine language for that computer
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Computer Architecture Concepts
Example:
High-Level Language: 10 + 20;
Assembly Language: MOV AX, 10
ADD AX, 20
Machine language: B8 1000
05 3000
op code Immediate
operand 3
Computer Architecture Concepts
Instruction Format
Opcode Mode Address/operand
Opcode field: specifies the operation to be
performed
Mode field: specifies the way the address field
is to be interpreted
Address/operand field: provides either a
memory address or an address for selecting a
process register, or contains the actual operand
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Computer Architecture Concepts
Basic computer operation cycle
Fetch the instruction from memory
Decode the instruction
Execute the instruction (fetch the operands, execute
the operation, and store the results in the proper place)
Register Set: consists of all registers in the
CPU that are accessible to the programmer
General purpose registers: also called data register that
are used for arithmetic and data movement (i.e., R0,
R1, R2 and R3)
Other registers: i.e., status register, stack pointer,
instruction pointer (program counter) 5
Operand Addressing
Example: X=(A+B)(C+D)
Three-address Instruction:
ADD T1, A, B M[T1] M[A] + M[B]
ADD T2, C, D M[T2] M[C] + M[D]
MUL X, T1,T2 M[X] M[T1] x M[T2]
Advantage/Disadvantage: short program for
evaluating expressions. More bits are
required to specify three addresses.
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Operand Addressing
Two-address Instruction:
MOVE T1, A M[T1] M[A]
ADD T1, B M[T1] M[T1] + M[B]
MOVE X, C M[X] M[C]
ADD X, D M[X] M[X] + M[D]
MUL X, T1 M[X] M[X] x M[T1]
Advantage/Disadvantage: saves bits in
instructions, and needs long program.
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Operand Addressing
one-address Instruction: to perform such
instruction, an implied address such as
accumulator register ACC is used to obtain one of
the operands and as the location of the result
LD A ACC M[A]
ADD B ACC ACC + M[B]
ST X M[X] ACC
LD C ACC M[C]
ADD D ACC ACC + M[D]
MUL X ACC ACC x M[X]
ST X M[X] ACC
Advantage/Disadvantage: saves bits in instructions,
but increases the number of instructions 8
Operand Addressing
zero-address Instruction: to perform such
instruction, implied addresses are needed for all
operands. Usually, it is fulfilled using stack
Stack: an special memory buffer used as a
temporary holding area for addresses and data.
It has LIFO structure (last in, first out).
TOS(SP) is the word at the top of the stack (the
last data to be added to). When one or more
words are used as operands for an operation,
they are removed from the stack. 9
Operand Addressing
Example: X=(A+B)(C+D)
zero-address Instruction:
PUSH A
PUSH B
ADD
PUSH C
PUSH D
ADD
MUL
POP X
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Operand Addressing
Note: Stack operations below is based on Intel based assembly
Original Stack
XX
low XX XX PUSH B TOS
YY
M[B]
YY PUSH A YY
M[A] TOS-1
00 M[A]
00 TOS
High 24 24
TOS 24
ADD
ADD M[D] TOS
M[D] XX
M[C]+ M[D]
M[C] TOS-1 M[B]
TOS M[A]+ M[B]
M[A]+ M[B]
TOS-1 M[A]+ M[B] TOS
24 24 PUSH C 24
PUSH D
MUL
POP 11
You finish it by yourself
Addressing Architecture
Memory-to-memory: all operands come
directly from memory and all results are
sent directly to memory.
- the instruction count is low
- the execution time is high
Register-to-register: allows only one
memory address and restricts its use to load
and store types of instructions.
- require a sizable register file
- execution time is potentially low 12
Addressing Architecture
Single accumulator:
- no register file
- accessing memory is needed
- inefficient
Stack architecture:
- need one or more memory accesses for
each stack operation
- good for rapid interpretation of high-level
language programs
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Addressing Modes
Addressing mode: specifies a rule for
interpreting or modifying the address field of
the instruction before the operand is actually
referenced.
Implied mode: the operand is specified implicitly
in the definition of the opcode.
Immediate mode: the operand is specified in the
instruction itself (i.e., constants)
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Addressing Modes
Register mode: the operand is in a register, whose
address is specified in the address field.
Register-indirect mode: the instruction specifies a
register whose content gives the address of the
operand in memory.
Direct addressing mode: the address field of the
instruction gives the address of the operand in
memory.
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Addressing Modes
Indirect addressing mode: the address field of the
instruction gives the address at which the effective
address is stored in memory.
Relative addressing mode:
Effective address=add. Part + content of Program
Counter (PC)
Indexed addressing mode:
Effective add. = add. Part + content of index
register
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Addressing Modes
Address Mode Example
An instruction in add. 300 and 301 is to “load to
ACC” with the add. Field ADR or an operand
equal to 500. Referring to the following memory
map, determine the content of ACC when the
above addressing modes are used, respectively (the
PC has the number 300 for fetching this
instruction, and when using register/register-
indirect/indexed mode, we assume to use R2 and
R2 =400).
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Addressing Modes
300 Opcode Mode
301 ADRS or NBR=500
...
400 350
...
500 600
...
600 HI
...
802 789
...
900 450 18
Instruction Set Architecture
Complex instruction set computers (CISCs):
provides hardware support for high-level
language operations and have compact
programs
- memory access is available
- addressing modes are substantial in number
- instructions formats have different lengths
- elementary and complex operations are
supported
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Instruction Set Architecture
Reduced instruction set computers (RISCs):
provides higher throughput and faster
execution
- memory access is restricted to load and
store instructions.
- data manipulation instructions are register
to register
- instructions formats have the same lengths
- elementary operations are supported
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