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Simplifying Free-to-Air Digital Satellite Receiver Designs


									                                                    Simplifying Free-to-Air
                                                    Digital Satellite Receiver

                                                    Richard Crossley
                                                    Satellite Products Marketing Manager
                                                    Mitel Semiconductor

      1. Introduction                                                      ‘real time’ activity. If this could be improved, it could change
      Despite the numerous potential applications in industry and          the way STBs are tested and installed, as well as offering sig-
      commerce, satellite TV is first and foremost a consumer busi-        nificant new possibilities in Free to Air applications, where us-
      ness, driven by the features, performance and cost of the prod-      ers often have to rely on slow downloads of network tables or
      ucts and services on offer. New technology is the primary route      accessing internet pages to determine channel availability.
      to enhance features and performance and reducing costs.
          This paper reviews the possibilities of addressing these three   2.4 Lower Cost.
      areas through advances in the front-end technology used in a         There is an expectation in the industry for the cost of the STB
      typical digital satellite receiver. The required enhancements are    products to reduce by a minimum of 20% per year, and this
      quantified, followed by a description of the design project in-      must be a major target of any new solution.
      tended to deliver these enhancements. The design philosophy,
      a top level functional description and a more detailed discus-       3. The Design Process
      sion of key elements are followed by a presentation of the de-
      livered benefits and their applications.                             3.1 System Level Design
                                                                           Optimising the performance-cost balance cannot be achieved
      2. The Requirements                                                  effectively by considering individual functions of the front end
                                                                           separately to the whole system. For maximum effectiveness the
      2.1 A Motherboard Solution.                                          system must be designed as a whole before partitioning the func-
      Major cost savings can be made by replacing the OEM tuner            tions into ICs. One part of this process of optimisation is decid-
      module with a front end function implemented directly onto           ing which functions to integrate, and which to implement dis-
      the motherboard. Any significant advance in front end technol-       cretely as part of the applications circuit. Making the right
      ogy must be based on such a route. To achieve a successful           choices at this point can make a significant difference to the
      motherboard solution, a design must address issues of compo-         cost effectiveness of the final solution. A further key stage in
      nent count, complexity, size (form factor), reliability, produc-     the design process is the inclusion of ancillary features which
      tion test, and of course the total system cost.                      can offer further small gains in performance or cost reduction,
                                                                           either by simplifying the applications circuit, or by integrating
      2.2 Reduction in Software Overhead in Development and                functions which would normally be provided elsewhere in the
      Operation.                                                           STB, thus reducing the hardware and software overhead.
      Time to market is a key competitive factor in the consumer
      market. At a time when software development in particular is         3.2 IC Functions
      consuming an ever greater level of resource in STB develop-          Using the above process, a system design project was recently
      ment, any reduction in the development time required to inte-        undertaken to address these areas of potential improvement.
      grate the front end software into the STB is an important gain.      The solution uses three ICs to provide the core functions; a
      It is also desirable to reduce the level of intervention required    direct conversion tuner IC, a low phase noise PLL synthesiser,
      by the main STB controller in the operation of the front end,        and a QPSK demodulator (incorporating dual ADCs and the
      thus reducing the software overhead and freeing up processor         FEC functions). One further IC is used to integrate many of the
      bandwidth for other tasks.                                           discrete components associated with the Low Noise Amplifier
                                                                           and AGC circuit. Key elements of the system design are re-
      2.3 Faster Scanning and Acquisition.                                 viewed below.
      Many broadcasters now are including a ‘scanning’ function in
      the STB software specification, the ability for the STB to search    4. Key Design Elements
      and acquire available signals. Current solutions tend to rely
      heavily on software to implement this function, and are there-       4.1 Direct Conversion Tuner
      fore relatively slow to the point where it cannot be considered a    To achieve the required simplification and cost reduction in the

152   International IC Taipei ‘99 • Conference Proceedings
RF section, a direct conversion based architecture can be used        Although it is not technically difficult to integrate the required
in place of the more traditional superheterodyne architecture.        filters (4-5th order elliptical), the necessary capacitors do take
By disposing of the second IF stage, the direct conversion de-        a significant area of silicon real estate, and for consumer appli-
sign enables a reduction in the number of ICs used and dis-           cation the most cost effective route is to implement them dis-
poses altogether with the need for a costly IF SAW filter. The        cretely, a solution which costs approximately $0.10 per chan-
primary requirements of a Direct Conversion Tuner in this ap-         nel.
plication are; good signal handling at the front end stage to re-
move the need for a tracking filter, low phase noise, good I/Q        5.2 IC Packaging
phase and gain matching, wide tuning range (950-2150MHz),             The same cost criteria should be used in considering the pack-
and good Local Oscillator rejection. These can be achieved by         aging of the solution. Whilst there is not yet a cost effective
careful application of good RF design techniques, particularly        semiconductor technology which allows the RF functions to be
in regard to the oscillator design. One very effective way of         integrated with the QPSK function whilst retaining adequate
achieving good phase noise performance over a wide tuning             performance, it is possible to package several ICs in a single
range is to use two integrated oscillators. By implementing two       package, either using standard IC packaging, or multi-chip
identical oscillators and following one with a single divide stage,   module hybrid technology. However, these routes, whilst ap-
one oscillator can address the upper half of the tuning range,        pearing to offer an attractive solution, do have some key cost
the other the lower half. Careful selection of the tuned circuit      related drawbacks. In general these alternative packaging op-
components ensures a safe degree of overlap in the central re-        tions require the assembly of known good die if the final mod-
gion.                                                                 ule yield is to be cost effective. This is currently difficult to
                                                                      achieve due to the parasitic effects of packaging on complex
4.2 QPSK/FEC control - Hardware State Machine.                        RF IC die, and for this reason the conventional IC packaging
The design of the main control function for the QPSK & FEC            remains the best solution for a consumer system.
has a major impact on both the front end user interface and the
speed of operation of key front end functions. Conventional           5.3 Low Cost Crystal
solutions have tended to use one of two approaches; either a          By using a phase locked loop integrated in the QPSK IC to
relatively low level, register based approach, which requires         generate the front end system clock, it is possible to use a rela-
significant software overhead to drive the front end, or an ap-       tively low frequency clock input to the QPSK chip. Using a
proach based on a micro-core embedded in the QPSK IC. Al-             low level reference frequency output from RF PLL IC, the num-
though a micro-core based design can reduce the load on the           ber of crystals in the front end system can be reduced to one.
main processor, it has the disadvantage that it often requires
significant quantities of code to be downloaded to the QPSK           5.4 Standard Components & Materials in the Application
IC on power-on. In addition, a software based control core lim-       Circuit
its the speed of certain functions. To avoid these drawbacks and      Costs can also be minimised by using commonly available and
to achieve the desired speed improvements an alternative solu-        standard value discrete components in the applications circuit.
tion can be used, based on a hardware state machine for the           The same is true when specifying the PCB. The use of com-
control core. This architecture offers a high level user interface,   monly accepted material such as FR4, and specifying standard
no software downloading, and high operating speeds whilst still       production tolerancing for the layout keeps system costs down.
retaining the full register level access control for specialist ap-
plications. A high level user interface allows the major func-        6. Adding Ancillary Features
tions to be programmed with simple high level commands in-
stead of using low level register programming, resulting in a         6.1 DiSEqC - Digital Equipment Satellite Control
major reduction in development time. The other major benefit          In many current STBs the Low Noise Block (LNB) control func-
is a significant speed increase in the scanning function, which       tion is implemented by main system controller combined with
requires minimal intervention by the system microcontroller           some additional circuitry, either in discrete or IC form. By in-
and offers a speed improvement of between 5 and 15 times cur-         corporating these control functions in the QPSK IC it is pos-
rent front end solutions.                                             sible to reduce the load on the controller, and the component
4.3 Optimised Algorithms - for High Speed Scanning &
Acquisition at all Baud Rates                                         6.2 Fast I2C Loop-Through
A further key element for an improved front end system is the         In order to achieve maximum performance from the RF front
design of the algorithm used to control the main acquisition          end, many STB designs implement two I2C buses, one for the
functions of the QPSK demodulator. The algorithms must be             majority of system functions, and a separate control bus for the
robust, highly resistant to false locks, and yet fast enough to       front end. This ensures potential I2C bus noise is isolated from
take advantage of the inherent speed of the hardware control-         the RF tuner section. By incorporating an I2C loop through
ler. Further improvements in scanning and acquisition time at         function in the QPSK IC, the new design ensures that only the
lower symbol rates can be achieved by using more than one             I2C commands addressed to the RF section are gated through
algorithm optimised for different symbol rate ranges. By se-          to the RF PLL, thus removing the need for a separately gener-
lecting the algorithm most suited to the signals being searched       ated I2C bus. Since true transmission gates are used to imple-
for, the operating speed can be maximised.                            ment this function, the RF front end can be programmed at the
                                                                      maximum I2C rate of 400KHz, again increasing the general
5. Optimising the Design for Minimum Production Cost                  speed of the front end operation.

5.1 Discrete channel filters
The best way to implement the channel filters is the subject of
an ongoing technical discussion within the industry. The main
discussion centers on whether the filters are best on, or off chip.

                                                                            International IC Taipei ‘99 • Conference Proceedings           153
      6.3 Integrated Low Noise Amplifier & AGC Function                      Feedback from key STB manufacturers indicates that the hard-
      Although the main front end functions are provided by the two          ware controller combined with the high speed I2C bus imple-
      RF ICs (direct conversion tuner & PLL synthesiser) and the             mentation improves scanning/acquisition times by a factor be-
      QPSK IC, further benefits can be achieved by using an inte-            tween 5 and 15, depending on the application.
      grated LNA/AGC function. This can replace up to 20 discrete
      components. The increased simplicity and reliability this can          8.4 Lower cost - to meet the industry requirement for 20%
      bring to the design is of particular benefit when the front end is     cost reduction per year?
      to be implemented directly on the STB motherboard. The addi-           The component cost excluding ICs is less than $2, which de-
      tion of this IC also enhances performance by increasing the            pending on volume will enable a potential saving of up to 25%
      isolation between the RF input and the tuner local oscillator.         on an OEM based solution

      7.0 Performance measurements                                           9.0 Applications
      7.1 Scanning speeds                                                    9.1 Potential time/cost savings in manufacture/test/installation
      As described above, the use of a hardware controller consider-         Any incremental savings in test time are directly reflected in
      ably speeds up the scanning and acquisition process. Acquisi-          manufacturing costs, and there are clear potential time benefits
      tion times for standard higher data rates such as Astra signals        in using the high speed scanning facility as part of the equip-
      can be as low as 15S, and a test scan of all the Astra satellite can   ment test. The same is true of the installation process, where
      identify all the currently available signals in under 30 seconds.      the ability to pre-select the symbol rate and puncture rates to be
      This compares with several minutes, or more for current pro-           searched can be used to minimise the search time, and even
      duction solutions. These speed gains are reflected across the          isolate a specific broadcasters channel where unique symbol
      range of symbol rates and fact a separate algorithm can be used        rate/puncture rate combinations exist.
      to optimise acquisition times at low symbol rates.
                                                                             9.2 User Benefits
      7.2 Bit Error Rate Performance                                         Apart from potential benefits to manufacturing/test mentioned
      The design performs across the full 1-45Msymbol/s range, al-           above, these advances in front-end technology offer clear ben-
      though by targeting specific applications it is possible to fur-       efits to the final user. Faster acquisition is a benefit to any sys-
      ther optimise the system cost. For example a lower cost PLL            tem, but it is Free to Air System users that potentially have
      synthesiser can be used if the system is targeted at a 20-             most to gain from the fast scanning facility. When a steerable
      30MSym/s application                                                   dish is pointed at a new satellite it can currently take tens of
                                                                             minutes to identify all the channels. The alternatives, either down
      8.0 Assessing the Results against the Target                           loading network tables or using the internet to obtain channel
      Requirements                                                           information are not necessarily much quicker, and in the case
                                                                             of the internet, it is certainly less convenient. Clearly in order
      8.1 Motherboard Solution?                                              to fully identify the available programme material, it is neces-
      The first PCB layout of a motherboard implementation using             sary to decode the SI information via the transport mechanism
      this new technology was completed by a STB customer within             in the STB baseband, and the time taken by the front-end to
      1 week, and the whole design was working within 5 days of              acquire signals is only part of the total time required for this
      receiving the bare motherboard pcb. In addition to the ICs, the        task. However the potential to speed up by many times the front
      front end design requires only 24 discrete components other            end task does potentially save many minutes, and depending
      than resistors and capacitors. Further optimisation work is cur-       on the symbol rate, offer a scanning system that operates much
      rently reducing the number of capacitors, inductors and remov-         nearer ‘real time’.
      ing a crystal. The design requires a board area of just 35x110mm
      on 2 layer or 4 layer FR4, with components mounted on a single         10. Conclusions
      side only. A new version in development with components on             Using a system design approach, and innovative IC design it is
      both sides measures just 40x40mm.                                      possible to make significant advances in front-end performance
                                                                             and features whilst reducing costs.
      8.2 Reduction in Software Overhead in Development and
      The high level user interface drastically reduces the level of
      intervention by the STB controller. The front end can be
      initialised and the first signal acquired with just a handful of
      simple one byte commands. After defining the symbol rate
      ranges and puncture rates to be searched, the main system con-
      troller simply has to define the start and stop frequencies. From
      that point the only interaction required is a response to the in-
      terrupt received when a signal is detected, and a subsequent
      ‘recommence sweep’ command’. There is no software to down-
      load to the front end on power-up. The high level command
      mode makes the interface with the front end very user friendly,
      and as a result considerably speeds up development time. In a
      recent example one STB manufacture integrated the key soft-
      ware routines and had a working solution within three days.

      8.3 Faster Scanning and Acquisition?

154   International IC Taipei ‘99 • Conference Proceedings

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