# Basic Logic Design with Verilog HDL by Go3542

VIEWS: 232 PAGES: 67

• pg 1
```									Basic Logic Design
with Verilog HDL
Combinational Circuits

Lecture note ver.1 by Chen-han Tsai
ver.2 by Chih-hao Chao
ver.3 by Xin-Yu Shi
ver.4 by Bo-Yuan Peng
ver.5 by Cheng-Zhou Zhan
Outline
 Introduction to Verilog HDL
 Syntax in Verilog HDL
 Gate-Level Modeling
 Test-Bench
 Compilation and Simulation Tools
 Preview of Lab Questions

2
Outline
 Introduction to Verilog HDL
 Syntax in Verilog HDL
 Gate-Level Modeling
 Test-Bench
 Compilation and Simulation Tools
 Preview of Lab Questions

3
What is Verilog HDL?
   Why using Hardware Description
Language?
◦ Design abstraction: HDL ←→ layout by
human
◦ Hardware modeling
◦ Reduce cost and time to design hardware
   Two Popular HDLs
◦ VHDL
◦ Verilog

4
What is Verilog HDL?
   Key features of Verilog
◦ Supports various levels of abstraction
   Behavior level
   Register transfer level
   Gate level
   Switch level
◦ Simulate design functions

5
Different Levels of Abstraction
   Architectural / Algorithmic Level
◦ Implement a design algorithm in
high-level language constructs.
   Register Transfer Level
◦ Describes the flow of data
between registers and
how a design process
these data.

6
Different Levels of Abstraction
   Gate Level
◦ Describe the logic gates and the
interconnections between them.
   Switch (Transistor) Level
◦ Describe the transistors and
the interconnections
between them.

7
Simplified Hardware Design Flow

Designer
Level   Cost
RTL                    RTL       High    Low
Simulation               Editor

Verilog             RTL Code

Gate Level              Logic
Simulation            Synthesizer

Gate Level Code

Post Gate
Level             Place & Route
Simulation
Physical Layout

Tape Out
Low     High

Chip
8
Example: 1-bit Multiplexer

sel
to “select” output
sel   in1   in2   out

0     0     0     0
in1     0                  0     0     1     0

out         0     1     0     1

in2     1                  0     1     1     1

1     0     0     0

1     0     1     1

if (sel==0)                1     1     0     0

out = in1;
1     1     1     1

else                 out = (sel’‧in1) + (sel‧in2)
out = in2;

9
Gate Level Description

in1
a1_o
iv_sel   a1          o   out
in2                         1
n1      a2   a2_o

sel       iv_sel

Gate Level: you see only netlist (gates and wires) in the code.

10
Behavior Level / RTL Description

always block             assign

RTL: you may see high level behavior in the code
Behavior: event-driven behavior description construct
11
Outline
 Introduction to Verilog HDL
 Syntax in Verilog HDL
 Gate-Level Modeling
 Test-Bench
 Compilation and Simulation Tools
 Preview of Lab Questions

12
A Simple Verilog Code

module name   in/out port

declaration
syntax
port/wire
declaration

kernel hardware
gate-connection/
behavior

13
Module
   Basic building block in Verilog
   Module
1. Created by “declaration” (can‟t be nested)
2. Used by “instantiation”
   Interface is defined by ports
   May contain instances of other modules
   All modules run concurrently

14
Module Instantiation

instance
example

15
Instances
 A module provides a template from which
you can create actual objects.
 When a module is invoked,Verilog creates
a unique object from the template.
 Each object has its own name, variables,
parameters and I/O interface.

16
Analogy: Module vs. Class

Format           module m_Name( IO list );   class c_Name {
...                         ...
endmodule                   };

Instantiation    m_Name ins_name ( port      c_Name obj_name;
connection list );
Member           ins_name.member_signal      obj_name.member_data

Hierachy         instance.sub_instance.membe object.sub_object.member_data
r_signal

17
Port Connection

   Connect module port by order list
◦ FA1 fa1(c_o, sum, a, b, c_i);
   Connect module port by name (Recommended)
◦ Usage: .PortName (NetName)
◦ FA1 fa2(.A(a), .B(b), .CO(c_o), .CI(c_i), .S(sum));
   Not fully connected
◦ FA1 fa3(c_o, , a, b, c_i);
18
Verilog Language Rule
   Case sensitive
   Identifiers
◦ Digits 0123456789
◦ Underscore _
◦ Upper and lower case letters from the alplabet
 Terminate statement/declaration with
semicolon “;”
◦ Single line: // it’s a single line comment example
◦ Multi-line: /* When the comment exeeeds single
line,
multi-line comment is
necesssary */

19
Data Type: Register
   Register
◦   Keyword: reg, integer, time, real
◦   Event-driven modeling
◦   Storage element (modeling sequential circuit)
◦   Assignment in “always” block (LHS of
expressions)

20
Data Type: Net
   Net
◦ Keyword: wire, wand, wor, tri, triand, trior,
supply0, supply1
◦ Doesn‟t store value, just a connection
◦ Input, output and inout ports are default
“wire”

21
Four-valued Logic Value
   Nets and registers in Verilog codes hold
four-valued data
◦ 0 represent a logic „0‟ or false condition
◦ 1 represent a logic „1‟ or true condition
◦z
 Output of an undriven tri-state driver – High-Z
value
 Models case where nothing is setting a wire‟s value

22
Four-valued Logic Value
   Nets and registers in Verilog codes hold
four-valued data
◦x
 Models when the simulator can‟t (doesn‟t) decide
the value – un-initialized or unknown logic value
 Initial state of registers
 A wire is being driven to 0 and 1 simultaneously
 Output of a gate with z inputs

23
Logic System
   Four values: 0, 1, x/X, z/Z (not case
sensitive)
◦ The logic value x denotes an unknown
(ambiguous) value
◦ The logic value z denotes a high-impedance
value (High-Z value)
 Primitives have built-in Logic
 Simulators describe 4-value logic

24
Logic System: Example

a                       y
0   1   X   Z                 b

0   0   0   0   0
a   0             1         x             z
1   0   1   X   X
X   0   X   X   X   b       x z           x z       x z           x z

Z   0   X   X   X
y                      x        x             x

25
Number Representation
 Format: <size>’<base_format><number>
 <size> - decimal specification of bits count
◦ Default: unsized and machine-dependent but at least
32 bits
   <base_format> - ' followed by arithmetic base
of number
◦   d or D – decimal (default if no base format given)
◦   h or H – hexadecimal
◦   o or O – octal
◦   b or B – binary

26
Number Representation
 Format:
<size>’<base_format><number>
 <number> - value given in base of base
format
◦ _ can be used for reading clarity
◦ x and z are automatically extended

27
Number Representation
   Examples:
◦   6‟b010_111   gives 010111
◦   8‟b0110      gives 00000110
◦   4‟bx01       gives xx01
◦   16‟H3AB      gives 0000001110101011
◦   24           gives 0…0011000
◦   5‟O36        gives 11110
◦   16‟Hx        gives xxxxxxxxxxxxxxxx
◦   8‟hz         gives zzzzzzzz

28
Number Representation
   659 // unsized decimal                        // underline usage
   „h 837ff           // unsized hexadecimal     27_195_000
   „o7460             // unsized octal           16‟b0001_0101_0001_1111
   4af                // illegal syntax          32‟h12ab_f001
   4‟b1001            // 4-bit binary
   5‟D 3 // 5-bit decimal                        // X and Z is sign-extended
   3‟b01x             // 3-bit number with
unknown LSB   reg [11:0] a;
   12‟hx // 12-bit unknown                       initial
   8‟d -6// illegal syntax                       begin
   -8‟d 6// phrase as - (8‟d6)                       a = „hx;      // yields xxx
a = „h3x;     // yields 03x
a = „h0x;     // yields 00x
end

29
Net Concatenation

Module B
Module A
Module C
3„o7

Representations           Meanings
{b[3:0],c[2:0]}           {b[3] ,b[2] ,b[1] ,b[0], c[2] ,c[1] ,c[0]}
{a,b[3:0],w,3’b101}       {a,b[3] ,b[2] ,b[1] ,b[0],w,1’b1,1’b0,1’b1}
{4{w}}                    {w,w,w,w}
{b,{3{a,b}}}              {b,a,b,a,b,a,b}
30
Operators
Arithmetic Operators         +, -, *, /, %
Relational Operators         <, <=, >, >=
Equality Operators           ==, !=, ===, !==
Logical Operators            !, &&, ||
Bit-wise Operators           ~, &, |, ^, ~^
Unary Reduction              &, ~&, |, ~|, ^, ~^
Shift Operators              >>, <<
Conditional Operators        ?:
Concatenations               {}

Excerpts from CIC training course: Verilog_9807.pdf
31
Operator Examples

All bits are 0 logic false

Excerpts from CIC training course: Verilog_9807.pdf
32
Compiler Directives
   'define
◦ 'define RAM_SIZE 16
◦ Defining a name and gives a constant value to it.
   'include
◦ Including the entire contents of other verilog source
file.
   'timescale
◦ 'timescale 100ns/1ns
◦ Setting the reference time unit and time precision of

33
   \$monitor
◦ Displays the values of the argument list whenever any
of the arguments change except \$time.
   \$display
◦ Prints out the current values of the signals in the
argument list
   \$finish
◦ \$finish
◦ Terminate the simulation

34
Outline
 Introduction to Verilog HDL
 Syntax in Verilog HDL
 Gate-Level Modeling
 Test-Bench
 Compilation and Simulation Tools
 Preview of Lab Questions

35
Gate Level Modeling
   Steps
◦ Develop the Boolean function of output
◦ Draw the circuit with logic gates/primitives
◦ Connect gates/primitives with net (usually
wire)
   HDL: Hardware Description Language
◦ Figure out architecture first, then write code.

36
Primitives
 Primitives are modules ready to be
instanced
 Smallest modeling block for simulator
 Verilog build-in primitive gate
◦ and, or, xor, nand, nor, xnor
 prim_name #delay inst_name( out0, in0, in1,.... );
◦ not, buf
 prim_name #delay inst_name( out0, out1, ..., in0);
   User defined primitive (UDP)
◦ building block defined by designer

37

Ci   A   B   Co   S
A       B        0    0   0   0    0

0    0   1   0    1

Full            0    1   0   0    1
Co               Ci
Adder            0    1   1   1    0

1    0   0   0    1
S            1    0   1   1    0

1    1   0   1    0

1    1   1   1    1

38
   Co = AB + BCi + CiA

A
B
B
Co
Ci
Ci
A

39
   sum = a  b  ci

a
b
c                     sum

a
b             sum
c

40
◦ Instance ins_c from FA_co        full adder

◦ Instance ins_s from FA_sum               carry out
a          connection
b
b
co
c
c
a

sum
connection
a
b                 sum
c

41
Outline
 Introduction to Verilog HDL
 Syntax in Verilog HDL
 Gate-Level Modeling
 Test-Bench
 Compilation and Simulation Tools
 Preview of Lab Questions

42
Test Methodology
 Systematically verify the functionality of a
model.
 Procedure of simulation
◦ Detect syntax violations in source code
◦ Simulate behavior
◦ Monitor results

43
Test Methodology

Stimulus

Hardware Design
Testbench
(Design Under Test)

Response

44
Verilog Simulator

45
reg    a, b, cin;                 // for stimulus waveforms
wire   sum, c_out;
full_add M1 (sum, c_out, a, b, cin); //DUT
initial #200 \$finish;             // Stopwatch
initial begin                      // Stimulus patterns
#10 a = 0; b =   0;   cin   =   0; // Execute in sequence
#10 a = 0; b =   1;   cin   =   0;
#10 a = 1; b =   0;   cin   =   0;
#10 a = 1; b =   1;   cin   =   0;
#10 a = 0; b =   0;   cin   =   1;
#10 a = 0; b =   1;   cin   =   1;
#10 a = 1; b =   0;   cin   =   1;
#10 a = 1; b =   1;   cin   =   1;
end
endmodule

46
Summary
   Design module / DUT
◦ Divide-and-Conquer
◦ Architecture figure of each sub-module
 Make architecture figures before you write Verilog codes
◦ Connection of sub-modules
   Test-bench
◦ Feed input data and compare output values at right timing
slots
◦ Usually describe in behavioral level
◦ Not real hardware, just like software programming (e.g.
C/C++)

47
Note
   Verilog is a platform
◦ Support hardware design (design module)
◦ Also support C/C++ like coding (test bench)
   How to write verilog well?
◦ Know basic concepts and syntax
◦ Get a good reference codes
(a person or some code files)
◦ Form a good coding style
   Hardware
◦ Combinational circuits (today‟s topic)
◦ Sequential circuits (we won‟t model them in this course)

48
Outline
 Introduction to Verilog HDL
 Syntax in Verilog HDL
 Gate-Level Modeling
 Test-Bench
 Compilation and Simulation Tools
 Preview of Lab Questions

49
Start to Use ModelSim

Double click the icon
“ModelSim SE 5.7d”
Start to Use ModelSim
Create a Project

Assign by yourself
Open a New File
Edit Verilog Files
Save files as “xxxxx.v”

Compile

Compile Successful Message
Simulation

2. Press “Simulate”

Simulation

2. Press OK
Simulation
View Signals
View Signals
View Signals
View Signals
Run
End Simulation

```
To top