OpenRISC-Based Embedded System Design by 814ilp

VIEWS: 235 PAGES: 69

									OpenRISC-Based Embedded
     System Design


       April. 3, 2007




      Dynalith Systems
      www.dynalith.com
                            Agenda
Introduction to OpenCores
OpenRISC Architecture
OpenIDEA
Example




                            Introduction   (2)
                           Introduction to OpenRISC
OpenRISC
   Free open-source synthesizable RISC processor
   Distributed by OpenCores, http://www.opencores.org
OpenRISC 1000 (or1k)
   Target
       medium and high performance networking and embedded computer environments
   Architecture
       32/64-bit load/store RISC architecture
       Designed with emphasis on performance, simplicity, low power requirements and scalability
   Architecture Definition
       Instruction set, register set, cache management & coherency, memory model, exception model,
       addressing mode, operands conventions, application binary interface
   Not define implementation-specific details
       Pipeline depth, cache organization, branch prediction, instruction timing, bus interface




                                                                       Reference: OpenRISC 1000 Architecture Manual


                                               Introduction   (3)
                       OR1K Architecture Overview

Address space             32-bit or 64-bit logical address space

                          Simple and uniform-length instruction
                          Different instruction set extensions
                           - ORBIS 32/64 (OpenRISC Basic Instruction Set)
                                32-bit wide, operating on 32- and 64-bit data
Instruction
                           - ORDVX64 (OpenRISC Vector/DSP eXtension)
                                32-bit wide, operating on 8-, 16-, 32- and 64-bit data
                           - ORFPX32/64 (OpenRISC Floating-Point eXtension)
                                32-bit wide, operating 32- and 64-bit data
                          Separate instruction and data cache/MMU (Harvard architecture)
Architecture
                          Unified instruction and data cache/MMU (Stanford architecture)

Memory addressing         Addition of a register operand and a signed 16bit immediate


Instruction operands      Two source register operands (or one register and a constant) and one result register


Branch                    Branch delay slot for keeping the pipeline as full as possible


Context switch            Fast context switch support in register set, caches and MMUs




                                            Introduction   (4)
                 OpenRISC 1000 implementations
OR1200
  Entry level 32bit RISC processor
  I/D Cache, I/D MMU, Tick timer, PIC, Debug
  Internet appliances, Networking, Handheld                                      OpenRISC 1000
OR1100                                                                         architecture 32/64-bit
  Entry level 32bit DSP                                            OpenRISC 1200
  I Cache, Tick timer, PIC, Debug                                                            OpenRISC 1x00
                                                                       32/-bit
  VoIP, Modems, Imaging
OR1400
  High performance superscalar 64bit RISC
  I/D Cache, I/D MMU, Tick timer, PIC, Debug, FPU,
  Vector/DSP                                                    OpenRISC   1     2   0   0
  Telecom, Home entertainment
OR1500                                                                                            How the
  A limited configuration                                                                     implementation is
                                                                                                 configured
  SystemC implementation
                                                                                             Which features are
                                                                                               implemented
                                                                                              OpenRISC 1000
                                                                                                  family



                                           Introduction   (5)
                                OpenRISC 1200
An implementation of OR1K architecture                Performance
   32-bit scalar RISC                                       250 MIPS Dhrystone 2.1 @ 250Mhz wc
   ORBIS32 instruction set                                  250 MMAC operations @ 250Mhz wc
   Harvard micro-architecture                               <500mW or <1W @ 250Mhz, 0.18mm
   Five-stage integer pipeline                              <0.4mm2 @ 0.18mm 6LM (excluding
   Virtual memory support (MMU)                             cache & memory)
      Separated IMMU and DMMU
   Separated I-cache and D-cache
Including Components
   Debug unit
   Tick timer
   Programmable interrupt controller
   Power management




                                       Introduction   (6)
                                       OpenRISC 1200
                                                                L1 Caches
                                                                      I/D Cache (1 to 8 KB)
                                                                      1-way direct-mapped cache
                                                                MMU
                                                                      With 1-way direct-mapped TLB
                                                                      Harvard model
                                    System I/F
                                                                      TLB, 16 to 64 entries
                    OpenRISC 1200                               Power Management
                                                                      Power save modes
PM                                                                    Software controlled clock frequency
       POWERM                          IMMU
I/F                                                                   Interrupt wake-up
                                                 WB
                                                                      Dynamic clock gating for individual units
                                                  I
DB                                    ICache                    Interrupt Controller
        DEBUG                                                         30 maskable interrupt sources
I/F                                     8KB
                                                                Tick Timer
                                                                      Task scheduling
                                      DCache
       TICK TIMER      CPU/DSP                                        Time measurement
                                       8KB
                                                 WB                   Interrupt generation
                                                  I                   Single-run, restartable or continuous mode
INT                                                             Debug Unit
          PIC                         DMMU
 I/F                                                                  JTAG Test Access Port
                                                                      Non-intrusive Realtime debug/trace for both CPU and
                                                                      System
                                                                      Accessible via development interface
                                                                      Links into GDB



                                                                             Reference: OpenRISC 1200 IP Core Specification


                                                 Introduction   (7)
OpenRISC 1200, Leon 2, MicroBlaze




             Introduction   (8)
                         Architecture Details
Register Set
Instruction Set
Exception Model
Memory Model
Memory Management
Cache
Debug Unit
Performance Counter Unit
Power Management
Timer/PIC
Application Binary Interface




                               Introduction   (9)
                                    Register Set
Register set                                                          Special purpose registers

   Thirty-two or sixteen 32/64-bit general purpose                Group #                Description
   registers                                                          0           System control/status
   All other registers are special purpose registers                  1                   Data MMU
   User-level/supervisor-level register                               2               Instruction MMU
   Multiple sets of GPRs (not implemented in or1200)                  3                   Data cache
Special-purpose registers                                             4              Instruction cache
   32 groups, up to 2048 registers in a group                         5                    MAC unit
   l.mtspr/l.mfspr instruction                                        6                   Debug unit
                                                                      7            Performance counter
                                                                      8             Power management
                                                                      9                        PIC
                                                                     10                    Tick timer
                                                                      11             Floating point unt
                                                                   12-23                   Reserved
                                                                   24-31                 Custom unit


                                                                 Reference: OpenRISC 1000 Architecture Manual

                                         Introduction   ( 10 )
                                         Instruction Set
Simple and uniform-length instruction format                     ORFPX64
ORBIS32 (or1200)                                                        32-bit wide, 32-bit boundary aligned, 64-bit data
    32-bit wide, 32-bit boundary aligned, 32-bit data                   operation
    operation                                                           Double-precision floating-point instructions
    32-bit integer instructions                                         64-bit load/store instructions
    Basic DSP instructions                                       ORVDX64
    32-bit load/store instructions                                      32-bit wide, 32-bit boundary aligned, 8-, 16-, 32-,
    Program flow instructions                                           64-bit data operation
    Special instructions                                                Vector instructions
ORBIS64                                                                 DSP instructions
    32-bit wide, 32-bit boundary aligned, 64-bit data            Reserved opcodes for custom instructions
    operation
    64-bit integer instructions
    64-bit load/store instructions
ORFPX32
    32-bit wide, 32-bit boundary aligned, 32-bit data
    operation
    Single-precision floating-point instructions




                                                Introduction   ( 11 )
                                                    Instruction Set

              Or1200 Implementation
Arithmetic/   l.add/l.addc/l.addi       l.and/l.andi
                                                                                          prefix   .   instruction   .   postfix
logical       l.sub                     l.or/l.ori
              l.mul/l.Mulu              l.rori
                                        l.sll/l.slli/l.sra/l.srai/l.srl/l.srli                                             Precision/data
                                        l.xor/l.Xori                                                                       width
                                                                                                                           d : double
Branch        l.bf/l.bnf                                                                                                   s : single
              l.j/l.jal/l.jalr/l.jr                                                                                        b : byte
              l.Rfe                                                                                                        h : half-word
                                                                                                                           n : nibble
Load          l.lbs/l.lbz/l.lhs/l.lhz/l.lws/l.lwz
/Store        l.sb/l.sh/l.sw
                                                                                                                           Instruction
Flag          l.sfeq/l.sfne
              l.sfges/l.sfgeu/l.sfgts/l.sfgtu                                                                              Instruction set
              l.sfles/l.sfleu/l.sflts/l.sfltu                                                                              l : ORBSIS
                                                                                                                           lf : ORFPX
Register      l.mfspr/l.mtspr                                                                                              lv : ORVDX
              l.movhi
Exception     l.trap/l.sys

Etc.          l.Nop



                                                               Introduction      ( 12 )
Exception Model
                     Reset vector
                            0x100
                     Bus error
                            Caused by a bus interface error
                            Bus error
                     Instruction/Data page fault
                            Caused by access to an invalid virtual
                            address
                            Segmentation fault
                     Alignment
                            Caused by not aligned access
                            Bus error
                     Range
                            Caused by not available register access




    Introduction   ( 13 )
                                 Memory Model
Weakly ordered memory model
   High performance memory system
   Responsibility for strict access ordering on programmer
   Memory synchronization instruction
      l.msync : complete of all load/store operations before the RISC core continues
   Or1200 implementation
      Strongly ordered memory model
Atomicity
   Atomic memory access instructions
      l.lwa, l.swa
   Or1200 implementation
      Not intended for use in multiprocessor environments
      No support for coherency between local data cache and caches of other processors or
      main memory
      Write-through cache




                                        Introduction   ( 14 )
                         Memory Management
Support for implementation specific size of physical address spaces up to 35
address bits (32 GByte)
Three different page sizes:
   Level 0 pages (32 Gbyte; only with 64-bit EA) translated with D/I Area Translation
   Buffer (ATB)
   Level 1 pages (16 MByte) translated with D/I Area Translation Buffer (ATB)
   Level 2 pages (8 Kbyte) translated with D/I Translation Lookaside Buffer (TLB)
Address translation using one-, two- or three-level page tables
Powerful page based access protection with support for demand-paged virtual
memory
Support for simultaneous multi-threading (SMT)
OR1200 implementation
   Only level 2 paging is implemented.




                                     Introduction   ( 15 )
                           Memory Management
OpenRISC 1000 Specification
   32-bit implementation
   64-bit implementation




                                Introduction   ( 16 )
                         Memory Management
OR1200 implementation
   Level 3 paging implemented
   1-way direct mapped TLB

                                       Virtual Page Number (VPN)
                            31                                                     13     12                                  0

                                  TLB Tag                       TLB Index                            Page Offset
                                 (13(12)-bit)            (7(8)-bit; 64(128)-entry)                   (13-bit; 8KB)

                            31                     19(20)                          13




                                                14(13)             1    0                 31               13                                  0
                                                Tag (13(12)-bit)        V                 Physical PN (19-bit)   swe    sre   uwe      ure    ci




                                                        TLB                                                     TLB
                                                 Translate Register                                        Match Register

                                    64(128)                                     64(128)
                                     -entry                                      -entry




                                                                                 31                                      13       12                 0

                                                                                          Physical Page Number                         Page Offset
                                                            ?
                                                                                                 (19-bit)                                (13-bit)


                                                                Hit/Miss                                               Physical Address




                                                Introduction           ( 17 )
                                    Cache
Cache
   1-way direct-map
   Up to 8KB for each I/D cache
Cache control
   Block prefetch
   Block flush
   Block invalidate
   Block write-back
   Block lock
Or1200 cache implementation
   Write-through mode
   No support for coherency
   No prefetch
   No support for cache line lock




                                    Introduction   ( 18 )
                                      Quick Memory
Quick memory
   On-chip memory
   Unified I&D memory




         Virtual           Physical
 GenPC   Addr.     I-MMU    Addr.                         I-Cache                   Data BIU
                                                                    Inst.
                                       QMEM

         Virtual           Physical
          Addr              Addr                                    Store
  LSU              D-MMU                                  D-Cache                   Data BIU
                                                                    Buffer
                                                                             Data




                                          Introduction   ( 19 )
                              Debug Unit
Eight sets of debug value/compare registers
Match signed/unsigned conditions on
   instruction fetch EA
   load/store EA
   load/store data
Combining match conditions for complex watchpoints
Watch-points can be counted by Performance Counters Unit
Watch-points can generate a breakpoint (trap exception)
Counting watch-points for generation of additional watch-points




                                 Introduction   ( 20 )
Debug Unit
                Registers
                         DVR (Debug Value Register)
                         DCR (Debug Control Register)
                            Compare target
                            Compare condition
                         DMR (Debug Mode Register)
                            WP/BP setting
                            Combination of conditions of DVRs
                         DWCR (Debug Watch-point Counter
                         Register)
                         DSR (Debug Stop Register)
                            Core stop condition
                         DRR (debug Reason Register)
                OR1200 implementation
                         Breakpoint but no watchpoint




 Introduction   ( 21 )
                         Performance Counter Unit
Benefits
   To improve performance by developing better application level algorithms,
   To better optimized operating system routines
   For improvements in the hardware architecture of these systems
   To improve future OpenRISC implementations
   To add future enhancements to the OpenRISC architecture.
   To help system developers debug and test their systems.
Performance counter
   Eight counters
   Counting predefined events
       Load/store/instruction fetch
       I/D-cache miss
       LSU/branch/instruction fetch/data dependency stall
       I/D-TLB miss
       Watch point
Not implemented in OR1200




                                             Introduction   ( 22 )
                                Power Management
Slow down
   Support 0~15 clock frequency level
   Need external clock synthesizer
Power mode (dynamic clock gating, dynamic voltage scaling)
   Normal mode
   Doze mode
      All disabled (clock gating) except tick timer and PIC
      Enter normal mode by timer or interrupt
   Sleep mode
      All disabled (clock gating) and voltage down except PIC
      Enter normal mode by interrupt
   Suspend mode
      All disabled (clock gating) and voltage down
      Enter normal mode by reset
OR1200
   Power manager implemented
   But no clock gating implemented




                                              Introduction   ( 23 )
                                                 Overall Blocks
                           Physical
    I-MMU                   Addr.                                        I-Cache                      Inst. BIU
                                                                                       Inst.
                                                  QMEM

                                      Physical
Virtual                                Addr                                           Store
                    D-MMU                                                D-Cache                      Data BIU
Addr.                                                                                 Buffer
                                                                                               Data



                 Virtual                                                                                PIC
                  Addr                                 Register
   GenPC                                                 File                      Freeze

                                                                                                       Timer
                      LSU                              Operand
                                                        MUX
     Inst.
                                                                                   Except
    Fetch
                                                                  Multiplier                           Power
                                                 ALU               MAC                                Manager



          Control Logic
                                                                                    SPR
           (decode)
                                                 Write-back MUX                                        Debug
                                                                                                        Unit



                                                          Introduction    ( 24 )
                    Configurable Features

Supporting FPGA         Xilinx
                                                         On-chip memory
                        Altera
Instruction cache       1-way 512-bytes
                        1-way 4K-bytes
                        1-way 8K-bytes
                        No
Data cache              1-way 4K-bytes
                        1-way 8K-bytes
                        No
Instruction MMU         64-entry TLB
                        128-entry TLB
                        No
Data MMU                64-entry TLB
                        128-entry TLB
                        No
BIST                    RAM BIST
                        No
                                 Introduction   ( 25 )
                      Configurable Features

Burst bus interface       On
                          Off
Bus retry count           1~256
WISHBONE                  Prior to WISHBONE B.3
                          CAP (consecutive address burst)
                          (prior to B.3)
                          WISHBONE B.3
Divider                   On
                          Off
Rotate                    On
                          Off
Multiplier                Fast
                          Slow
                          Off
MAC                       On
                          Off
Multiplier                On
                          Off
                                 Introduction   ( 26 )
                Configurable Features

Clock divide        1 or 2 or 4
Register file       Two port RAM
                    Dual Port RAM
                    Flip-flop based register
Debug unit          HW break point On/Off
                    # of DVR/DCR pair 0~7
Trace buffer        On
                    Off
PIC                 # of interrupt (2~31)
                    Off
                    No
Tick timer          64-entry TLB
                    128-entry TLB
                    No
Qmem                On
                    Off
Store buffer        Entry 4 or 8
                    No
                          Introduction   ( 27 )
                             Custom Instruction
Reserved instructions for custom implementation
   ORBIS32/64
      Eight instructions are reserved
      l.cust1 ~ l.cust8
   ORFPX64
      Two instructions are reserved
      lf.cust1.d, lf.cust1.s
   ORVDX64
      Eight instructions are reserved
      lv.cust1 ~ lv.cust8
Custom instruction implementation
   Add decode logic for the instruction (or1200_ctrl.v)
   Add processing logic for the instruction (or1200_alu.v)




                                        Introduction   ( 28 )
                         Development Tools


  Development Tool          Name                   Version
Compiler                     gcc                        3.4.4    GNU compiler
Binary utility             binutils                     2.16.1   GNU binary utilities
C library                  newlib                       1.10.0   GNU C library
Architecture simulator     or1ksim                      0.2.0    Or100 ISS with peri.
                                                                 models
Debugger                    gdb                          5.3     GNU source level
                                                                 debugger
GUI                        insight                               GUI




                                Introduction   ( 29 )
                     Operating System




  Operating System     Name                       Version
Linux                  Linux                 Kernel 2.4
uClinux                uClinux                      2.0
RTEMS                  RTEMS                       4.5.0    Hard real-time OS
ecos                    ecos                        2.0




                          Introduction   ( 30 )
                  Reference Platform/Example



           Etc.           Name                       Version
SoC platform             orp_soc                               SoC reference platform
Monitor program          orpmon
MP3 decoder              mad-xess                              MAD MP3 player porting
GUI                    Microwindows
examples                                                       Various simple
                                                               examples




                             Introduction   ( 31 )
                               Outline
Software Development with OpenIDEA
   Software Development
   Architecture Simulation
Hardware Development with iNSPIRE-Lite
Hardware/Software Co-Verification with OpenIDEA
Verification Flow




                               Introduction   ( 32 )
          Software Development


Source                                  Code
Browser                                 Editor




                                        Compiler
                                        Window




                Introduction   ( 33 )
Software Development
                       Platform
                              Windows 2000/XP
                       Target Processor
                              or1200
                       Code Editor
                              Source Browser
                              Syntax Highlighting
                              Syntax Checking
                              Block Indent/Dedent/Folding
                              Comment out/uncomment
                              Line Number
                              Find/Replace/Find in Files




      Introduction   ( 34 )
Software Development
                       Compiler
                              gcc 3.4.4
                       Utilities
                              binutil 2.16.1
                              make
                              bin2c
                              bin2hex
                              bin2flash
                              bin2srec
                       Newlib
                              1.10.0




      Introduction   ( 35 )
Software Development
                       Startup Code
                       Link Script File




      Introduction   ( 36 )
             Architecture Simulation
            Source-Level Debugging



OpenIDEA                                 ISS: Architecture Sim


    Debug                                  Processor Model
   Windows
                                                SRAM Model
           Source-Level                             Flash Model
            Debugger
                           Socket               Peripheral Models
                                         C Models




                          Introduction     ( 37 )
          Source-Level Debugging


Source       Register                  Watch            Stack
Browser


                                                                Code




             Debugger                           Break Point




                        Introduction   ( 38 )
Source-Level Debugging
                        Debugger
                               gdb 5.0
                        C Source-Level Debugging
                               Break
                               Step
                               Watch, etc.
                        Assembly-Level Debugging
                               Instruction Step
                               Register View, etc.




       Introduction   ( 39 )
Architecture Simulation
                        Processor Architecture Exploration
                               Core
                               MMU
                               Cache, etc.
                        System-Level Simulation with Peripheral
                        Models
                               Memory
                               UART
                               Ethernet
                               VGA, etc.
                        Performance Profiling
                               Execution Log
                               Memory Profile, etc.




       Introduction   ( 40 )
                                  Agenda
Software Development with OpenIDEA
Hardware Development with iNSPIRE-Lite
   Automatic Hardware Composition
   Open-Source Library
   Simulation/Synthesis/Prototyping
Hardware/Software Co-Verification with OpenIDEA
Verification Flow




                                      Introduction   ( 41 )
                                               iNSPIRE
                                                                          HDL Simuilation
          HDL                                                              Environment
           HDL
            HDL
                                                                            Synthesis &
                                                                              Mappnig
                                                                            (for FPGA)
          EDIF
           EDIF                                                            Cycle-Level &
            EDIF
                                                                         Transaction -Level
                                                                           Co-Simuilation
                                                                            Environment


                                              Library


Integrated Design Environment for Hardware Development
   Architecture Exploration
   Generation of
       HDL Simulation Environment
       SystemC Simulation Environment
       Synthesis & FPGA Mapping
       Cycle-Level & Transaction-Level Co-Simulation Environment
   Supporting Various Library




                                                 Introduction   ( 42 )
Architecture-Wizard
                       LEGO-Brick-Like Hardware Composition
                              GUI-Based Hardware Composition
                              Various IP Library
                                 Open Source IP
                       Architecture Exploration
                              IP Properties




      Introduction   ( 43 )
Architecture-Wizard
                       Bus Generation
                              AMBA AHB
                              AMBA APB
                              WISBHBONE
                       Bus Architecture Exploration
                              Bus Architecture
                              Address Map
                              Priority, etc.




      Introduction   ( 44 )
IP Library
                  OpenCores Library
                         License (L)GPL
                           OR1200
                           OR1200 Debug
                           Audio
                           Video
                           Ethernet
                           CAN
                           DMA
                           PS2, etc.
                  Dynalith Library
                          FLASH Controller
                          SRAM Controller
                          JTAG to USB, etc.




 Introduction   ( 45 )
IP Library
                  RTL Source
                  Synthesis Script
                  Example
                         Hardware
                         Software




 Introduction   ( 46 )
             Simulation/Synthesis
                                           Simulation Environment
                                              Top Module Generation
Simulation                                    Simulation Model Connection
Synthesis                                        SRAM, SDRAM, UART, etc.
Emulation                                     Simulation Script
                                           Synthesis
                                              Top Module Gereration
                                              Synthesis Script
                                              Synthesis Assist
                                           FPGA P&R
                                              FPGA Mapping Script
                                              P&R Assist




                   Introduction   ( 47 )
                                Agenda
Software Development with OpenIDEA
Hardware Development with iNSPIRE-Lite
Hardware/Software Co-Verification with OpenIDEA
   Debugger + ISS
   Debugger + ISS + HDL Simulator (SystemC)
   Debugger + ISS + HDL Simulator + FPGA
   Debugger + HDL Simulator (+ FPGA)
   Debugger + FPGA Prototyping
   Debugger + ASIC
Verification Flow




                                 Introduction   ( 48 )
                                     1. SW Simulation
OpenIDEA (Debugger+ISS)
   Software Development




           OpenIDEA                           ISS

                                                                                Profile/Log
               Debug                            Processor Model
              Windows
                                                    SRAM Model
                                                                                 Terminal
                      Source-Level                    Flash Model
                       Debugger
                                     Socket              UART Model                 Hello World.
                                              C Models                 Socket




                                               Introduction   ( 49 )
         2.1 HW/SW Co-Simulation (IP Verification)
OpenIDEA (Debugger+ISS) + Third Party HDL Simulator
   IP Verification
   Device Driver Development




          OpenIDEA                           ISS                                HDL Sim.

                                               Processor Model
              Debug
             Windows                               SRAM Model
                                                        IP1            Socket
                     Source-Level                         IP2
                      Debugger                                                         IP3
                                    Socket
                                             C Models




                                               Introduction   ( 50 )
        2.2 HW/SW Co-Simulation (System-Level)
OpenIDEA (Debugger+ISS) + Third Party HDL Simulator + FPGA Board (Dynalith)
   System-Level Co-Simulation




            OpenIDEA                           ISS                                HDL Sim.

                                                 Processor Model         Socket         BUS
                Debug
               Windows
                                                                                   SRAM Model
                                                                                        IP1
                       Source-Level
                        Debugger                                                         IP2
                                      Socket
                                                                                             IP3
                                               C Models




                                                 Introduction   ( 51 )
                   3 HW/SW Co-Simulation/Co-Emulation
 OpenIDEA (Debugger+ISS) + Third Party HDL Simulator + FPGA Board (Dynalith)
     System-Level Co-Simulation/Co-Emulation




OpenIDEA                           ISS                                        HDL Sim.                   FPGA


                                     Processor Model              Socket            BUS        PCI/USB
    Debug
   Windows
                                              SRAM Model                            IP1                         IP2
           Source-Level
            Debugger
                          Socket
                                                                                         IP3
                                   C Models




                                                           Introduction    ( 52 )
               4.1 HW Simulation with SW Debugging
OpenIDEA (Debugger) + Third Party HDL Simulator
   HW/SW Co-Verification with Accurate Processor Model
   SW Debugging with HW Probing




                OpenIDEA                           HDL Sim.


                    Debug                            Processor Model
                   Windows                                             IP1
                                                                       IP2
                                                             BUS
                           Source-Level                                IP3
                            Debugger
                                          Socket          SRAM Model
                                                   C Models




                                           Introduction    ( 53 )
                    4.2 HW Simulation with SW Debugging(2)
OpenIDEA (Debugger) + Third Party HDL Simulator + FPGA Board (Dynalith)
   HW/SW Co-Verification with Accurate Processor Model
   SW Debugging with HW Probing




    OpenIDEA                           HDL Sim.                                       FPGA Board


        Debug                                                               PCI/USB
                                         Processor Model
       Windows                                                       IP1

                                              BUS                                          IP2
               Source-Level                                           IP3
                Debugger
                              Socket      SRAM Model
                                       C Models




                                                    Introduction   ( 54 )
                5. HW Prototyping SW Debugging
OpenIDEA (Debugger) + FPGA Board (Dynalith)
   HW/SW Co-Verification with Source-Level Debugger and BILA (Built In Logic Analyzer) or
   ChipScope(Xilinx)




           OpenIDEA                            FPGA Board


               Debug                            Processor Model
              Windows                                                  IP1
                                                                       IP2
                                                      BUS
                      Source-Level                                     IP3
                       Debugger      PCI/USB     SRAM Model
                                      JTAG




                                               Introduction   ( 55 )
                           6. In Circuit Emulation (ICE)
OpenIDEA (Debugger) + Evaluation Board/FPGA Board (Custom)
   In-Circuit Emulation
   Software Development with Real Platform




      OpenIDEA                                                 ASIC Board / Custom FPGA Board

                                                                 ASIC/FPGA
                                      OpenICE
          Debug
                                                                    Processor
         Windows                                                                      IP1
                                                                          BUS         IP2
                 Source-Level
                                                                                       IP3
                  Debugger                                        SRAM Model
                                USB             JTAG




                                                Introduction     ( 56 )
                              Agenda
Introduction to OpenRISC
Software Development with OpenIDEA
Hardware Development with iNSPIRE-Lite
Hardware/Software Co-Verification with OpenIDEA
Verification Flow




                               Introduction   ( 57 )
                             Hardware Design/Verification Flow
                              RTL Design of Each IP
Individulal IP
  Design &
 Verification           Individulal IP Verification Using HDL
                                      Test-Bench

System-Level                 IP Verification in System
HW-SW Co-
 Verification
                          System-Level RTL Verification
           RT-Level




                                 FPGA Prototyping

                                     Synthesis
           Gate-Level




                               Gate-Level Simulation

                                        PnR

                               Static Timing Analysis


                               Post PnR Simulation


                                                                Introduction   ( 58 )
                                        IP Design and Verification
                              RTL Design of Each IP
Individulal IP
  Design &                                                                     HDL Simulation
 Verification           Individulal IP Verification Using HDL
                                      Test-Bench
                                                                               iNSPIRE                       HDL Simulator
System-Level                 IP Verification in System                                                       Simuilation Top
HW-SW Co-                                                                                                       DUV
 Verification                                                                                                                      Driver/Phy/Mem
                                                                                 Architecture                            IP
                                                                                                                                      ory Model
                          System-Level RTL Verification                            Wizard
                                                                                                Generation
           RT-Level




                                                                                                                      Test-bench
                                                                                                                                            Socket
                                 FPGA Prototyping

                                     Synthesis
           Gate-Level




                               Gate-Level Simulation

                                        PnR

                               Static Timing Analysis


                               Post PnR Simulation


                                                                Introduction    ( 59 )
                                        IP Design and Verification
                              RTL Design of Each IP
Individulal IP
  Design &                                                                     Co-Emulation (Acceleration)
 Verification           Individulal IP Verification Using HDL
                                      Test-Bench
                                                                                                iNSPIRE

System-Level                 IP Verification in System                                            Architecture   Design Flow
HW-SW Co-                                                                                           Wizard         Wizard
 Verification
                          System-Level RTL Verification                    Generation
           RT-Level




                                                                                HDL Simulator                       FPGA Board
                                 FPGA Prototyping
                                                                                 Simuilation Top                     FPGA
                                     Synthesis                                                                        DUV
           Gate-Level




                               Gate-Level Simulation                                    Test-                                    Driver/Phy
                                                                                                      Proxy              IP
                                                                                        bench                                     /Memory

                                        PnR

                               Static Timing Analysis


                               Post PnR Simulation


                                                                Introduction   ( 60 )
                         System-Level HW/SW Co-Verification (RTL)

                              RTL Design of Each IP
Individulal IP
  Design &
 Verification           Individulal IP Verification Using HDL
                                      Test-Bench

System-Level                 IP Verification in System
HW-SW Co-                                                                      2.1 HW/SW Co-Simulation
 Verification
                          System-Level RTL Verification
           RT-Level




                                                                               OpenIDEA                           ISS                          HDL Sim.
                                 FPGA Prototyping
                                                                                                                    Processor Model
                                                                                   Debug
                                     Synthesis                                    Windows                               SRAM Model
                                                                                                                             IP1      Socket
           Gate-Level




                                                                                          Source-Level                         IP2
                                                                                           Debugger                                                   IP3
                               Gate-Level Simulation                                                     Socket
                                                                                                                  C Models


                                        PnR

                               Static Timing Analysis


                               Post PnR Simulation


                                                                Introduction    ( 61 )
                         System-Level HW/SW Co-Verification (RTL)

                              RTL Design of Each IP
Individulal IP
  Design &
 Verification           Individulal IP Verification Using HDL
                                      Test-Bench

System-Level                 IP Verification in System
HW-SW Co-                                                                      4.1 HW Simulation with SW Debugging
 Verification
                          System-Level RTL Verification
           RT-Level




                                                                               OpenIDEA                           HDL Sim.
                                 FPGA Prototyping
                                                                                    Debug                           Processor Model
                                                                                   Windows                                            IP1
                                     Synthesis
                                                                                                                                      IP2
           Gate-Level




                                                                                                                         BUS
                                                                                          Source-Level                                IP3
                               Gate-Level Simulation                                       Debugger
                                                                                                         Socket      SRAM Model
                                                                                                                  C Models
                                        PnR

                               Static Timing Analysis


                               Post PnR Simulation


                                                                Introduction    ( 62 )
                         System-Level HW/SW Co-Verification (RTL)

                              RTL Design of Each IP
Individulal IP
  Design &
 Verification           Individulal IP Verification Using HDL
                                      Test-Bench

System-Level                 IP Verification in System
HW-SW Co-                                                                      4.2 HW Simulation with SW Debugging
 Verification
                          System-Level RTL Verification
           RT-Level




                                 FPGA Prototyping

                                                                               OpenIDEA                           HDL Sim.                            FPGA Board
                                     Synthesis
                                                                                                                                            PCI/USB
           Gate-Level




                                                                                   Debug                            Processor Model
                                                                                  Windows                                             IP1

                               Gate-Level Simulation                                                                     BUS                               IP2
                                                                                          Source-Level                                IP3
                                                                                           Debugger
                                                                                                         Socket      SRAM Model
                                                                                                                  C Models
                                        PnR

                               Static Timing Analysis


                               Post PnR Simulation


                                                                Introduction     ( 63 )
                         System-Level HW/SW Co-Verification (RTL)

                              RTL Design of Each IP
Individulal IP
  Design &
 Verification           Individulal IP Verification Using HDL
                                      Test-Bench

System-Level                 IP Verification in System
HW-SW Co-                                                                      5. HW Prototyping with SW Debugging
 Verification
                          System-Level RTL Verification
           RT-Level




                                 FPGA Prototyping

                                                                               OpenIDEA                            FPGA Board
                                     Synthesis
           Gate-Level




                                                                                   Debug                            Processor Model
                               Gate-Level Simulation                              Windows                                             IP1
                                                                                                                                      IP2
                                                                                                                         BUS
                                                                                          Source-Level                                IP3
                                        PnR                                                Debugger      PCI/USB     SRAM Model
                                                                                                          JTAG


                               Static Timing Analysis


                               Post PnR Simulation


                                                                Introduction    ( 64 )
               System-Level HW/SW Co-Verification (Gate-Level)

                              RTL Design of Each IP
Individulal IP
  Design &
                        Individulal IP Verification Using HDL
 Verification
                                      Test-Bench
                                                                               4.1 HW Simulation with SW Debugging
                                                                               OpenIDEA                           HDL Sim.
System-Level                 IP Verification in System
HW-SW Co-
                                                                                    Debug                           Processor Model
 Verification                                                                      Windows                                            IP1
                          System-Level RTL Verification                                                                               IP2
                                                                                                                         BUS
           RT-Level




                                                                                          Source-Level                                IP3
                                                                                           Debugger
                                                                                                         Socket      SRAM Model
                                 FPGA Prototyping                                                                 C Models


                                     Synthesis
           Gate-Level




                               Gate-Level Simulation

                                        PnR

                               Static Timing Analysis


                               Post PnR Simulation


                                                                Introduction    ( 65 )
                                       TM
OpenIDEA                                                OpenRISC Development Toolkit
                                              In-Circuit Emulation
 OpenIDEA                                        With ASIC                                  ASIC
 Software Development                             Source-Level SW Debugging
 Processor Architecture Simulation                JTAG Connection to PC
 Source-Level Debugging


                                              HW/SW Co-Emulation
                                                  With FPGA Prototype Board (iNCITE™ )                         iNCITE
                                                  Source-Level SW Debugging
                                                  Signal-Level HW Debugging Using BILA
                                                  Fast USB 2.0 Connection to PC
                                                  Various Peripherals Supporting




                                              HW/SW Co-Simulation
                                                  With Third-Party HDL Simulator         3rd-Party HDL Simulator
                                                  Source-Level SW Debugging
                                                  Signal-Level HW Debugging

 iNSPIRE-Lite
  Graphical Architecture Composition
  Automatic Hardware Generation
  Various Open-Source Library


                                                                       “OpenIDEA”는 OpenRISC 기반의 SoC 제작을 위한 하드웨어-소프
                                                                       트웨어 통합 개발 환경입니다.
                                                                       자동화된 하드웨어와 소프트웨어 개발 환경을 지원하며, 다양한 형태
                                                                       의 하드웨어/소프트웨어 통합 시뮬레이션 및 에뮬레이션을 통한 검증
                                                                       을 지원합니다.

                                                                                               (주)다이나릿시스템
 전화: 02) 556-0020             Fax: 02) 556-2252          E-mail: contact@dynalith.com        http://www.dynalith.com
Design and verification steps using OpenIDEA
                                  ISS-based software simulation
                                          It uses OpenRISC ISS to run software
                                          and pure-functional hardware model for
                                          hardware.
                                  ISS-HDL co-simulation
                                          It uses OpenRISC ISS to run software
                                          and RTL hardware model running on top
                                          of HDL logic simulator.
                                  HDL-based simulation
                                          It uses a whole system including Open-
                                          RISC core running on top of HDL
                                          simulator and the core is controlled by
                                          debugger.
                                  FPGA-based emulation
                                          It uses OpenRISC core to run software
                                          and hardware blocks in FPGA.




                  Introduction   ( 67 )
Recommended design and verification steps
                                 1. ISS-based software simulation using
                                 OpenIDEA.
                                 2. Building system hardware model using
                                 iNSPIRE-Lite.
                                 3. ISS-HDL co-simulation using
                                 OpenIDEA and HDL simulator.
                                 4. Building system hardware for FPGA
                                 using iNSPIRE-Lite.
                                 5. FPGA-based emulation using
                                 OpenIDEA and iNCITE.




                 Introduction   ( 68 )
UART example
                   Example system
                           OpenRISC 1200 processing core
                           Memory controller
                           UART (Universal Asynchronous Receive
                           and Transmit)
                           WISHBONE bus
                   The user application program will be
                   loaded into the SSRAM after cross-
                   compilation, and run by the OpenRISC
                   processing core.
                   The user application program simply
                   controls the UART in order to get and put
                   character data through the serial cable,
                   which is connected through the Line
                   Driver and UART.




   Introduction   ( 69 )

								
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