RF and mm-Wave Research by c1z1Y38


									RF and mm-Wave Research

         Ali M. Niknejad
         Robert Brodersen

     BWRC 2004 Summer Retreat
   University of California at Berkeley
Presentation Outline

    Research Focus
    60 GHz Update
    COGUR Project
    BSIM Update
            Research Focus Areas (I)

       COGUR                               60 GHz WLAN

    Dynamic Radio                           Gb/s Data Rates
Multistandard Operability              Multi-Antenna Architecture
   Broad/Multi band                       Sub-100nm CMOS
   Short/Long Range
                                 WLAN at 17/24/40 GHz
           Research Focus Areas (II)
  Organic Transistors                    FinFet Devices
(with Prof. Subramanian)                 (with Prof. King)

  Inductor/Capacitors                   Sub 65 nm CMOS
     Active Devices                    Analog Performance
 Oscillators/Amplifiers               Microwave Performance
   Power Harvesting

                           BSIM-DG      Next Generation
   Low Cost RFID                      Communication Circuits
60 GHz Transceiver Update

 Chinh Doan, Sohrab Emami, David Sobel
    Mounir Bohsali, Brian Limketkai,
      Sayf Alalusi, Patrick McElwee
   Why is operation at 60 GHz interesting?

                                                                 57 dBm

                                                                 40 dBm

Lots of Bandwidth!!!
      7 GHz of unlicensed bandwidth in the U.S. and Japan
      Europe CEPT “there is an urgent need to identify and harmonize civil
       requirements in the frequency range 54–66GHz.”
                   60 GHz Challenges

   High path loss at 60 GHz (relative to 5 GHz)
       Antenna array results in better performance at higher frequency
        because more antennas can be integrated in fixed area
   Silicon substrate is lossy – high Q passive elements difficult
    to realize?
       No, the Q factor is even better at high frequencies with T-lines, MIM
        caps, and loop inductors (Q > 20)
   CMOS device performance at mm-wave frequencies
   CMOS building blocks at 60 GHz
   Design methodology for CMOS mm-wave
   Low power baseband architecture for Gbps communication
    60 GHz CMOS Wireless LAN System

                       10-100 m

   A fully-integrated low-cost Gb/s data communication using 60
    GHz band.
   Employ emerging standard CMOS technology for the radio
    building blocks. Exploit electronically steer-able antenna
    array for improved gain and resilience to multi-path.
           A Leap Forward for CMOS

                                          Where we are now
                                X           with 130 nm

   CMOS offers two orders of magnitude cost reduction
    while providing higher integration and reliability
   Each new process generation moves it 20-40% higher
         60 GHz Design Methodology
   Characterize active devices
       Small-signal models for 130 nm and 90 nm CMOS up to 65 GHz
       Large-signal models (gain compression, mixing, power)
   Characterize passive devices
       transmission lines, bypass/coupling capacitors, varactors, chokes
   Build library of active and passive devices
   Use library to build and validate modeling
       Bandpass filters, quadrature couplers
   Verify performance of key building blocks at 60 GHz
       filters, amplifiers, mixers, oscillators
   Investigate baseband architecture to process 1 Gb/s
   Integrate building blocks into 60 GHz front-end
   Build integrated package antenna array (w/ VTT
   Interface to analog baseband
130-nm CMOS Maximum Gain

                   VGS = 0.65 V
                   VDS = 1.2 V
                   IDS = 30 mA
                   W/L = 100x1u/0.13u
             mm-Wave BSIM Modeling

   Compact model with extrinsic
   DC I-V curve matching
   Small-signal S-params fitting
   Large-signal verification

   Challenges:
        Starting with a sample which is
         between typical and fast
        Millimeter-wave large-signal
        Noise
        3-terminal modeling
                       DC Curve Fitting

    Measured and modeled IDS vs. VDS.   Measured and modeled gm vs. VGS.

   I-V measurements were used to extract the core BSIM
    parameters of the fabricated common-source NMOS.
           Model Extraction: Small-Signal

   Extensive on-wafer S-parameter
    measurement to 65 GHz over a
    wide bias range
   Parasitic component values
    extracted using a hybrid
    optimization algorithm in Agilent
   The broadband accuracy of the
    model verifies that using lumped
    parasitics is suitable well into the
    mm-wave region.
Large-Signal Verification

            Harmonics power measurement
                Class AB operation
                Large-Signal amplification at
                 60 GHz
     Transmission line design of an LNA
Load, Matching
   And Bias


                          Matching           Performance derived from
                                             measured components:
                          And Bias           Gain > 11 dB
                                             Return loss > 20 dB
                                             Power = 54 mW

 How do we model these transmission lines?
    Co-planar (CPW) and Microstrip T-Lines


   Microstrip shields EM fields from
   CPW can realize higher Q inductors
    needed for tuning out device
   Use CPW
    40-GHz and 60-GHz CMOS Amplifiers

                                          11.5-dB Gain
            18-dB Gain
                                           @ 60 GHz
             @ 40 GHz

   Design methodology is incredibly accurate!
   Power consumption: 36 mW (40 GHz), 54 mW (60 GHz)
   Noise and distortion measurements in progress
     Modeling of 60-GHz CMOS Mixer

   Conversion-loss is better than 2 dB
    for PLO=0 dBm
   IF=2GHz
   6 GHz of bandwidth
            Combining LO and RF Signals
   Branch line 90º coupler
       Long lines for phase shift
       Hi insertion loss
       Area

   Reducing t-line length

   Transistors provide
    some free caps!
           Coupler’s Simulation Results
   Should be no problem with
    the doughnut and bridges
                    Published CMOS Circuits

                     We have LNAs and
                       Mixers here!


            50                                                 Amplifiers




             1999    2000   2001   2002   2003   2004   2005
Hybrid-Analog Receiver Architecture

                                         Proposed Baseband          Clk   Clock Rec
                                                                               Timing, DFE
           IF                                    Complex
    RF                            VGA    ejq                                  Carrier Phase,
                                                   DFE   BB’Q                  Estimators



    Condition the signal prior to quantization
               Phase and timing recovery, equalization in analog domain
               Greatly simplifies requirements on the ADC/VGA circuitry
    Synchronization estimators in the digital domain
               Can still use robust digital algorithms for synchronizaiton
            The open questions are…
   Inexpensive packaging strategies
       Flip-chip bonding
       LTCC
   Noise modeling and performance
   Breakdown voltage and PA
   The system design strategy to use the 7 GHz of bandwidth
    and simplify circuit requirements
   Realizing the high level of antenna gain needed to provide
    robust links
       Aperture antennas
       Antenna arrays
       On-chip antennas?
   At 130 nm, mainstream digital CMOS is able to exploit the
    unlicensed 60-GHz band
   Accurate device modeling is possible by extending RF
    frequency methodologies
   A transmission-line-based circuit strategy provides
    predictable and repeatable low-loss impedance matching
    and filtering
Cognizant Universal Radio
           Axel Berny
            Gang Liu
          Zhiming Deng
      Nuntachai Poobuapheun
              COGUR Design Goals
   An agile dynamic radio cognizant of its environment
   Universal operation ensures multi-standard and future
    standard compatibility
   Cognitive behavior allows spectrum re-use, underlay, and
   Dynamic operation allows low power (only need linearity
    and low-phase noise VCO in a near-far situation)
   Multi-mode PA can work in “linear” mode for OFDM and
    high PAR modulation schemes. Efficiency is maintained
    while varying output power
From Super-Het to Low/Zero IF Architectures

    Today fully integrated radios are often low-IF or zero-IF to reduce IF
     SAW filters
    Receiver front-end is often integrated in a single chip. PA is a separate
     chip or module. Synthesizer is often a separate chip.
    These radio architectures are optimized for a specific standard (image
     rejection, linearity, filtering, bandwidth)
    How do we integrate 5-10 such radios into one wireless device?
COGUR Transceiver

                 Broadband dynamic
                 Wide tuning agile
                  frequency synthesizer
                 Dual-mode broadband
                  PA with integrated
                  power combining and
                 Linear VGA or
                 High-speed
                  background calibrated
               COGUR Front End Specs
   Frequency: 800 MHz – 2.5 GHz (Cellular, WLAN, WPAN)
   Front-End:
        LNA: S21 > 12 dB, NF < 3 dB, IIP3 > 0 dBm
        Passive Image Reject Mixer (20 dB), G >-5 dB, NF<12 dB, IIP3 > +20 dBm
        Baseband analog filter: 40 dB blocker attenuation (5th order filter)
        VGA: Gain 10 – 70 dB, NF = 5 dB, IIP3 = -10 dBm, + 10 dBm
        PA: Multi-mode Class A/F, peak power 250mW/500mW
        On-chip power combining with dynamic output power control and near
         constant efficiency at power back-off
   Synthesizer:
        Frequency resolution: 2.5kHz
        Phase noise: < -116dBc/Hz at 600kHz
        Settling time: < 150us
   ADC:
        Resolution 10-bits
        200 MHz Sampling Rate
        Background Calibrated
             Broadband LNA Topology
   Two Stage input matching
    improves bandwidth by 3x
   Input network is a Chebychev
   Filter termination provided by
    active device
   Very similar to workhorse
    inductively degenerated
    common source amplifier
   Noise figure optimization
    possible (NFmin)
   Power match almost equal to
    noise match
Broadband LNA Covers 800 MHz – 2.5 GHz

18                                                                6

15                                                                5

12                                                                4

 9                                                                3

 6                                                                2

                                         S21 (dB)
 3                                                                1
                                         NF (dB)

 0                                                                0
     0   0.5   1      1.5            2   2.5        3   3.5   4
                   Frequency (GHz)
              Dynamic LNA Performance
     18                                                               3

     15                                                               0

                                                      S21 (dB)
     12                                               NF (dB)         -3
                                                      S11 (dB)

     9                                                                -6

     6                                                                -9

     3                                                                -12

     0                                                                -15
          0     2      4       6         8       10    12        14
                             Bias Current (mA)
   Gain > 12 dB for bias current varying from 2 mA – 14mA
   NF < 3 dB for bias current varying from 2 mA – 14 mA
   Input match better -9 dB for current varying from 2mA – 14m A
    Wideband Fractional-N Synthesizer

   Core VCO has a tuning range of 2:1 to cover almost any
    frequency band. Loop must be stable and low-noise over
    entire range.
    Broadband VCO with Switch Caps

   Core VCO employs switched capacitor tuning to cover
    over 1 GHz of tuning range with low Kvco
   Digital calibration loop keeps amplitude of VCO fixed
    over entire range
Synthesizer Phase Noise Simulation
 Broadband VCO Layout
                        A 1.8 GHz LC VCO
                        1.3 GHz Tuning Range
                        Mixed-signal Amplitude
VCO                     0.18µm CMOS
                        phase noise of –104.7dBc/Hz at
         Peak Det.       a 100kHz
         & Comp.
                        3.2mA from a 1.5V supply

          TX: Class A/F Dual Mode PA
   Design a power amplifier which meets requirements called
    by the next generation wireless communication standards
    while providing backward compatibility with existing
       Integration: fully integrated without any off chip components
       Long talk time: maintain high efficiency over entire output range
       High data rate: amplitude modulation requires high linearity
      Distributive Active Transformer

   Power combining major challenge of
    PA design
   Caltech work has shown that “DAT” is
    promising candidate for fully integrated
    power combining and matching
   Low loss transmission lines form 1:1
   Distributed nature allows
    power/efficiency control
                  BSIM5 Beta is Here
   Brief history of BSIM:
       BSIM3: Industrial standard model, regional threshold based
        model, advanced short-channel device physics
       BSIM4: RF modules, improved holistic noise, leakage currents,
        non-uniform doping, stress effect
   Problems with BSIM3/4:
       Models are inherently regional (sub-threshold is smoothly matched
        to strong inversion). A lot of short-channel effects in VTH.
       Models are source referenced (transistor produces artificial
        discontinuity in specialized applications such as passive mixers)
       Possibility of negative conductance or capacitance
   BSIM5:
       New non-VTH charge-based single-equation core (Q-V).
       I-V and C-V models based on Q-V core.
       Short channel / advanced process effects included from BSIM4
       Bulk referenced model. Smooth and continuous derivatives.

   BWRC Member Companies
   DARPA TEAM Project
   SRC and member companies
   STMicroelectronics and IBM for wafer processing and
    design support
   Agilent Technologies (measurement support)
   National Semiconductor
   Qualcomm
   Analog Devices
   BSIM5 Support: TI, Intel, IBM, AMD,

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