5.4: A 5GHz CMOS Transceiver
for IEEE 802.11a Wireless LAN
David Su, Masoud Zargari, Patrick Yue,
Shahriar Rabii, David Weber, Brian Kaczynski,
Srenik Mehta, Kalwant Singh, Sunetra Mendis,
and Bruce Wooley1
Atheros Communications, Sunnyvale, California
1Stanford University, Stanford, California
Outline
❑ Introduction: 802.11a Wireless LAN
❑ Architecture
❑ Radio Design
• Transmitter
• Receiver
• Frequency Synthesizer
❑ Summary
IEEE 802.11a WLAN
s Frequency: 5 GHz UNII (Unlicensed National
Information Infrastructure)
200mW 800mW
40mW
5.15G 5.25G 5.35G 5.725G 5.825G
s Total UNII Bandwidth: 300 MHz (> IEEE 802.11b)
s Modulation: OFDM
(Orthogonal Frequency Division Multiplexing)
+ BPSK / QPSK / 16QAM / 64QAM
s Data Rate: 6 - 54 Mbps
Spectral-Efficient Modulation
s 64-QAM (Quadrature Amplitude Modulation)
— Large signal to noise ratio > 30dB
• Phase noise
• I/Q mismatch
s OFDM (Orthogonal Frequency Division Mux)
— Large peak to average power ratio of 52 or
17dB
• TX: large power backoff
• RX: large dynamic range
• Some signal clipping can be tolerated
Requires High Linearity
Architecture
Architecture + –
Direct - No off-chip IF filter - LO leakage
Conversion - Single synthesizer - LO pulling
- Quadrature LORF
- DC offset
Traditional - Low LO leakage - Off-chip IF filter
Superheterodyne - Weak LO pulling - Two synthesizers
- No quadrature LO
- Design flexibility
Dual conversion with 1GHz sliding IF
Radio Transceiver
Transmitter
Tx_in
Synthesizer Control
5GHz
Rx_out
Receiver
Dual Transmit Conversion
Freq(Hz)
dc 1G 4G 5G
LOIF LORF
s Radio Frequency (RF) ≠ Local Oscillator (LO)
• LO leakage is out of band
• LO pulling by power amplifier is reduced
LO RF
s Sliding Intermediate Frequency (IF): LO IF -
= --------------
4
• Single synthesizer
• Excellent 1 GHz quadrature for good transmit image
rejection
s Double Image-reject mixers
• Avoid IF filtering of sideband
Transmitter Block Diagram
LORF(I) LOIF(I)
TX_I
PA
RF_OUT LOIF(Q)
5 GHz
TX_Q
LORF(Q) LOIF(I)
Dual Receive Conversion
fIF fRF
Freq(Hz)
dc 1G 3G 4G 5G
LOIF LORF
s No external IF filtering
s Channel selection at Baseband with passive
LC filtering
s Very high IF of 1GHz
• 3GHz image is 2GHz away from 5GHz signal
• Inherent bandpass filtering of 3GHz: –23dBc
• RF mixer: 5-4 = 1GHz (IF) and 5+4 = 9GHz
• No image-reject mixers
Receiver Block Diagram
LORF LOIF (I)
PGA
off-chip RX_I
LC LPF
LNA
DAC Offset
RF_IN
DAC Control
5GHz
off-chip
LC LPF RX_Q
PGA
LOIF (Q)
Synthesizer
s Single synthesizer with sliding IF:
LO RF
LO IF = --------------
-
4
s Divide-by-four generates quadrature LOIF
• Excellent I/Q matching
s P+/N-well varactor
s Frequency Plan:
RF 5.160 to 5.340 GHz 10 MHz spacing
LORF 4.128 to 4.272 GHz 8 MHz spacing
LOIF 1.032 to 1.068 GHz 2 MHz spacing
Synthesizer Block Diagram
8MHz off-chip
PFD CP VCO
RC LPF
32 16/17 LORF
(4GHz)
Decoder 4 LOIF
(1GHz)
Channel Select
5GHz CMOS RF Design
s Advantages:
• Low-cost, high-yield
• Multi-layer interconnect makes decent inductors
• High-level of integration supports sophisticated
digital signal processing*
s Challenges:
• 5 GHz: 0.25µm + narrowband with inductors
• No high-Q BPF: architecture + dynamic range
• Process/Temp Variation: DSP algorithms
• Noise/Power performance limitations
* J. Thomson et al, ISSCC 2002, Paper 7.2
Power Amplifier Design
s Large peak to average ratio (PAR) of 52 or 17dB
s Signal peaks are infrequent: 0.25dB SNR
degradation when PAR reduced to 6dB for
16-QAM*.
s Implications:
• Poor power efficiency
• With 6dB PAR, to obtain 40mW (16dBm) requires
Psat of ~22dBm or 160mW
• With 17dB PAR, to obtain 40mW (16dBm) requires
Psat of ~33dBm or 2W
*Van Nee & Prasad, OFDM for Wireless Multimedia Communications,
Artech House, 2000
Power Amplifier Topology
Vpa = 3.3V
s Class A operation
L2* L3 s Cascoded
Output • 3.3V supply voltage
C2 • Stability
s Capacitive Level-shift
• Metal-2,3,4,5 stacks
Input M2 M3 s Inductive loads
L4* s Differential
• Off-chip balun
Bias
* C.P. Yue and S.S. Wong, IEEE JSSC, May 1998
Power Amplifier Schematic
Vpa=3.3V
L3p L2p L1p L1n L2n L3n
C1p C1n
Vout+ C2p C2n Vout-
M3p M2p M2n M3n
L4p L4n
Bias Bias Bias Bias
Vin- Vin+
PSAT = 22 dBm
Measured BPSK OFDM Spectrum
16.25MHz
POFDM = 17.8 dBm
Measured Transmit Constellation
64QAM (300kHz) modulated signal
Measured Transmit Output Power
18
OFDM Output Power (dBm)
16
14
Carrier Leak –29dBc
12 Spectral Images –51dBc
10
6 9 12 18 24 36 48 54
Data Rate (Mbps)
LNA Schematic
Vdd
Vout
M3 M4
Vin+ M1 M2 Vin-
Lsp Lsn
Receiver NF: LNA to Baseband = 8dB
Programmable Baseband Amplifier
Vdd Vdd
Bias_p
Vout- Vout+
R2 R2
Vin+ R1 Vin-
Bias_n
Vos+ Vos-
Bias_n
offset control
Measured Receiver Performance
10
IF Mixer Output (dBm)
0
Max. Gain
-10
-20
-30
-40 Min. Gain
-50
-60
-90 -80 -70 -60 -50 -40 -30 -20 -10 0
RF Input (dBm)
Voltage Controlled Oscillator (VCO)
Vc
Control Control
M1 M2
Composite Phase Noise at 5GHz
Phase Noise (dBc/Hz) –80
–90
–100
–110
–120
–130
1k 10k 100k 1M 10M
Frequency (Hz)
Die Photograph
Tx
Rx
Logic
Synth
Bias
Measured Performance
TX Output Power Level 22 dBm
RX Chain Noise Figure 8 dB
Phase Noise (∆f=1MHz) –112 dBc/Hz
Supply Voltages 2.5 V & 3.3 V I/O
TX Chain Power Dissipation 790 mW
RX Chain Power Dissipation 250 mW
Synthesizer Power Dissipation 180 mW
Technology 0.25 µm 1P5M CMOS
Package 64-pin LPCC
Die Size 22 mm2
Conclusions
s IEEE 802.11a radio transceiver in 0.25 µm
standard digital CMOS for 5-GHz WLAN
s No external IF filter:
• TX: double image-reject mixers
• RX: very high IF of 1GHz
s Dual conversion with sliding IF: single
synthesizer
s Integration of:
• transmitter with 22dBm output power
• receiver with 8dB noise figure
• synthesizer with –112dBc/Hz (∆f=1MHz)
Acknowledgement
s Support of the Wireless Team at Atheros for
design, layout, and testing. In particular:
H. Dieh, J. Kung, R. Popescu, A. Ong,
J. Zheng, D. Nakahira, R. Subramanian,
J. Kuskin, A. Dao, D. Johnson, C. Lee, L. Thon,
P. Husted, W. McFarland, S. Wong, R. Bahr, T.
Meng
s Assistance of TSMC. In particular: S. C. Wong
and B. K. Liew.