Verification IC Verification Tools Used for Student or Trainee Assessment

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Verification IC Verification Tools Used for Student or Trainee Assessment Powered By Docstoc
					       IC Verification Tools Used for Student or Trainee Assessment
The IPCI system is designed for training professionals and to be used in university education.
Encouraging the student to become involved in setting criteria for evaluation of his or her work
shifts a portion of responsibility to the student. Used sensitively, with more emphasis on student
growth and self-understanding than on arriving at a final grade, self-evaluation can contribute to
a student's ability to structure his or her learning. It can increase a student's ownership for the
learning process.

We propose to use for performance self- or peer evaluation the professional tools for verification
of the integrated circuits (IC) design. These are:
     Logical and Schematics verification and optimisation:
            o Analog simulation using PSpice or HSpice
            o and digital simulation mostly with VHDL and Verilog simulators
     Layout verification:
            o Design Rule Checking (DRC)
            o Circuit Extraction and Parasitic Extraction
            o Layout versus Schematics (LVS): layout against net-list comparison and
                simulations by comparing the extracted net-list with the original one

Layout verification determines whether the polygons that represent different mask layers in the
chip conform to the technology specifications. Design Rule Checking is an essential part of the
back-end design process. It is important to validate the manufacturability of designs before going
into production in order to maximise yield. This is why it is so important to use a DRC to check
all the complex rules associated to the selected foundry processes.
It is not less important to ensure that the designed IC layout does what it is meant to do. So, one
has to perform a valid and complete extraction to verify your results through simulations and by
comparing the extracted netlist with the original one, as well as to study various parasitic
capacitance and distributed RC extraction at transistor and gate levels.

An example for the use of the verification tools for students/trainees evaluation is to ask them to:

      Interpret various specification statements in the rulefile dealing with DRC and LVS
       results databases and reports, DRC rulechecks, LVS device recognition statements
      Interpret simple DRC width and spacing checks
      Interpret complex, state-of-the-art DRC antenna checks
      Identify and locate the following DRC-related problems: external spacing of edges on
       different or same layers; internal spacing of edges on different or same layers;
       measurement of geometry on one layer enclosed by geometry on another
      Identify and locate the following LVS-related problems: shorts and opens, including those
       on power and/or ground nets.

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