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					                                                                SVT




       The CDF Silicon Vertex Trigger
                   Vertex 2002
                      Luciano Ristori
              Istituto Nazionale di Fisica Nucleare
                            Pisa – Italy




Nov 7, 2002           Luciano Ristori - Vertex2002_7Nov02.ppt   1
                                                                          SVT



              The Silicon Vertex Trigger was designed and built for the
              CDF collaboration by people from the following
              institutions:


                     • INFN – Pisa
                     • INFN – Trieste
                     • University of Chicago
                     • Université de Genève




Nov 7, 2002                     Luciano Ristori - Vertex2002_7Nov02.ppt   2
              CDF DETECTOR                               SVT




Nov 7, 2002    Luciano Ristori - Vertex2002_7Nov02.ppt   3
              CDF r-z view                              SVT




Nov 7, 2002   Luciano Ristori - Vertex2002_7Nov02.ppt   4
                       SVX II                                              SVT


                                                        10.6 cm




                                                                  2.5 cm
    90 cm




Nov 7, 2002   Luciano Ristori - Vertex2002_7Nov02.ppt                      5
                                Why and how?                                                           SVT


• Trigger on B hadronic decays
         – B physics studies, eg. CP violation in B decays, Bs mixing
         – new particle searches, eg. Higgs, Supersymmetry
• A b-trigger is particularly important at hadron colliders
         – large B production cross section for B physics
         – high energy available to produce new particles decaying to b
           quarks
         – overwhelming QCD background
              • need to improve S/B at trigger level


• Detect large impact parameter tracks from B decays using the
  fact that (B)1.5 ps


                        Technical challenge!
                                                                                              secondary vertex
                                                                             primary vertex
Nov 7, 2002                        Luciano Ristori - Vertex2002_7Nov02.ppt                             6
              SVT: Silicon Vertex Trigger                                                  SVT


                                                                Inputs:
                                                                –   L1 tracks from XFT (, pT)
                                                                –   digitized pulse heights from
                                                                    SVX II
                                                                Functionalities:
                                                                –   hit cluster finding
                                                                –   pattern recognition
                                                                –   track fitting
                                                                Outputs:
                                                                –   reconstructed tracks
                                                                                        (d, , pT)




Nov 7, 2002           Luciano Ristori - Vertex2002_7Nov02.ppt                             7
              Triggering in Run 2                                             SVT




                                                            Central Tracker (Pt,)
                                                            EM + HAD/EM + Track
                                                            EM+HAD (Jet)
                                                            Muon + Track
                                                            Missing ET, S ET
                                45 kHz
                                                            Si Secondary vertex
                                                            EM shower max, ISO
                                                            Jet Clustering
                                                            Multi object triggers
                                 300Hz



                                                            Farm of ~200 PC’s
                           60 Hz                            running fast versions
                                                            of Offline Code 
                       ~20MB/s
                                                            more sophisticated
                                                            selections
Nov 7, 2002       Luciano Ristori - Vertex2002_7Nov02.ppt                     8
                          CDF Run II trigger architecture                                                                    SVT

                      detector elements

    CAL         COT
                            DØ resultsCES
                           MUON
                                 SVX



                            MUON
                                                                               •      Tracking system
                XFT                              XCES
                            PRIM.
                                                                                         – central outer tracking (COT)
                                                                                         – silicon tracking (SVX II & ISL)
               XTRP
                                                                               •      three-level trigger
   L1           L1            L1                                                         – L1: 5.5 s pipeline
  CAL         TRACK          MUON
                                                                                                    • XFT: L1 2D COT track
                                                                                         – L2: 20 s processing time
              GLOBAL                                                                                • two stages of 10 s
                L1
                                                                               •      SVT at stage 1 of L2
   L2
  CAL
                                          SVT
                                                                                         –     SVX II readout
                                                                                         –     hit cluster finding
          GLOBAL
          LEVEL 2
                                                TSI/CLK                                  –     pattern recognition
                                                                                         –     track fitting



Nov 7, 2002                                               Luciano Ristori - Vertex2002_7Nov02.ppt                            9
              Finding tracks in the silicon                      SVT




Nov 7, 2002           Luciano Ristori - Vertex2002_7Nov02.ppt   10
                        Building the “Pattern Bank”                                SVT

    Instead of looking for hit combinations such that f(x1,x2,x3,…) = 0

1.        Build a database with all patterns corresponding to “good” tracks
2.        Compare hits in each event with all patterns to find track candidates


5

4

3

2

1




In this example:
Straight lines, 5 layers, 12 bins/layer

                    Total number of patterns ~ (12)2*(5-1) = 576

      Nov 7, 2002                       Luciano Ristori - Vertex2002_7Nov02.ppt   11
                                                         AM chip internal structure                                                                    SVT

                                                                                                           AB<6:0> ( R/W MODE)
           SELP<2:0>
                                                                                             ADDRESS DECODER
    SELECT PLANE
      DECODER
                                                  pattern 0                            pattern 1                                    pattern 127
                                                       12 bits word     HIT                                         HIT                               HIT
            DATA BUS MULTIPLEXER




                                   layer0                                                12 bits word                                12 bits word
                                                      12 bits compar.   BIT             12 bits compar.             BIT             12 bits compar.   BIT
                                   layer1

DB<11:0>                           layer2

                                   layer3

                                   layer4

                                   layer5



                                                            COUNT
      OPC<3:0>                                                                    HIT COUNTER
                                                             SHIFT
                                            CONTROL




           ENP*
           SEL*                                                                     MATCH BIT
           CLKB
                                                                                                     ADDRESS ENCODER
        CLKA
         OR*                                                                                                              AB<6:0> (OUTPUT MODE)



      Nov 7, 2002                                                         Luciano Ristori - Vertex2002_7Nov02.ppt                                     12
                    AMchip                               SVT




Nov 7, 2002   Luciano Ristori - Vertex2002_7Nov02.ppt   13
              Amplug: mezzanine board                          SVT




Nov 7, 2002         Luciano Ristori - Vertex2002_7Nov02.ppt   14
                            AM Board                              SVT




128 Amchips                              x16               VME
x 128 patterns
   each
= 16K pattern
   board

                                                           AMbus




Nov 7, 2002      Luciano Ristori - Vertex2002_7Nov02.ppt         15
                        SVT basic architecture                                                         SVT

• Pattern recognition and track fitting done separately and pipelined

              Pattern recognition with Associative Memory (AM)
                  highly parallel algorithm
                  using coarser resolution to reduce memory size
                                                                                 Hits
                          Hits                                                          Associative
                                          Hit Buffer                                     Memory

                                                                            Roads

                                                                         Track
                        Roads + hits                                     Fitter         Tracks
                                                                                        (d, pT, )



              Fast track fitting with linear approximation
                 using full resolution of the silicon vertex detector

Nov 7, 2002                            Luciano Ristori - Vertex2002_7Nov02.ppt                        16
              From non-linear to linear constraints                                  SVT



       Non-linear geometrical constraint for a circle:
                  F(x1 , x2 , x3 , …) = 0




                                                                             D xi


   But for sufficiently small displacements:

      F(x1 , x2 , x3 , …) ~ a0 + a1Dx1 + a2Dx2 + a3Dx3 + … = 0
              with constant ai               (first order expansion of F)

Nov 7, 2002                        Luciano Ristori - Vertex2002_7Nov02.ppt          17
              Constraint surface                            SVT




Nov 7, 2002      Luciano Ristori - Vertex2002_7Nov02.ppt   18
              SVT Wedges                                 SVT




Nov 7, 2002   Luciano Ristori - Vertex2002_7Nov02.ppt   19
                            SVT system architecture                                                                        SVT




 raw data from            Hit Finders
                                                           Sequencer
 SVX front end                                                                        Associative Memory
                                        COT tracks
                                        fromXTRP

                                                                                        roads



              12 fibers

                                            hits                                                           Track Fitter


                                                     Merger                   hits
                                                                                                             to Level 2

                                                                                        Hit Buffer
     x 12 phi sectors




Nov 7, 2002                                 Luciano Ristori - Vertex2002_7Nov02.ppt                                       20
                          SVT: board count                                               SVT

•         Hit Finders       42
•         Mergers           16
•         Sequencers        12                                        INFN
•         AMboards          24
•         Hit Buffers       12                                        INFN & Geneva
•         Track Fitters     12                                        University of Chicago
•         Spy Controls       8
•         XTFA               1
•         XTFB               2
•         XTFC               6
•         Ghostbuster        1

              TOTAL        136        + spares


Nov 7, 2002                 Luciano Ristori - Vertex2002_7Nov02.ppt                     21
                        SVT: board and crate layout                                                 SVT


          CPU               Hit Finder                                    Merger         XTFA

          Tracer            Sequencer                                     Hit Buffer     XTFB

          Spy Control       Associative Memory                            Track Fitter   XTFC




              b0svt00           b0svt07                                  b0svt06         b0svt05




              b0svt01           b0svt02                                  b0svt03         b0svt04


Nov 7, 2002                              Luciano Ristori - Vertex2002_7Nov02.ppt                   22
              Hit Buffer board                             SVT




Nov 7, 2002     Luciano Ristori - Vertex2002_7Nov02.ppt   23
              Hit Finder board                             SVT




Nov 7, 2002     Luciano Ristori - Vertex2002_7Nov02.ppt   24
              Merger board                                SVT




Nov 7, 2002    Luciano Ristori - Vertex2002_7Nov02.ppt   25
              SVT crates in CDF counting room                      SVT




Nov 7, 2002             Luciano Ristori - Vertex2002_7Nov02.ppt   26
              Impact parameter vs. phi                                                       SVT




                                                                           x       phi
d
                         Raw                                                   y
                                                                       d




d
                    Subtracted

                                                                    d = y cos(phi) – x sin(phi)
              phi


Nov 7, 2002               Luciano Ristori - Vertex2002_7Nov02.ppt                           27
                           SVT: beam profile                                                           SVT



      Impact parameter distribution

                                                    This distribution is interpreted as the
                                                    convolution of the actual transverse size of
                                                    the beam spot with the impact parameter
                                                    resolution of the SVT

                                                      sigma ~ 50 um ~ 43 um + 25 um


                                                                    SVT resolution   beam spot size




Nov 7, 2002                       Luciano Ristori - Vertex2002_7Nov02.ppt                             28
                    Tevatron Beam Moves!                                               SVT


Beam center at
 beginning of      25 microns
store normally
 stable within
  20 microns.                                                             TeV store
  Drift during                                                            ~12 hours
the duration of
                   x position
a store of 20 to      (m)
 30 microns in
                    x slope
   x,y (often       (rad)
  correlated)
                   y position
 Beam slope           (m)
 more stable
                    y slope
(variation <20      (rad)
microradians)

   Nov 7, 2002                  Luciano Ristori - Vertex2002_7Nov02.ppt               29
                            Hadronic B decays with SVT                                                                SVT

                                                Two paths
@3x   1031 cm-2       s-1

            • L1:                                                         • L1:
                    •Two XFT tracks                                                   •Two XFT tracks
~ 3 KHz
                    •Pt > 2.5 GeV; Pt1 + Pt2 > 6.5 GeV                                •Pt > 2.5 GeV; Pt1 + Pt2 > 6.5 GeV
                    •D < 135°                                                        •D < 135°

            • L2:                                                         • L2:
                    •d0>100 m for both tracks                                        •d0>120 m for both tracks
~ 5 Hz              •Validation of L1 cuts with D>20°                                •Validation of L1 cuts with D>2°
                    •Lxy > 200 m                                                     •Lxy > 200 m
                    •d0(B)<140 m                                                     •d0(B)<140 m

                                     Two body                                                         Many body
                                      decays                                                           decays

      Nov 7, 2002                           Luciano Ristori - Vertex2002_7Nov02.ppt                                  30
              CDF as a Charm factory?                          SVT




Nov 7, 2002         Luciano Ristori - Vertex2002_7Nov02.ppt   31
              Fully Hadronic B decays                          SVT




Nov 7, 2002         Luciano Ristori - Vertex2002_7Nov02.ppt   32
                                 SUMMARY                                   SVT


              • The design and construction of SVT was a significant
                step forward in the technology of fast track finding
              • We use a massively parallel/pipelined architecture
                combined with some innovative techniques such as
                the associative memory and linearized track fitting
              • SVT is now fully commissioned and we have shown
                we can handle all the technical challenges related to
                detector and beam alignment in real time
              • Performance of SVT is as expected
              • CDF is triggering on impact parameter and collecting
                data we hope will soon lead to significant physics
                results



Nov 7, 2002                     Luciano Ristori - Vertex2002_7Nov02.ppt   33

				
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