FREQUENTLY ASKED QUESTIONS
WHAT ARE THE PREREQUISITES? CONTACT INFORMATION
• Acceptance by the ECE Department.
Process requires a sufficient background
CDR Dave Neely, USN
in mathematics and technical undergradu-
ECE Dept. – DL, Outreach
ate studies. Applicants with a BSEE degree
will usually satisfy the requirements.
• Command/Company Endorsement. firstname.lastname@example.org
Roberto Cristi, Ph.D.
IS THERE A SERVICE COMMITMENT? ECE Dept. – DL Business Manager GRADUATE CERTIFICATE
There is no service commitment associated with
the FTC Certificate Program.
WHO IS ELIGIBLE?
Applicants with a US government affiliation,
Monique P. Fargues, Ph.D.
ECE Dept. – Assoc. Chair for FAULT TOLERANT
government laboratory engineers, active or
reserve military personnel, Navy civilians, current
NPS resident students, and a limited number of
A DISTRIBUTED LEARNING PROGRAM
contractors sponsored by Department of Defense
For more information on the
ECE department, go to:
WHEN DOES THE PROGRAM START?
Annually, beginning in the Fall quarter. www.nps.edu/ece
For more information on other
HOW LONG DOES IT TAKE TO COMPLETE? NPS DL programs, go to:
Usually 3 quarters (1 course per quarter).
U1 U4 Produced by:
Naval Postgraduate School
Center for Educational
Design, Development, and Distribution
U2 U3 411 Dyer Rd., Knox 120, Monterey, CA 93943 Naval Postgraduate School
THE PROGRAM THE CURRICULUM THE OUTCOMES
The Fault Tolerant Computing Certificate Program EC3800 Microprocessor Based System Design (3-2) Upon completion of the Fault Tolerant Computing
provides a solid foundation in an area of significant Advanced microprocessor system for embedded Certificate Program, students will have the practical
importance and promise. Students will experience a control applications. Topics include CPU operation experience and cognitive skills required to:
mix of instruction and hands-on laboratory work. and timing, address decoding, exception processing, • Analyze, design and evaluate fault toler-
design of static and dynamic memory systems, bus
ant computer systems and apply these
arbitration, and direct memory access controllers.
skills in a military systems environment.
The laboratory consists of a design project integrat-
ing hardware and software using a state-of-the-art • Apply knowledge of conventional micro-
development system. processor and programming fault tolerant
computer systems using Verilog simulations.
EC4810 Fault Tolerant Computing (3-2)
Testing of circuits and systems. Redundancy to • Analyze, design and evaluate hardware
achieve reliability. Design-for-testability, and built-in fault tolerant computer systems by apply-
self test. Software and systems reliability. ing knowledge of test techniques, hardware
redundancy techniques, design-for-testability,
CS4920 Advanced Topics (3-2) built-in self test and systems diagnosis.
Designed to support advanced group study of
reliability through software. Rollback and • Analyze, design and evaluate software
recovery techniques. fault tolerant computer systems by apply-
ing knowledge of software implemented
redundancy, rollback, and recovery.
x1 x2 x3 f1 f2 f3 f4 Graceful degradation Advance Your Career!
C0 Much of the cost of digital systems is
C1 due to testing. As a result, there is much
research on the Design for Testability
B1 (DFT) problem. Here, the designer adds
α × × × x1 x2 x3 circuits whose only purpose is to ease
the testing burden. It may be as simple
× × × x1 x3
as connecting an internal point to an
×β × x1 x2 output pin to make it accessible as a
Shift B4 test point. Often, it involves sophisti-
Register × × × x2 x3 cated changes to the circuit. Students
× in the Fault Tolerant Computing Certifi-
cate Program will study these concepts
OUT both in the classroom and the lab.
Design For Testability www.nps.edu/ece