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ModelSim 6.5 Update Overview

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ModelSim 6.5 Update Overview Powered By Docstoc
					        ModelSim DE                 ™




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                            ModelSim DE
         Leading Single & Mixed Language Simulation
   Native single kernel verification environment
    —   Verilog 1995, 2001, 2005
    —   VHDL 1987/1993/2002/2008
    —   SystemVerilog for design
    —   SystemVerilog and PSL assertions
    —   SystemC with SCV and TLM, C, C++ (option)

   Broadest type support at language boundaries
    —   Component/module instantiation
    —   SignalSpy™
    —   SC control, observe and connect methods
    —   Only simulator able to share type definitions written in one
        package in both VHDL and SystemVerilog
            Preserving full benefits of strong type checking



                                    Mentor Graphics
                                    ModelSim DE 6.5
                        ModelSim DE
         Leading Single & Mixed Language Simulation

   Integrated debug and analysis capabilities
    —   Comprehensive root cause analysis
    —   Coverage analysis and reporting
    —   Commands/GUI consistent across languages, HW platforms
        and abstraction levels


   SecureIP support
    —   Higher performance Xilinx IP
    —   Native support for VHDL and Verilog


   Linux and Windows support

                              Mentor Graphics
                              ModelSim DE 6.5
                          ModelSim DE
          Leading Assertion and Coverage technology
   SVA and PSL assertions
    —   Improved verification effectiveness
    —   Improved time to debug
            Identify failures as they occur
            ModelSim DE advanced assertion debugging
    —   Assertion browsing

   OVL assertion library ready

   Code Coverage
    —   Efficient coverage collection
            Unified Coverage Database (UCDB)
    —   Improve verification test productivity
            Ranking and Merging


                                   Mentor Graphics
                                   ModelSim DE 6.5
          Agenda

   Assertions

   Debug & Analysis

   Coverage




            Mentor Graphics
            ModelSim DE 6.5
Assertion Based Verification Improves
            Time-To-Bug
                                    Reference Model
                             Design Under Test




                              Lurking bugs:
             =              found late in the
                                                 =
                               design cycle

     ABV detects bugs at the source, saving valuable debug time
     ABV detects bugs missed by top-level test benches

                               Mentor Graphics
                               ModelSim DE 6.5
         What is an Assertion?

  A concise description of [un]desired behavior

                0    1   2      3      4   5
          req

          ack
                Example intended behavior



    “After the request signal is asserted, the
acknowledge signal must come 1 to 3 cycles later”



                         Mentor Graphics
                         ModelSim DE 6.5
                    Who Uses Assertions?
                                                     Functional spec says
     Hmm.. I assume the                              ACK will follow REQ
       CS inputs are                                   within 7-12 clock
     mutually exclusive                                     cycles

                                                      Spec. says that REQ
                                                      must not drop before
 Must remember…
                                                       ACK is received.
This is a 1-hot state
      machine

                                                  What I really need to
         Better warn others                     know is how many times
            about those                           a transfer DOESN‟T
         checksum gotchas                               complete




                              Mentor Graphics
                              ModelSim DE 6.5
                      Concise and Expressive
                              property req_ack;                      SystemVerilog
              SVA Assertion    @(posedge clk) $rose(req) |-> ##[1:3] $rose(ack);
                              endproperty
                              as_req_ack: assert property(req_ack);

                              always @(posedge req)                      Verilog
                                begin
                                   repeat (1) @(posedge clk);
      0   1   2   3   4   5        fork: pos_pos
                                      begin
req                                      @(posedge ack)
                                         $display("Assertion Success",$time);
                                          disable pos_pos;
ack                                   end
Example intended behavior            begin
                                        repeat (2) @(posedge clk);
                                        $display("Assertion Failure",$time);
                                        disable pos_pos;
                                     end
                                   join
                                end // always
              HDL Assertion

                                     Mentor Graphics
                                     ModelSim DE 6.5
ABV Improves Time-To-Coverage
                               Reference Model
                        Design Under Test




                                                            ?
     ABV reveals internal structural coverage
     ABV produces actionable metrics to improve coverage

                          Mentor Graphics
                          ModelSim DE 6.5
               Best Time To Bug Resolution
   Assertions identify failure closest to design failure
     —   Need ability to visualize the assertion
     —   Need ability for root cause analysis

   ModelSim DE has the best visualization and debug tools
     —   Language neutral debug suite
     —   Assertion Analysis
             Lists all assertions at current hierarchy
     —   Waveform Viewing
             S/W logic analyzer
             View assertion and it’s signals
             Clear indication of assertion status: active/inactive/pass/fail
     —   Assertion animation
             Decomposes assertion for best understanding
     —   Complete user interface tools for root cause analysis
             Source code and graphical dataflow


                                            Mentor Graphics
                                            ModelSim DE 6.5
          Viewing Assertions in the Wave
                                                                                     Green mid-line
                                                                                     indicates assertion is
                                                                                     active

                                                                                   Green triangle
                                                                                   indicates assertion
                                                                                   passed

                                                                                   Red inverted triangle
                                                                                   indicates assertion
                                                                                   failure




                                                                                     Blue low-line
                                                                                     indicates assertion
                                                                                     is inactive

Simply D&D Assertions from Assertion Browser into Wave Window to view assertions
Assertions can be expanded to view all signals associated with the assertion


                                             Mentor Graphics
                                             ModelSim DE 6.5
       View Multiple Assertion Threads
                                                        Blue box
                                                      above thread
                                                        indicates
                                                       start of new
                                                          thread
                                      RMC on start
                                      of thread box
                                      invokes ATV




 Automatic
Thread count
   integer


 Expand to
     see
 individual
   thread

                    Mentor Graphics
                    ModelSim DE 6.5
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ModelSim DE 6.5
Mentor Graphics
ModelSim DE 6.5
    Textual Dataflow: Tracing Signals


Find driver(s) of prdy_r




                     Select Signal
                     then RMB




                                     Mentor Graphics
                                     ModelSim DE 6.5
           Graphical Dataflow: Tracing Signals
       Find Cause of Unknown with ChaseX




   Users can also direct dataflow
    window to compute and draw paths
    between one point and another

                                 Mentor Graphics
                                 ModelSim DE 6.5
                Easing Causality Tracing
                Source Code Hyperlinking
                                           Enable source code
                                           hyperlinking




Hyperlinked variables




                         Mentor Graphics
           30            ModelSim DE 6.5
Easing Causality Tracing
Source Code Hyperlinking



   Jump to source window and
   highlight variable declaration


                             Jump through hierarchy




           Mentor Graphics
           ModelSim DE 6.5
Expanded Data requires Data Management
           Message Viewer
   Organize all simulation messages
   Sort by severity or type
   Cross links to other windows for quick isolation of
    problems




                          Mentor Graphics
                          ModelSim DE 6.5
          Agenda

   Assertions

   Debug & Analysis

   Coverage




            Mentor Graphics
            ModelSim DE 6.5
                                       Code Coverage
   Measures language coverage
     —   Have you executed each:
              Statement
              Branch
              Condition
              Expression
              Or Toggled each bit
   Best used at block level
     —   Easier to exercise code
         aspects
     —   Ensures blocks are tested &
         ready for integration
   Built-in
     —   Low overhead
     —   Easy to use
     —   High capacity and performance
         UCDB
   Improve verification throughput
     —   Rank UCDB test files and
         eliminate regression tests that do
         not contribute to coverage
         metrics
     —   Comprehensive coverage
         exclusion support




                                              Mentor Graphics
                                              ModelSim DE 6.5
           Unified Coverage DataBase (UCDB)
   Best capacity and
    performance                            ModelSim
   Most comprehensive
   Base technology for                                                                                Test
    Questa Verification                   Code   Functional Assertion    0-in      User      Test
                                                                                                       Plan
    Management                          Coverage Coverage    Engine     Formal   Coverage   Specific




                         Verification                                             3rd Party, Other
                          Coverage                                                Mentor Tools &
                         Analysis &                      UCDB                           User
                          Reporting                                                     Data


    Database Toolset, load, copy,
    merge, rank, report, analyze



                                                     Mentor Graphics
                                                     ModelSim DE 6.5
           Ranking Coverage Results

                           Per Instance or DU




                             Include Time based goals




   Merge and analyze regression suite results
   Identify highest yield coverage regression tests
    —   Eliminate non-contributing tests

                                Mentor Graphics
                                ModelSim DE 6.5
HTML Coverage Viewing



                       Specify design
                       Hierarchy



For details click on
specific Item




                       Mentor Graphics
                       ModelSim DE 6.5
Code Coverage Reporting Efficiencies
    Includes complete coverage result details
    Easy reporting to management




                   Coverage Totals




                   UCDB/Simulation
                   Details
                           Mentor Graphics
                           ModelSim DE 6.5
ModelSim DE 6.5 Functional Verification

    The best execution
     —   Integrated platform available today
    The best technology
     —   Improve verification effectiveness with assertions
    The right strategy
     —   Make every verification cycle count!




                            Mentor Graphics
                            ModelSim DE 6.5
Mentor Graphics
ModelSim DE 6.5
Additional Mentor Products




          Mentor Graphics
          ModelSim DE 6.5
       Processor-driven Verification

   Allows test efforts to span multiple stages of the design
    - test reuse across the project

Testbench-based
tests

Processor-
Driven C test
                  High-Level   RTL/Gate   Emulation   Prototype   Post-
                  Simulation   Simulation             or FPGAs    Fabrication



   Questa Codelink provides the critical features to
    support processor-driven, including multi-core
    verification

                               Mentor Graphics
                               ModelSim DE 6.5
Hardware/Software Correlation




            Mentor Graphics
            ModelSim DE 6.5
Multi-Core Processor Debug Environment




                Mentor Graphics
                ModelSim DE 6.5
Mentor‟s 0-In® Formal Verification Solution
                Delivers …
   Highest capacity and
    performance
   Extensive Design Style
    Support
   Smart integration of
    formal verification with
    simulation
   The largest library of assertion IP in the industry
   Intuitive graphical analysis and debug
   Questa Coverage database enabled
     The „proven‟ formal verification solution
                          Mentor Graphics
                          ModelSim DE 6.5
                  0-In® CDC Verificaton

   Structural CDC verification
    —   Automatically identifies all clocks and
        clock-domain crossings (CDCs)

   Verification of CDC protocols
    —   Automatically proves CDC Protocols
    —   Simulate CDC protocol assertions

   Silicon-accurate RTL simulation
    —   Mimics the metastability effects in
        synchronizers

   Accurate Coverage metrics
    —   Provides a measure of completeness for
        the testbench as related to metastability
        issues


0-In® CDC – The Benchmark in CDC verification
                                  Mentor Graphics
                                  ModelSim DE 6.5
Mentor Graphics
ModelSim DE 6.5

				
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posted:11/19/2011
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