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					Computer Systems and Architecture
Solutions to sample examination paper 1)Explain the primary functions of the following components found in the MIPS datapath: i)Registers ii)Multiplexer iii)Sign-extend Unit iv)Program Counter v)Instruction Register Solution: Registers provide temporary storage for data that is being used currently by the CPU, or is frequently used by the CPU [4%] Multiplexers allow data to be routed to/from different CPU components. [3%] Sign-extend unit converts a 16-bit offset address into a full 32-bit physical address. [3%] Program counter stores the address of the next instruction to be executed. [3%] Instruction register holds the instruction currently being executed. [3%] 2)Translate the following code fragments into MIPS assembly language. Assume that all variables are initially in memory, and can be loaded/stored by reference (i.e. “lw $r1, &x” loads variable x into register r1). Also assume that all results must be stored in memory. You may assume that registers r1r7 are available for general use.[You may refer to the table of MIPS instructions provided.] i)a = (b * c) + d; ii)a = (b/c)-(d/e); iii)a=0; for(i=1; i<5; i++) { a = a + i; } a = a*a; Solution: [note: there are other possibilities] i) lw $r1, &b lw $r2, &c mult $r1, $r1, $r2 lw $r2, &d add $r1, $r1, $r2 sw $r1, &a [5%] [7%] [3%] [3%] [3%] [3%] [4%]

[10%]

// Load b into r1 // Load c into r2 // r1 contains b*c // Load d into r2 // r1 contains b*c+d // Store r1 as a

ii)

lw $r1, &b lw $r2, &c div $r1, $r1, $r2 lw $r2, &d lw $r3, &e div $r2, $r2, $r3 sub $r1, $r1, $r2 sw $r1, &a addi $r1, $r0, 0 addi $r2, $r0, 1 LOOP:subi $r3, $r2, 5 bgez $r3, NEXT add $r1, $r1, $r2 addi $r2, $r2, 1 j LOOP NEXT:mult $r1, $r1, $r1 sw $r1, &a memory

// Load b into r1 // Load c into r2 // r1 contains b/c // Load d into r2 // Load e into r3 // r2 contains d/e // r1 contain (b/c)-(d/e) // Store r1 as a // Set a=0 in r1 // Initialise i in r2 // r3 contains i-5 // i-5>=0 quit loop // a=a+i // Increment i in r2 // Return to start // a=a*a // Store a in

iii)

3)Describe the memory organisation of the MIPS processor. Explain the function of each region of memory. [15%] Solution: At the bottom of the memory map is the code memory, where program instructions are stored. There is a protected region of code memory at the very bottom that is used to store critical OS code. The region is of fixed size. Above code memory is the data memory, which store global program data. Allocation of data memory to variables is static. Next is the heap, which is of variable size and grows upwards. It is used for dynamically allocated data and grows and shrinks as required. Finally there is the stack, which sits at the very top of the memory map and grows downwards. It is used for temporary storage of data. 4)Explain the basic principles and advantages/disadvantages of interruptbased I/O. [15%] Solution: In interrupt-based I/O, each peripheral device is allocated an interrupt request channel through which it can inform the CPU that it requires attention. When the CPU is available, it can access the device and take appropriate action. This will usually involve a call to a special interrupt-handling subroutine. The advantage of this is that the CPU does not have to keep polling external devices to find out when they require attention The disadvantage is that the CPU still has to execute the interrupt handling subroutine. In some cases, this could be rather long (for example, copying a DVD), and so the CPU can use

many cycles performing routine data transfer operations. DMA, which is designed to handle such transfers is a solution to this problem. 5)Explain the functions of the four layers in the TCP/IP network architecture. [12%] Solution: The application layer provides services that are used directly by the application software, such as HTTP, FTP, SMTP The Transport layer provides services required by the protocols of the application layer, such as UDP (used for high-speed transaction) and TCP (which is reliable and has error-correction). The transport services perform the packet segmentation of the data. The Internet layer adds addressing information to each packet (IP is connectionless) and prepares the packets for transport. The Network Interface layer handles technology-dependent aspects of the transfer by wrapping IP packets in network-specific wrappers for transmission onto the local network. 6)Draw a diagram that shows how to construct a simple ALU that supports and, or, add, xor instructions. Explain how to configure the ALU for each instruction. [20%] Solution:
A[0] B[0] A[1] B[1] A[31] B[31]

A

B

A

B

A

B

Halfadder
Cin Cout Cin

Fulladder
Cout Cin

Fulladder
Cout

Q

Q

Q

C[0] 0 MUX 1 0 MUX 1 0 MUX 1 0 MUX 1 0 MUX 1 0 MUX 1

0 C[1]

MUX

1

0

MUX

1

0

MUX

1

Q[0]

Q[1]

Q[31]

OVERFLOW

For “or”: set c0=0, c1=0 For “and”: set c0=1, c1=0 For “add”: set c0=0, c1=1 For “xor”: set c0=1, c1=1


				
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