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					Computer Systems and Architecture
Sample exam paper Answer All Questions Time allowed: 1 hour 30 Minutes 1)Explain the primary functions of the following components found in the MIPS datapth: i)Registers ii)Multiplexer iii)Sign-extend Unit iv)Program Counter v)Instruction Register [3%] [3%] [3%] [3%] [4%]

2)Translate the following code fragments into MIPS assembly language. Assume that all variables are initially in memory, and can be loaded/stored by reference (i.e. “lw $r1, &x” loads variable x into register r1). Also assume that all results must be stored in memory. You may assume that registers r1r7 are available for general use.[You may refer to the table of MIPS instructions provided.] i)a = (b * c) + d; ii)a = (b/c)-(d/e); [5%] [7%]

iii)a=0; for(i=1; i<5; i++) { a = a + i; } a = a*a; [10%] 3)Describe the memory organisation of the MIPS processor. Explain the function of each region of memory. [15%] 4)Explain the basic principles and advantages/disadvantages of interruptbased I/O [15%] 5)Explain the functions of the four layers in the TCP/IP network architecture. [12%] 6)Draw a diagram that shows how to construct a simple ALU that supports and, or, add, xor instructions. Explain how to configure the ALU for each instruction. [20%]

Subset of the MIPS Instruction Set
Load/Store Instructions Load word Store word Load upper immediate Arithmetic Instructions Add Subtract Add immediate Add unsigned Subtract unsigned Add immediate unsigned Multiply/Divide Multiply Instructions Multiply unsigned Divide Divide unsigned Logical Instructions AND OR NOR AND immediate OR immediate XOR immediate Shift left logical Shift right logical Conditional Branch Instructions Branch on equal Branch on not equal Branch on < 0 Branch on <= 0 Branch on > 0 Branch on >= 0 Branch on < 0 and link Branch on >= 0 and link Set on less than Set less than immediate Set less than unsigned Set less than immediate unsigned Conditional Jump instructions Jump Jump to register Jump and link lw $r1 , &a sw $r1 , &a lui $r1 , 100 add $r1,$r2,$r3 sub $r1,$r2,$r3 addi $r1,$r2,100 addu $r1,$r2,$r3 subi $r1,$r2,$r3 addi $r1,$r2,100 mult $r1,$r2,$r3 mult $r1,$r2,$r3 div $r1,$r2,$r3 divu $r1,$r2,$r3 and $r1,$r2,$r3 or $r1,$r2,$r3 nor $r1,$r2,$r3 and $r1,$r2,100 or $r1,$r2,100 xor $r1,$r2,100 sll $r1,$r2,10 srl $r1,$r2,10 beq $r1,$r2,100 bne $r1,$r2,100 bltz $r1, 100 blez $r1, 100 bgtz $r1, 100 bgez $r1, 100 bltzal $r1, 100 bgezal $r1, 100 slt $r1,$r2,$r3 slti $r1,$r2,100 sltu $r1,$r2,$r3 sltiu $r1,$r2,100 j 10000 jr $r31 jal 10000 Load the contents of address &a into register r1 Stores the contents of register r1 into address &a Loads the value “100” into the upper 16 bits of $r1 ($r1 = 100*10^16) r1 = r2 + r3 r1 = r2 - r3 r1 = r2 + 100 r1 = r2 + r3 r1 = r2 - r3 r1 = r2 + 100 r1 = r2 x r3 r1 = r2 x r3 r1 = r2 / r3 r1 = r2 / r3 r1 = r2 & r3 r1 = r2 | r3 r1 = !(r2 | r3) r1 = r2 & 100 r1 = r2 | 100 r1 = r2 ^ 100 r1 = r2 << 10 r1 = r2 >> 10 if (r1 == r2) PC = PC+4+100 if (r1 != r2) PC = PC+4+100 If (r1 < 0) PC = PC+4+100 If (r1 <= 0) PC = PC+4+100 If (r1 > 0) PC = PC+4+100 If (r1 >= 0) PC = PC+4+100 If (r1 < 0) r31 = PC; PC = PC+4+100 If (r1 >= 0) r31 = PC; PC = PC+4+100 if (r2 < r3) r1 = 1; else r1 = 0 if (r2 < 100) r1 = 1; else r1 = 0 if ($r2 < $r3) $r1 = 1; else $r1 = 0 if (r2 < 100) r1 = 1; else r1 = 0 PC = 10000 PC = $r31 r31 = PC + 4; PC = 10000


				
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