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Custom Integrated Circuits Conference San Diego Calif Powered By Docstoc
					Proceedings                 of the
IEEE       1989
CUSTOM INTEGRATED CIRCUITS
CONFERENCE




Town &      Country Hotel                                     May 15-18,1989
San     Diego, California




The CICC '89 is   sponsored by   the IEEE Electron Devices   Society, the IEEE Solid-State Circuits
Council, and co-sponsored by   the IEEE Rochester Section. Its aim is to
                                                                      bring together designers,
producers and users of custom     ICs to discuss recent   developments and future directions in
custom integrated circuits.




                                                                                    89CH2671-6
CONTENTS

MONDAY EVENING                                                         California                       Session 1

  7:00   NEW PRODUCTS—NEW METHODS I
         H.   Scalf, General Chairman

                                             —,            _


                                                                           ^

MONDAY EVENING                                                       Golden West                        Session 2

  7:00   NEW PRODUCTS—NEW METHODS II
         A.   Silzars, General Chairman




TUESDAY MORNING                                                            Presidio                     Session 3      PAPER

  8:00   WELCOME/OPENING REMARKS
         R. Milano, General Chairman
         M. Hartranft, Conference Chairman

  8:20   CICC '89—Technical          Program
         D. Brown, Technical Program Committee Chairman

  8:30   KEYNOTE ADDRESS
         "Design   Automation for Analog and Mixed      Analog/Digital     ICs"
         J. Solomon
         Co-Chairman of Cadence Design Systems, Inc.

         FLOORPLANNING AND ROUTING
         Chairman: J. Lipman
         Co-Chairman: S. Stevens
  9:15   A    Special Purpose Coprocessor Supporting                 Cell Placement and     Floorplanning Algorithms   3.1
         R-M. Kling, P.   Banerjee, University   of Illinois, Urbana, IL

  9:40   A New Floorplanning Algorithm for Analog Circuits                                                             3.2
         C.K. Kim, E. Berkcan, B. Currin, M. d'Abreu, General Electric Co.,       Schenectady,   NY

 10:05   A Hierarchical      Floor-Planning, Placement, and Routing Tool for Sea-of-Gates Designs                      3.3

         C. Ng, S. Ashtaputre, E. Chambers, K-H. Do, S-T. Hui, R. Mody,
                                                                  D. Wong, VLSI Technology, Inc., San Jose, CA

 10:30   An Interior Point Method For        Solving The Global Routing               Problem                          3.4
         A. Vannelli,   University of Waterloo, Waterloo, Ont., Canada
 10:55   A Gate Matrix Deformation and 3-Dimensional Maze Routing for Dense MOS Module Generation                      3.5
         Y. Sone, S. Suzuki, K. Asada, University of Tokyo,      Tokyo, Japan
 11:20   An Efficient Layer      Assignment Algorithm for Gridless Switchbox Routing                                   3.6

         A. Pitak, C. Lursinsap,  University of Southwestern Louisiana, Lafayette, LA
CONTENTS

TUESDAY MORNING                                                       Friars/Padre/Sierra                            Session 4         PAPER

         ANALOG AND DIGITAL DESIGN SYNTHESIS
         Chairman: M.Mittal
         Co-Chairman: R.        Bryant

  9:15   LOGOPT—A Multi-Level Logic Synthesis and Optimization System                                                                  4.1
         A.M.   Prabhu, AT&T Bell        Labs.   Murray Hill, NJ
  9:40   CHARM: A Synthesis Tool for High-Level Chip-Architecture                             Planning                                 4.2
         K-H. Temme,        University   of Dortmund,      Dortmund, W. Germany
 10:05   ACACIA: The CMU Analog Design System                                                                                          4.3

         L.R. Carley, D. Garrod,      R.   Harjani, J. Kelly, T. Lim,   E. Ochotta, R.A. Rutenbar,   Carnegie   Mellon   University,
         Pittsburgh, PA
 10:30   From     Analog Design Description                 to   Layout: A New Approach        to   Analog Sililcon Compilation        4.4

         E. Berkcan, C.K. Kim, B. Currin, M. d' Abreu, General Electric Co., Schenectady, NY

 10:55   An     Integrated Switched Capacitor Filter Design System                                                                     4.5
         A. Barlow, K. Takasuka, Y. Nambu, T. Adachi, J. Konno, Asahi Kasei Microsystems, Tokyo,                   Japan
 11:20   LATE NEWS PAPER
         Design Automation System for Analog Circuits Based                            on   Fuzzy Logic                                4.6

         M. Hashizume, H.Y. Kawai,           K. Nii, T.   Tamesada,   University of Tokushima, Tokushima-shi, Japan




TUESDAY MORNING                                                            Golden West                               Session 5         PAPER


         PROGRAMMABLE DEVICES
         Chairman: G. Ledenbach
         Co-Chairman: S. Chiao


  9:15   A 6 Nanosecond CMOS EPLD With uW                          Standby Power                                                       5.1

         M.J. Allen, Intel    Corp., Folsom,      CA

  9:40   A Function Specific EPLD for the PS/2 Micro Channel Bus                            Adapter                                    5.2

         Y-F. Chan, C-Y. Hung, C. Hsiao, P. Wong, N. Lee, C. McClintock, Altera Corp., Santa Clara, CA

 10:05   The Effect of        Logic   Block      Complexity on Area of Programmable Gate Arrays                                        5.3
         J.Rose*, R.J. Francis**, P. Chow**,         D. Lewis**, Stanford University, Stanford, CA*; University of Toronto,

         Toronto, Ont., Canada**
 10:30   Electrical and Geometrical Circuit Performance                        Using   an Advanced      Sea-of-Gates Philosophy        5.4
         P.Duchene*, H. Heeb**, A. Osseiran*, M. Declercq*, W. Fichtner**, Swiss Federal Institute of Technology,
         Lausanne, Switzerland*, Swiss Federal Institute of Technology, Zurich, Switzerland**
 10:55   A12ns, CMOS Programmable Logic Device for Combinatorial Applications                                                          5.5
         S.P. Gowni*, P.E. Piatt*, A.L. Hawkins*, W.R. Hiltpold*, S.M. Douglass**, Cypress Semiconductor Corp.,
         Starkville, MS*; Cypress Semiconductor Corp., San Jose, CA**
 11:20   A 7.5 ns 350mW BiCMOS P AL®-type Device                                                                                       5.6
         R.   Leung,   K.   Le, C. Sung, Y-M. Chu, G. Conner, R. Lane, J.L. deJong, SigneticsCo., Sunnyvale,              CA

 11:45   LATE NEWS PAPER
         A 15ns 2500 Gate          Highly Flexible          CHMOS EPLD                                                                 5.7
         R.W.    Swartz, M.J. Allen, Intel Corp., Folsom, CA
 12:00   LATE NEWS PAPER
         A 5000-Gate CMOS EPLD With                       Multiple Logic    and Interconnect        Arrays                             5.8

         S.C. Wong, H.C. So, J.H. Ou, J. Costello, Altera Corp., Santa Clara, CA
CONTENTS

TUESDAY MORNING                                                         California                                Session 6               PAPER


         DATA CONVERTERS
         Chairman: J. Tandon
         Co-Chairman: L. D'Luna


  9:15   A16-Bit 160 kHz CMOS A/D Converter                  Using Sigma-Delta Modulation
         M. Rebeschini*, N. van Bavel**, P. Rakers*, R. Greene*, J. Caldwell*, J. Haug*, MotorolaCorp.              Res.   Design Labs,
         Schaumburg, IL*; Motorola Telecom Design, Austin, TX**
  9:40   An 11 Bit, 50     kSample/s CMOS A/D Converter Cell Using a Multislope Integration Technique
         J-G. Chern, A.A. Abidi,    University of California,   Los Angeles, CA

 10:05   An 8-Bit Two-Step Flash A/D Converter for Video Applications
         A. Cremonesi*, F. Maloberti**, G. Torelli**, C. Vacchi**, ST Microelectronics        Agrate Brianza, Milano, Italy*;
         University Pavia, Pavia, Italy**
 10:30   A12Bit5 Msec CMOS Recursive ADC with 25mW Power                               Consumption
         M.   Yotsuyanagi, A. Yukawa,     K.   Hino-oka, K. Shiraki, H. Abiko,   NEC   Corp., Kanagawa, Japan
 10:55   CMOS Low Distortion           Sample & Hold Circuit for Audio D/A Converter
         N. Sugawa, T. Ikarashi, K. Kuwana, T. Kawakami, A. Kimitsuka,            T. lida, Toshiba Microelectronics Corp.,
         Kawasaki, Japan
 11:20   A Complete Single         Supply CMOS 12 Bit DAC
         S. Hisano, M.P. Timko, Analog Devices, Wilmington, MA
 11:45   LATE NEWS PAPER
         A10-Bit    High Speed CMOS DAC Macrocell
         A.W.   Vogt,   I.J. Dedic, Advanced Microelectronic     Systems, Wembley, U.K.




TUESDAY AFTERNOON                                                        Presidio                                 Session 7               PAPER


         MIXED ANALOG/DIGITAL APPLICATIONS I
         Chairman: D.A. Wayne
         Co-Chairman: A. Grebene

         A 30 MHz Low-Noise CMOS                                           Drive Heads                                                    7.1
  1:30                                           Preamplifier for Disk
         T-W. Pan, A.A. Abidi, University of California, Los      Angeles,   CA

  1:55   A Differential PLL Architecture for High Speed Data                     Recovery                                                 7.2
         R.S. Co., J.C.   Liang, K.W. Ouyang, Western Digital Corp., Irvine, CA
  2:20   A    High-Performance Perpendicular FDC Using Analog and Digital Standard Cell Methodology                                       7.3
         K. Matsuo*, S. Fujii*, K. Kasai", I. Tsuchiya**, T. Sasaki*, K. Toda*, T. Yoshizuka*,          K. Suzuki*, M. Kamata*,
         M. Kaizuka*, Toshiba Corp., Kawasaki, Japan*; Toshiba Microcomputer Eng. Corp., Kawasaki,                   Japan**
  2:45   CMOS Analog Front-End for Conversational Video Phone Modem                                                                       7.4
         C.W. Solomon*, L. Ozcolak*, G.         Sellani*, W.E. Brisco**, EXAR Corp., San Jose, CA*; LumaTelecom, Inc.,
         Sunnyvale, CA**
                                                                                                                                          7.5
  3:10   A Precision       Optical Metering System for Medical Instrumentation
         W.R, Krenik*. D. Gonzalez*, E.G. Dierschke*, L.J. Izzi*, B. Carter*, J.        White**,   R. Miller**, Texas Instruments Inc.,

         Dallas, TX*; Miles, Inc., Mishawaka, IN**
  3:35    A Four Chip Implantable Defibrillator/Pacemaker Chipset                                                                         7.6

         J.G. Ryan, K.J. Carroll, B.D. Pless, Ventritex, Inc.,     Sunnyvale,     CA

          A Novel BiMOS Switch for Use in                                                                                                 7.7
  4:00                                                 Switched-Capacitor Filters
                                                                                                    Canada
          I. Abu-Khater, E.I.   El-Masry, Technical University of Nova Scotia, Halifax, N.S.,
CONTENTS

TUESDAY ARTERNOON                                                 Friars/Padre/Sierra                          Session 8                PAPER


         HIGH DENSITY/PERFORMANCE GATE ARRAYS
         Chairman: R. Blake
         Co-Chairman: G. Sporzynski

  1:30   A177K Gate 150 PS CMOS SOG with 1856 I/O Buffers                                                                               8.1
         M.Murayama, Y. Matsuda, K. Yoshida,           H. Ooka, T. Otani, S.   Toyoda,   F. Tsubokura, A. Aso, NEC   Corp.,
         Kanagawa, Japan
  1:55   0.8 urn 1.4MTr. CMOS SOG Based on Column Macro-Cell                                                                            8.2
         Y. Okuno, M. Okabe, T. Arakawa, I. Tomioka, T. Ohno, T. Noda, Y. Kuramitsu, Mitsubishi Electric             Corp., Hyogo,
         Japan
  2:20   BiNMOS: A Basic Cell for BiCMOS Sea-of-Gates                                                                                   8.3
         A. El Gamal, J.L. Kouloheris, D. How, M. Morf, Stanford University, Stanford, CA

  2:45   A 270 ps 24.000 Gate BiCMOS Gate Array                                                                                         8.4
         A. Denda, K. Yamada, T. Hatano, H. Okamura, N. Aoki, M. Iruka, N. Kusunose, H.             Ogawa, S. Saigo, NEC Corp.,
         Kawasaki, Japan
  3:10   A350ps50K0.8 /xm BiCMOS Gate Array With Shared Bipolar Cell Structure                                                          8.5
         H. Hara, Y. Sugimoto, M. Noda, T. Nagamatsu, Y. Watanabe, H. Iwai, Y. Niitsu, G. Sasaki, K. Maeguchi, Toshiba
         Corp., Kawasaki, Japan
  3:35   A100K Gate Sub-Micron BiCMOS Gate                      Array                                                                   8.6
         J.Gallia, A. Yee, l-F. Wang, K. Chau, H. Davis, S. Swamy, T. Sridhar, V. Nguyen, K. Ruparel, K. Moore,
         C. Lemonds, B. Chae, P. Eyres, T. Yoshino, J. Pozadzides, R. Fine, A. Shah, Texas Instruments, Dallas,               TX

  4:00   A 0.5 jum BiCMOS Channelless Gate           Array                                                                              8.7
         F.Murabayashi*, Y. Nishio*, H. Maejima*, A. Watanabe*, S. Shukuri**, T. Nishida**, K. Shimohigashi**,                Hitachi
         Research Lab, Ibaraki-ken, Japan*; Hitachi Central Research Lab, Tokyo, Japan**




TUESDAY AFTERNOON                                                       Golden West                            Session 9                PAPER


         DEVICE        MODELING
         Chairman: R.Milano
         Co-Chairman: H. Scalf


  1:30   Physics-Based Bipolar Transistor Model for Low-Temperature Circuit Simulation                                                  9.1
         J.J. Liou*, J.S. Yuan**,     University of Central Florida, Orlando, FL*; University of Florida, Gainesville,   FL**

  1:55   Steady-State Bipolar Transistor Simulator for the 77° K—300° K Temperature                           Range                     9.2
         M. Chrzanowska-Jeske, R.C.          Jaeger,   Auburn   University, Auburn, AL
  2:20   A Simplified Approach for Quasi-Three-Dimensional                        Modeling npn Transistors                              9.3
         P.M. Zeitzoff, AT&T Bell Labs, Allentown, PA

  2:45   A    Technology-Independent Device Modeling Program Using Simulated Annealing Optimization                                     9.4
         M-K.   Vai,   M.F.D.   Ng, Northeastern University, Boston,    MA

  3:10   An    Improved l-V Model of Small Geometry MOSFETs for SPICE                                                                   9.5
         S.C.   Chung, T.S. Lin, Y.G. Chen, National ChiaoTung University, Taiwan, R.O.C.
  3:35   A Three-Transistor Model for Submicron MOSFET                                                                                  9.6
         S.C.   Wong,    H.C. Lin,   University of Maryland, College Park,   MD

  4:00   Simulating the Effects of Single-Event and Radiation Phenomena on GaAs MESFET Integrated                                       9.7
         Circuits
         P.   George,   P-K. Ko, C. Hu,   University of California, Berkeley,   CA
CONTENTS
TUESDAY AFTERNOON                                                          California                               Session 10            PAPER


         COMPUTER ELEMENTS
         Chairman: A. Goodman
         Co-Chairman: M. Horowitz


  1:30   A High     Density N AND EEPROM with Block-Page Programming for Microcomputer Applications                                       10.1
         M.   Momodomi,      Y. Iwata, T. Tanaka, Y. Itoh, R. Shirota, F. Masuoka, Toshiba         Corp., Kawasaki, Japan
  1:55   A 2Kbyte      Fully-Associative Cache Memory With On-Chip DRAM Control                                                           10.2
         S.   Golson*, S. Griffith**, Trilobyte Systems, Carlisle, MA*; Sun Microsystems, Billerica,         MA**

  2:20   A15 ns 32 x 32-Bit CMOS Multiplier With                 an   Improved Parallel Structure                                         10.3
         M.   Nagamatsu, S. Tanaka, J. Mori, T. Noguchi,        K. Hatanaka, Toshiba     Corp., Kawasaki, Japan
  2:45   A 3.8ns CMOS 16x16             Multiplier Using Complimentary Pass Transistor Logic                                              10.4
         K.   Yano, T. Yamanaka, T. Nishida, M. Saitoh, K. Shimohigashi, A. Shimizu, Hitachi Central Research Lab, Tokyo,
         Japan
  3:10   A Custom Processor for Use in a Parallel                 Computer System                                                         10.5
         D.K.   Wilde, NCUBE Corp., Beaverton, OR
  3:35   A 140Mb/s CMOS Crosspoint Chip for Switching Networks With Dynamic Path-Rearrangement                                            10.6
                                   Schmidt**, Fraunhofer Institute of Microelectronic Circuits & Systems, Duisburg, W.
         K.G. Hess*, G. Kettler**, W.
         Germany*, Forschungsinstitut der Deut. Bunde. beim Femmelde. Zent, Darmstadt, W. Germany**
  4:00   An ECL Compatible Full CMOS                210Mbps Crosspoint Switch                                                             10.7
         T. Yoneda, M. Komaki, S.      Sugatani,   Y. Ezaki,   Fujitsu   VLSI Ltd., Aichi, Japan

  4:25   LATE NEWS PAPER
         A BiCMOS 32-Bit Execution Unit for 70MHz VLSI Computer                                                                           10.8
         S. Tanaka*, T. Hotta*. M. Iwamura*, T. Yamauchi*, T. Bandoh*, A. Hotta**, T. Nakano**, S. Iwamoto***,
         S. Adachi***, Hitachi, Ibaraki-ken, Japan*, Hitachi, Tokyo, Japan**, Hitachi, Aichi-ken, Japan***




WEDNESDAY MORNING                                                        Regency Hall                               Session 11            PAPER


         MIXED ANALOG/DIGITAL APPLICATIONS II
         Chairman: J. Buurma
         Co-Chairman: K.Au


  8:30   CMOS High         Speed Digital Datastrobe Processor                                                                             11-1
         T. Komatsu*, K. Watanabe*, E. Minamimura*, Y. Kowase*, S. Ueda*, N. Horie*, S.                 Asai**, T. Matsuura**, Hitachi
         Ltd., Gunman, Japan*; Hitachi Ltd., Tokyo, Japan**
  8:55   Design of an Analog 8-Bit 2 Channel I/O ASIC for Disk Drive Control Applications                                                 11.2

         P. Quinlan, Analog      Devices, B.V., Limerick, Ireland
  9:20   A16 MBPS Adapter            Chip for the IBM Token-Ring              Local Area Network                                          11.3
         J.D. Blair, A. Correale, Jr., H.C. Cranford, D.A. Dombrowski, C.K. Erdelyi, C.R. Hoffman, J.L. Lamphere, K.W.
         Lang, J.K. Lee, J.M. Mullen, V.R. Norman, S.F. Oakland, IBM Corp., Research Triangle Park, NC
  9:45   An    Intelligent Multiplexer/Driver Integrated Circuit for an Implantable Multichannel Blood                                    11.4
         Flowmeter
         K-W.W.     Yeung,   J.D. Meindl, Stanford   University, Stanford,     CA

 10:10   A CMOS Camera Control IC                                                                                                         11.5
         I.Muenster*, B.J. Hosticka*, T. Neumann*, G. Zimmer*, W. Bletz**, R. Magel**, Fraunhofer Inst, of              Microelectronic
         Circuits & Systems, Duisburg, W. Germany*; Leica GmbH, Solms bei Wetzlar, W. Germany**

                                                                                                                                          11.6
 10:35   An    Integrated Digital Y/C Separator for S-VHSVCR's
         H.Owashi*. K. Minabe*, H. Otsubo*, T. Kuroyanagi*, S. Ueda**, H. Torii***, Hitachi Cons. Prod. Res.                Ctr.,
         Yokohama, Japan*; Hitachi Takasaki Works**; Hitachi Tokai Works***
 11:00   LATE NEWS PAPER
                                                                                                                                          11.7
         A CMOS 100MHz            Digital Oscilloscope Point Processor and Time                     Base   Integrated Circuit
         E.   Etheridge,   Tektronix, Inc., Beaverton, OR
CONTENTS

WEDNESDAY MORNING                                                     Friars/Padre/Sierra                               Session 12           PAPER


         HIGHLY PARALLEL ARCHITECTURES AND NEURAL NETS
         Chairman: P.      Ivey
         Co-Chairman: D. Brown


  8:30   BLITZEN: A VLSI Array              Processing Chip                                                                                  12.1
         R.A. Heaton, D.W. Blevins, Microelectronics Center of North Carolina, Research                    Triangle Park,   NC

  8:55   A Four-Processor Building Block for SIMO Processor Arrays                                                                           12.2
         A.L. Fisher, P.T.   Highnam.T.E. Rockoff, Carnegie Mellon University, Pittsburgh, PA
  9:20   A    High Speed Data Encryption Processor for Public Key Cryptography                                                               12.3
         T.   Rosati, Calmos Systems, Inc., Kanata, Ont., Canada
  9:45   A VLSI     Fuzzy Logic Inference Engine for Real-Time Process Control                                                               12.4
         W.D. Dettloff*, K.E. Younf, H. Watanabe**, Microelectronics Center of North Carolina, Research Triangle Park,
         NC*; University of North Carolina, Chapel Hill, NC**
 10:10   A    Bit-Serial   VLSI    Receptive Field Accumulator                                                                               12.5
         K. Strohbehn*,A.G.        Andreou", The Johns Hopkins University, Laurel, MD*; The                Johns   Hopkins University,
         Baltimore, MD**
 10:35   A Synthetic Neural          Integrated Circuit                                                                                      12.6
         L.A. Akers, M,    Walker,   R. Grondin, D. Ferry, Arizona State       University, Tempe,       AZ

 11:00   Fully Digital Neural Network Implementation                      Based    on   Pulse   Density Modulation                           12.7
         J.   Tomberg, T. Ritoniemi,      K. Kaski, H. Tenhunen, Tampere University of Technology,        Tampere, Finland



WEDNESDAY MORNING                                                         Golden West                                   Session 13           PAPER


         SIMULATION I
         Chairman: V.B.Rao
         Co-Chairman: D. Johnson

  8:30   iSPLICE3: A New Simulator for Mixed                     Analog/Digital VLSI Circuits                                                13.1
         E. Acuna, J.    Dervenis,   A.   Pagones,   R.   Saleh, University of Illinois, Urbana,   IL

  8:55   A New Multi-Level Timing Simulation Environment for Timing Verification                                                             13.2
         J. Benkoski, M.    Chew,    A.   Strojwas, Carnegie Mellon University, Pittsburg,         PA

  9:20   Hierarchical Timing View Generation                    Including Accurate Modeling for False Paths                                  13.3
         P. Das*, P.Johannes*, L Claesen*, H. DeMan**,                IMEC, Leuven, Belgium*;      Kath.     University of Leuven, Leuven,
         Belgium**
  9:45   An Analytical Model for BiCMOS                    Logic Transient Resopnse Allowing Parameter Variations                            13.4
         P.L.   Heedley,   R.C.   Jaeger, Auburn University, AL
 10:10   Analysis of Pulse Propagation                on    High-Speed VLSI Chips                                                            13.5
         M.    Nakhla, Carleton Universtiy, Ottawa, Ont.,         Canada

 10:35   An     Approach to Understanding Evaluation of Simulation Results                              as an   Integrated Task              13.6
         R.   Buschke,K. Lagemann, University Hamburg, Hamburg, W. Germany
CONTENTS
WEDNESDAY MORNING                                                        California                                    Session 14               PAPER


         PACKAGING AND INTERFACES
         Chairman: W.A. Vincent
         Co-Chairman: M.G. Moon


  8:30   Single Package 32Bit Floating Point Digital Signal Processor with Built-in 64K Byte SRAM Cache                                         14.1


         C    WKM1JJ*«QG1PPPJ#tlett, J.M. Segelken, AT&T Bell Labs, Murray Hill, NJ
  8:55   Packaging Structures Utilizing             New "Pinless" Grid           Array Technologies and Vacuum Well                             14.2
         Processes to Provide Enhanced Reliability and Circuit Densities
         P.   Nunally,   General   Dynamics Corp., Pomona, CA
  9:20   VLSI Performance            Compensation for Off-Chip Drivers and                    Clock Generation                                  14.3
         D.T. Cox*, D.L. Guertin*, C.L. Johnson*, R.A. Piro**, B.G. Rudolph*, D.W. Stout**, R.R. Williams*, IBM Application
         Business, Systems Div., Rochester, MN*; IBM Corp., Essex Junction, VT**
  9:45   Low dl/dt Noise and Reflection Free CMOS                   Signal      Driver                                                          14.4
         M. Hashimoto, O-K. Kwon, Texas Instruments Inc., Dallas, TX

 10:10   A Monolithic 50—200 MHz CMOS Clock Recovery and Retiming Circuit                                                                       14.5
         R.J.   Baumert, P.C. Metz, M.E. Pedersen, R.L. Pritchett, J.A. Young, AT&T Bell Labs, Allentown, PA
 10:35   High Voltage CMOS LCD Driver Using Low Voltage CMOS                                  Process                                           14.6
         J. Haas*, K. Au*, L. Martin*, T.L. Portlock*, T. Sakurai**, Motorola, Inc., Austin, TX*; Motorola Nippon Ltd.,               Tokyo,
         Japan**
 11:00   4.0Gb/sNMOS Laser Driver                                                                                                               14.7
         K.R. Shastri, K.A. Yanushefski, J.L. Hokanson, M.J. Yanushefski, AT&T Bell Labs, Allentown, PA

 11:25   LATE NEWS PAPER
         4Gb/s ECL Gate Mastersiice                                                                                                             14.8
         M. Tamamura, S. Emori, Y. Watanabe, I. Shimotuhama, N. Kikuchi, W. Ishibashi, K. Tachibana, Fujitsu Ltd.,
         Kawasaki .Japan
                                                                          ^


WEDNESDAY AFTERNOON                                                       Regency                                      Session 15               PAPER


         DIGITAL ASICs
         Chairman: D.Perkins
         Co-Chairman:       D.Daly

  2:00   Design of a Digital Audio Input Output Chip                                                                                            15.1
         M.M. Ligtharf,  Bechtolsheim**, G. DeMicheli***, A. El Gamal***, Philips Research Lab., Sunnyvale, CA*;
                            A.

         Sun Microsystems, Mountain View, CA**; Stanford University, Stanford, CA***

  2:25   VLSI Architecture for IEEE802.5             Token-Ring LAN Controller                                                                  15.2
         K. Tanaka*, K. Fujimoto*, E. Katsumata*,        T.
                                                     Yaguchi*, K. Tamaru*,  Kanuma*, S. lida**,
                                                                                         A.                       A.   Nishikawa**,
         H. Shiraishi**, T. Mineoka***, T. Shimamura***, Toshiba Semiconductor Device Eng. Lab.,
                                                                                            Kawasaki, Japan*;
         Toshiba Semiconductor System Eng. Center, Kawasaki, Japan**; Toshiba Microcomputer Engineering Co.,
         Kawasaki, Japan***
  2:50   Mixed                                     the Semicustom CMOS Gate Forest                                                              15.3
                   Design Approaches on
         J. Kernhof, M. Schau, M. Beunder, W. Haas, B.           Hoefflinger,   Institute for Microelectronics,   Stuttgart, W. Germany
  3:15           Performance Clock Distribution for CMOS ASICs                                                                                  15.4
         High
         S. Boon*, S. Butler*, R. Byrne*, B. Setering*, M. Casalanda**, A. Scherf**, VTC                Incorporated, Bloomington, MN*;
         Control Data Corp., Bloomington, IN**
         Q20D080 Analog RAM                                                                                                                     15.5
  3:40                                   Logic Array
         C. Blake, M. Hollabaugh,      Applied   Micro Circuits Corp., San      Diego,   CA

         0.6 ^m 12K-Gate ECL Gate                        With RAM and ROM                                                                       15.6
  4:05                                           Array
         T. Nishimura, H. Satoh, M. Tatsuki, A. Ohba, S. Hine, K.        Uga,    Y. Kuramitsu, Mitsubishi Electric Corp., Hyogo, Japan

  4:30   13000 Gate ECL Compatible GaAs Gate Array                                                                                              15.7
         W. Larkins, S. Canaga, G. Lee, W. Terrell, I.        Deyhimy, Vitesse Semiconductor Corp., Camarillo, CA
  4:55   LATE NEWS PAPER
                                                                                                                                                15.8
         A1.4ns/64kb RAM with             85ps/3680 Logic Gate Array
         M. Kimoto, H. Shimizu, Y. Ito, K. Kohno, M.lkeda, T. Deguchi, N. Fukuda, K. Ueda, S. Harada, K. Kubota,                      Fujitsu
         Ltd., Kawasaki, Japan
CONTENTS
WEDNESDAY AFTERNOON                                                 Friars/Padre/Sierra                                Session 16          PAPER


         TELECOMMUNICATION CIRCUITS
         Chairman: C.Jungo
         Co-Chairman: D.M. Embree

                                                                                                                                           16.1
  2:00   An  Analog Front End Chip for V.32 Modems
         J.P. Roesgen*, G.H. Warren**, Concord Data Systems, Marlborough, MA*; IMP,                      San   Jose,   CA**

  2:25   An Analog Front End for High Speed Fast Turnaround Modems                                                                         16.2

         R.Y. Halim, D. Shamlou, J. Illgner, Hayes Microcomputer Products, Inc., Norcross, GA

  2:50                                                                                                                                     16.3
         A£MO^na|paFK^
         l^^lrX'HrlsF^fe^t^PW^t*'J'Barner*'J- plary*-T- El-Kiki**,                                D.   McGuire**, AT&T Bell Labs, Murray


  3:15   Analog Front-End of an ECBM Transceiver for ISDN                                                                                  16.4
         R. Castello*, L. Tomasini**, S. Pernici**, F. Salerno***, M. Mazzucco***, M. Ferro***, University of Pavia, Pavia,

         Italy*; SGS-Thomson Microelectronics, Agrate Brianza, Italy**; CSELT, Torino, Italy***
  3:40   A Single Chip S-lnterface Transceiver for Public and Private ISDN                                                                 16.5
         F. Van   Simaeys,   J. Adams, D.   Rabaey,        M. Rahier, Alcatel—Bell Telephone      Mfg. Cy, Antwerp, Belgium
  4:05   A Codec with     On-Chip Digital Echo Canceller                                                                                   16.6
         V. Friedman*, J.M. Khoury*, L.J. Loporcaro*, M.J. Theobald*, E.M. Fields*, M.F. Tompsett*, V.P. Gopal**, G.L.
         Lustro**, M. Figueroa**, AT&T Bell Labs, Murray Hill, NJ*; AT&T Bell Labs, Naperville, IL**
  4:30   A No-Trimming SLIC Two-Chip Set With Coin Telephone Signaling Facilities                                                          16.7
         M. Akata, Y.   Nagataki, K. Koyabu,        K.   Mukai, S. Yoshida,   I. Ueki, NEC   Corp., Kawasaki, Japan
  4:55   LATE NEWS PAPER
         A 400MHz CMOS Packet Transmitter-Receiver Chip                                                                                    16.8
         A.J-H. Lee, J.A.    Sabnis,   M.W. Saniski, G.P.      Sampson, III, AT&T     Bell Labs. Allentown, PA




WEDNESDAY AFTERNOON                                                       Golden West                                   Session 17         PAPER


         PERFORMANCE OPTIMIZATION
         Chairman: M. Tarsi
         Co-Chairman: J. Barnes


  2:00   Automatic Circuit and           Layout Design for Mixed Analog/Digital ASICs                                                      17.1
         J. Trontelj, L. Trontelj, T. Slivnik, T.   Pletersek, G. Shenton, IMP Europe Ltd., Wilts,         U.K.

  2:25   PROMPT3—A Cell-Based Transistor Sizing Program Using Heuristic and Simulated Annealing                                            17.2
         Algorithms
         M-C. Chang, C-F. Chen,        AT&T Bell     Labs, Murray Hill,   NJ

  2:50   MOSIZ: A Two-Step Transistor Sizing Algorithm Based on Optimal Timing Assignment Method                                           17.3
         of Multi-State      Complex Gates
         Z-J. Dai, K. Asada,    University of Tokyo, Tokyo, Japan
  3:15   Operational Amplifier Compilation with Performance Optimization                                                                   17.4
         H. Onodera, H. Kanbara, K. Tamaru,              Kyoto University, Kyoto, Japan
  3:40   Optimal Ordering         of Gate Signals in CMOS Complex Gates                                                                    17.5

         M.   Lefebvre*, C. Chan**, Bell-Northern Research, Ottawa, Ont., Canada*; Carleton University, Ottawa, Ont.,
         Canada**

  4:05   Geometric Compaction of Building-Block Layout                                                                                     17.6
         X-M. Xiong, E.S. Kuh, University of California, Berkley, CA
  4:30   SDC Cell—A Novel CMOS/BiCMOS Design Methodology for Mainframe Arithmetic Module                                                   17.7
         Generation
         T. Hayashi*, T. Doi*, M. Asai*, K. Ishibashi*, S. Shukuri*, A. Watanabe**, M. Suzuki*, Hitachi Central Research Lab,
         Tokyo, Japan*; Hitachi Research Lab, Ibaraki, Japan**
CONTENTS

WEDNESDAY AFTERNOON                                                         California                                   Session 18              PAPER


         FABRICATION TECHNOLOGY
         Chairman: M. Hartranft
         Co-Chairman: P. Zeitzoff


  1:50   TUTORIAL
         Applications of CVD Tungsten in VLSI Circuits                                                                                           18.1
         S. Mehta, Cypress Semiconductor, San Jose, CA

  2:25   A Submicron CMOS Triple Level Metal Technology for ASIC Applications                                                                    18.2
         D. Fisher, K.Y. Chang,     F.   Pintchovsky,   J.   Klein, K-Y. Fu, S. Lai,   R.   Dillard, Motorola, Inc., Austin, TX
  2:50   GaAs MESFET           Digital Integrated Circuits Fabricated with Low Temperature Buffer Technology                                     18.3
         M.J.Delaney, C.S. Chou, L.E. Larson, J.F. Jensen, D.S. Deakin, A.S. Brown, W.W. Hooper, M.A.Thompson,                             LG.
         McCray, S.E. Rosenbaum, Hughes Research Labs, Malibu, CA
  3:15   A 5-Volt   Only Flash EEPROM Technology for High Density Memory and System IC Applications                                              18.4
         M. Gill, R. Cleavelin, S. Lin, I. D'Arrigo, G. Santin, P. Shah, A. Nguyen, R. Lahiry, P. DeSimone, G. Piva, J. Paterson,
         Texas Instruments Inc., Houston, TX
  3:40   A Submicron Analog CMOS         Technology                                                                                              18.5
         R.W. Gregor*,     K.J.
                           O'Brien*,      Wesley*, W.H. Stinebaugh, Jr.**,
                                            G.R.                                              H. Chew*, C.W.   Leung*,   AT&T Bell Labs,
         Allentown, PA*; AT&T Bell Labs, Murray Hill, NJ**
  4:05   A BiCMOS Technology with 660MHz Vertical PNPTransistorfor Analog/Digital ASICs                                                          18.6
         K.   Soejima,   A. Shida, M. Hirata, H.   Koga, J. Ukai,      H. Sata, NEC    Corp., Kanagawa, Japan
  4:30   A    Dual-Poly (n + /p +) Gate, Ti-Salicide,              Double-Metal        Technology for Submicron CMOS ASIC                        18.7
         and Logic Applications
         S.W. Sun, M. Swenson, J.R. Yeargain, C-O. Lee, C. Swift, J.R. Pfiester, W. Bibeau, W. Atwell, Motorola, Inc.,
         Austin, TX




WEDNESDAY EVENING PANEL                                                Friars/Padre/Sierra

  8:00   SILICON COMPILATION ON TRIAL: YOU BE THE JURY
         Moderator: J.      Lipman
                         VLSI Technology




WEDNESDAY EVENING PANEL                                                   Golden West

  8:00   MIXED MODE ASIC IN THE '90S: STILL WED TO CUSTOM
         Moderator: H.L.Scalf
                         American    Microsystems, Inc.            .




                                                                              «


WEDNESDAY EVENING PANEL                                                     California

  8:00   WHAT IS THE ROLE OF UNIVERSITIES IN THE IC DESIGN BUSINESS?
         Moderator: R. Saleh
                         University of Illinois
 CONTENTS

THURSDAY MORNING                                                              Regency                                      Session 19              PAPER


          CAD SYSTEMS FOR DESIGNS AND SPECIFICATIONS
          Chairman: A. Barlow
          Co-Chairman: T. Sideris

  8:30    The   Input/Output Specifications Analyzer for                    IC   Designs                                                           19.1
          E.S. Lee, H.T.    Chang,    R. Kovesdi, K.W. Su, AT&T Bell Labs,          Murray Hill,   NJ

  8:55    An    Approach to Knowledge-Based ASIC-Specification                                                                                     19.2
          K.D. Mueller-Glaser, J. Bortolazzi, University of           Erlangen, Neumberg,     W.   Germany
  9:20    Design Methodologies and CAD Tools                                                                                                       19.3
          C.   Piguet, CSEM, Neuchatel, Switzerland
  9:45    An Advanced         Design System: Design Capture, Functional Test Generation, Mixed Level                                               19.4
          Simulation and       Logic Synthesis
          M. Sekine*, T. Takei*, M. Aihara*, E. Yano*, K. Yamagishi*, K. Kohno*, K. Kitahara*, T. Fukasawa*, K. Iwawaki*,
          S. Ueda**, M. Kogure**, Toshiba ULSI Research Center, Kawasaki, Japan*;ToshibaOme Works, Ome City,
          Japan**
 10:10    Optimized Design Method for Full-Custom Microprocessors                                                                                  19.5
          K. Usami, J. Iwamura, Toshiba Corp., Kawasaki, Japan

 10:35    A    Fully Integrated Design Methodology For 10OK-Gate                         CMOS Custom LSIs With TAB                  Packaging      19.6
          T.   Yamamura,     K.   Kuwano,     S.   Sugatani, T. Tsujimura, Fujitsu Ltd., Kawasaki, Japan
 11:00    Computer Aids for High Performance CMOS Custom Design                                                                                    19.7
          T.C. Poon, Y.T. Oh, W.A. Oswald, P.             Magarshack, AT&T Bell Labs, Allentown,          PA




THURSDAY MORNING                                                        Friars/Padre/Sierra                                 Session 20             PAPER


          DIGITAL PROCESSORS AND SPEECH RECOGNITION
          Chairman: S.Hao
          Co-Chairman: L.         Christopher

   8:30   A Mask     Programmable DSP Array                                                                                                        20.1
          R.D. Albon, G.E.        Floyd,   J.E. Coles,   Plessey   Semiconductors Ltd.,   Plymouth,      U.K.

   8:55   A    High-Speed FIR Filter Designed by Compiler                                                                                          20.2
          R.   Hartley,   P. Corbett, P. Jacob, S. Karr, General Electric Co.,        Schenectady, NY
   9:20   A 20-Bit Decimator IC for                 High-Resolutioin Audio A/D Conversion                                                          20.3
          R.W.   Adams*, J. Frenkil**, D. Gottfried**, P. Pinelle**, dbx Inc., Newton, MA*; VLSI Technology, Inc., Wilmington,
          MA**
   9:45   The Design of           DSP   Components for the CD Digital Audio System Using Silicon Compilation                                       20.4
          Techniques
          R. Woudsma, A. Delaruelle,               Philips Res. Labs, Eindhoven, The    Netherlands

  10:10   A Multi-Channel           Digital        Demodulator for LVDT and RVDT Position Sensors                                                  20.5
          F.F. Yassa*, S.L. Garverick*, G. Ngo**, R. Hartley*, J. Prince**, J.            Lam**,   S.   Noujaim*,   R.   Korsunsky**, J.Thomas*,
          G.E. Co., Schenectady, NY*; G.E. Co., Binghamton, NY**

  10:35   RIPAC: A VLSI Processor for Speech                       Recognition                                                                     20.6
          L. Licciardi*, M. Paolini*, R. Tasso*, A. Torielli*, R. Cecinati**, CSELT, Torino,              Italy*; Elettronica San Giorgio,
          Genova, Italy**
  11:00   A VLSI    Wordprocessing Subsystem for a Real Time Large Vocabulary Continuous Speech                                                    20.7
          Recognition System
          A. Stolzle, S. Narayanaswamy, K. Kornegay, J. Rabaey, R.W. Brodersen, University of California, Berkeley, CA
CONTENTS

THURSDAY MORNING                                                             Golden West                             Session 21                  PAPER


           SIMULATION II
           Chairman: R.Saleh
           Co-Chairman: D. Johnson


  8:30     Switched-Capacitor Simulation Models for Full-Chip Verification                                                                       21.1
           T. Chanak*, R. Chadha**, K. Singhal***, Stanford University, Stanford, CA*; AT&T Bell Labs, Murray Hill, NJ**;
           AT&T Bell   Labs, Allentown,          PA***

  8:55     Functional-Level Simulation of Switched-Capacitor Circuits with Non-Ideal Switches and                                                21.2
           Operational Amplifiers
           D.   Giannopoulos,        S.   Wong, A. Lish, Philips Labs,   Briarcliff Manor, NY

  9:20     Dominant Pole(s)/Zero(s) Analysis for Analog Circuit                         Design                                                   21.3

           L.T.   Pillage, CM. Wolff,        R.A. Rohrer,   Carnegie Mellon University, Pittsburgh,   PA

  9:45     Extending SPICE for Electro-Thermal Simulation
           R.S. Vogelsong, C. Brzezinski, University of South Florida, Tampa, FL

 10:10     Computing            DC  Large Change Sensitivities                                                                                   21.5
           D.   Divekar,   H.   Daseking, R. Apte, Valid Logic Systems, San Jose,         CA

 10:35     Statistical Sensitivity             Analysis of MOSFET Integrated Circuits Using Process Database                                     21.6

           W.S.    Wong*,R.S. Winton*, J.J. Liou**, Mississippi State University, Mississippi State, MS*;            University of Central
           Florida, Orlando, FL**
 11 -.00   A Fast    Multipole Algorithm for Capacitance                    Extraction of    Complex 3-D Geometries                              21.7
           K. Nabors, J. White, M.I.T., Cambridge, MA


                                                                                 *



THURSDAY MORNING                                                               California                             Session 22                 PAPER


           TEST
           Chairman: P.         Fasang
           Co-Chairman: S. Davidson


  8:30     A Self-Testing ALU               Using Built-in Current Sensing                                                                       22.1


           P.   Nigh, W. Maly, Carnegie Mellon University, Pittsburgh,            PA

  8:55     A Serial    Interfacing          Technique for Built-in and External           Testing of Embedded Memories                           22.2
           B. Nadeau-Dostie*, A. Silburt*, V.K.          Agarwal**,   Bell-Northern Research Ltd., Ottawa, Canada*; McGill         University,
           Montreal, Canada**
  9:20     Detecting Stuck-Open Faults With Stuck-At Test Sets                                                                                   22.3
           S.D. Millman, E.J. McCluskey, Stanford University, Stanford, CA

  9:45     Boundary Scan & Its Application to Analog-Digital ASIC Testing                             in a   Board/System Environment            22.4
           P.P.   Fasang, National Semiconductor Corp., Santa Clara, CA
 10:10     Practical Built-in Test of CMOS State Machines with Realistic Faults: A System                              Perspective               22.5
           M. Katoozi*, M. Soma**, Seattle Silicon Corp., Bellevue, WA*;               University of Washington, Seattle,   WA**

 10:35     Physical Design of Testable VLSI: Techniques and Experiments                                                                          22.6

           M. Levitt*, J. Abraham**, University of Illinois, Urbana, IL*; University of Texas, Austin, TX**

 11:00     LATE NEWS PAPER
           Testing and Failure Analysis Methodology of the                           NS32532    Microprocessor                                   22.7
           E.Shihadeh, M. Beck, D. Biran, Y. Hoffman, T. Liran, B. Maytal, Y. Milkstein,              R. Nasrallah, Y. Nero, National
           Semiconductor (I.C.) Ltd., Migdal Haemek, Israel
CONTENTS

THURSDAY AFTERNOON                                                                 Regency                            Session 23               PAPER


         COMPLEX MODULE GENERATION AND ASSEMBLY
         Chairman: J. Barnes
         Co-Chairman: H-F.S. Law


  1:00   A    Compiler for Optimized Arithmetic Datapaths                                                                                      23.1
         K.F.   Pang, H.J. Huang, LSI Logic Corp., Menlo Park, CA
  1:25   A    Datapath Multiplier with Automatic Insertion of Pipeline Stages                                                                  23.2
         C.   Asato, C. Ditzen, S. Dholakia, VLSI Technology, Inc., San Jose, CA
  1:50   An N-Bus       Datapath Compiler for IC Design                                                                                        23.3
         R. Gordon, S.       McNeary,    T.   Ng, Y. Rotblum,   M. Tate, Silicon     Compiler Systems Corp.
  2:15   A 1.0 Mm Compilable FIFO Buffer for Standard Cell                                                                                     23.4
         M. Kawauchi*, M. Haraguchi*, Y. Okada*, Y. Tanaka**, H. Suzuki**, Toshiba Microelectronics Corp., Kawasaki,
         Japan*; Toshiba Corp., Kawasaki, Japan**
  2:40   A Generator for High-Density Macrocells With Hierarchical Structure                                                                   23.5
         K.   Takeya,   M.   Nagatani,   S.   Horiguchi, NTT LSI Laboratories, Atsugi, Japan
  3:05   High Speed Multi-Port Static RAM Silicon Compiler                                                                                     23.6
         H.H. Hana, S.J. Hussain, Seattle Silicon Corp., Bellevue, WA

  3:30   PANDA—A Hierarchical Mixed Mode VLSI Module Assembler                                                                                 23.7
         W.R. Bulllman, LA. Davieau, H.S. Moscovitz, G.D. O'Donnell, AT&T Bell Labs, Allentown, PA

  3:55   LATE NEWS PAPER
         Modular     Design of a High Performance 32-bit Microcontroller                                                                       23.8
         R.   Skruhak, M. McDermott, C. Wiseman, M. Taborn, J. Vaglica, E. Carter, Motorola, Inc., Austin,                TX




THURSDAY AFTERNOON                                                    Friars/Padre/Sierra                             Session 24               PAPER


         VIDEO AND IMAGE PROCESSING SYSTEM ICS
         Chairman: L.    Christopher
         Co-Chairman: F. Yassa


  1:00   A Mixed     Analog/Digital Video Signal Processing LSI With On-Chip                             AD and DA Converters                  24.1

         Y. Okada*, T. Matsuura*, T. Shinmi*, Y. Matsumoto**,  Nishijima***,  H.Masuda***, S. Ueda****, Hitachi
                                                                                                M.

         Central Research Lab, Tokyo, Japan*; Hitachi Semiconductor & IC Div., Tokyo, Japan**; Hitachi Consumer
         Research Center, Yokohama, Japan***; Hitachi Takasaki Works, Gunma, Japan****

  1:25   A    Digital Video Signal            Post-Processor for Color             Image Sensors                                               24.2

         L.J.
            D'Luna,      K.A.
                        Parulski,   Maslyn,   D.C.Hadley, M.A.               T.J.   Kenney,   R.H. Hibbard, R.M. Guidash, P.P. Lee, C.N
         Anagnostopoulos, Eastman Kodak Co., Rochester, NY
  1:50   A    Programmable         1400 MOPS Video              Signal   Processor                                                             24.3
         CM. Huizer, K. Baker, R. Mehtani, J. de Block, H. Dijkstra, P.J. Hynes, J. Lammerts, M.M. Lecoutere, A. Popp,
         A.H.M. van Roermund, P. Sheridan, R.J. Sluyter, F.P.J.M. Welten, Philips Research Lab, Eindhoven, The
         Netherlands

  2:15   A 30 nS    (600 MOPS) Image Processor with                      a   Reconfigurable Pipeline Architecture                              24.4
         K. Aono, M.    Toyokura, T. Araki, Matsushita          Electrical Industrial Co. Ltd.,   Moriguchi, Japan
  2:40   The    Design and Implementation of the IMS A110 Image and Signal Processor                                                           24.5
         S.R.   Barraclough,     M. Sotheran, K.     Burgin,   A.P. Wise, A. Vadher, W.P. Robbins, R.M.        Forsyth, INMOS Ltd., Bristol,
         U.K.

  3:05   A High    Speed Outline Font Rasterizing LSI                                                                                          24.6

         N. Kai, T. Minagawa, I. Nagashima, M. Ohhashi, Toshiba Corp., Kawasaki, Japan
CONTENTS

THURSDAY AFTERNOON                                                             Golden West                              Sesstion 25          PAPER

         AMPLIFIERS AND FILTERS
         Chairman: C.      Anagnostopoulos
         Co-Chairman: I. Scott

  1:00   Programmable, Four-Channel, 128-Sample, 40-Ms/s Analog-Ternary Correlator                                                           25.1
         S.C. Munroe, D.R. Arsenault, K.E. Thompson, A.L. Lattes, MIT Lincoln Laboratory, Lexington, MA
  1:25   A 10.7 MHz Continuous-Time                       Bandpass Filter Bipolar IC                                                         25.2
         M.   Koyama,     H.   Tanimoto,       S. Mizoguchi, Toshiba      Corp., Kawasaki, Japan
  1:50   A Very-Linear CMOS Transconductance Stage for OTA-C Filters                                                                         25.3
         P.M.   VanPeteghem,            B.J.   Haby,   H.M. Fossati, G.L.   Rice, Texas A&M University, College Station,    TX

  2:15   A2.4 Mm CMOS              Switched-Capacitor Video Decimator with Sampling Rate                          Reduction from 40.5        25.4
         MHz to 13.5 MHz
         R.P.   Martins, J. E. Franca, University TecnicadeLisboa, Lisboa, Portugal
  2:40   A Rail-to-Rail         Input/Output CMOS Power Amplifier                                                                            25.5
         M.D. Pardoen, M.G.R.             Degrauwe, Swiss Center for Electronics & Microtechnics, Neuchatel, Switzerland
  3:05   Construction of Analog Library Cells for Analog/Digital ASIC's Using Novel Designand                                      Modular   25.6
         Assembly Techniques
         M.J.S. Smith*, C.Anagnostopoulos**, C, Portmann***, R. Rao****, P. Valdenaire****, H. Ching****, University of
         Hawaii, Honolulu, Hawaii*; Eastman Kodak Co., Rochester, NY**; University of Nagoya***; VLSI Technology,
         Inc.****

  3:30   LATE NEWS PAPER
         Design and Optimization of CMOS Wideband Amplifiers                                                                                 25.7
         F.O. Op't Eynde, W. Sansen, Katholieke Universiteit Leuven, Heverlee, Belgium




THURSDAY AFTERNOON                                                               California                             Session 26           PAPER


         RELIABILITY
         Chairman: S.Quigley
         Co-Chairman: J.S. Runner


  1:00   Built-in Self-Repair Circuit for                  High-Density ASMIC                                                                26.1
         K. Sawada, T. Sakurai, Y. Uchino, K. Yamada, Toshiba                    Corp., Kawasaki, Japan
  1:25   Limitations of te Stuck-at Fault Model as an Accurate Measure of CMOS IC                                 Quality and a              26.2
         Proposed Schematic Level Fault Model
         R.J.   Lipp, Cross-Check Technology, San Jose, CA
  1:50   Metastability of CMOS Latch/Flip-Flop                                                                                               26.3
         L-S. Kim, R.     Cline,   R.   Dutton,   Stanford University, Stanford, CA

  2:15   An     Expert System to Assist in Diagnosis of Failures                       on   VLSI Memories                                    26.4
         T.   Viacroze,   M.   Lequeux,        IBM, Cestas, France
  2:40   Hot Carrier Effects on CMOS Circuit Performance                                                                                     26.5
         M.A.   Cirit, Silicon Compiler Systems, Warren,             NJ

  3:05   Pulse-Width Degradation in                     Digital   Circuits                                                                   26.6
         J. Tomczak*, T. Brooks*, C. Melorose**, IBM General                   Technology Division,   Essex Junction,   VT*; IBM General
         Products Division, San Jose, CA**

  3:30   The QML—An             Approach for Qualifying ASICS                                                                                26.7
         C.G.    Messenger, J.P. Farrell, Rome Air Development Center, GriffissAFB,                   NY

				
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