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Document Sample
Simulation of Power Electronic
Systems Using PSpice
Presented by Nik Din Muhamad
1
Presentation Outlines
In order to use Pspice for power electronic
systems, we have to:
Know background of SPICE
Understand Power Electronics Circuits/Systems
Know how to use VPULSE to generate useful
waveforms
Know how to make simple models using ABM
2
Scope
This presentation covers:
PSpice
System/Circuit Level Simulation
Power Electronic Circuits/Systems
Simulation
3
SPICE/PSpice
Did you know?
SPICE turns 38 years old this year
I Knew SPICE when she was 17 years old
I love PSpice because she can do almost
anything I need with FOC.
I like to talk about her.
4
Why simulation?
Simulations are essential ingredients of the
analysis and design process in power
electronics:
Saving of development time
Saving of costs („burnt power circuits tend
to be expensive‟)
Better understanding of the function
5
… continued
Testing and finding of critical states and
regions of operation (Worst Case Analysis)
Stress test (Smoke Analysis)
Optimization of system
Testing new ideas
6
Overview
Simulation of analog circuits normally
uses three basic tools:
SPICE simulator,
Mathematical analysis package,
and Microsoft Excel.
7
SPICE
Simulation Program for Integrated Circuit
Emphasis
Intended for ICs, not for power electronics.
Uses iterative Newton-Raphson Algorithm
to solve a set of nonlinear equations.
8
SPICE LIMITATIONS
The Newton-Raphson algorithm is guaranteed
to converge if the equations is continuous.
The transient analysis has the additional
possibility of unable to converge because of the
discontinuity in time.
9
SPICE LIMITATIONS
Computer Hardware Limitation:
• Voltage and currents are limited to +/-1e10.
• Derivatives in PSpice are limited to 1e14.
• The arithmetic used in PSpice is double
precision and has 15 digits of accuracy.
10
Power Electronic Circuit
Power electronic circuits
are characterized by switching
on and off of power
semiconductor switches; the
generated waveform is
passed through inductors and
capacitors for filtering.
11
Power Electronic Circuit
Due to switching action of the switch,
discontinuity (in circuit variables and in
time) can easily occur during simulation,
which leads to convergence problem.
“Avoid discontinuity”
12
Discontinuity Analogy:
A Bump on the Road
Unacceptable Bump
Acceptable Bump
“Whole car shakes when I hit a bump on the road”
PSpice doesn’t like discontinuity as we don’t like
a bump on the road.
13
Avoid Discontinuity
S
G
VGS VGS
t t
All signals must be made „less discontinuous‟
All relationships must be continuous
14
VPULSE
Waveform generator
PULSE
SAWTOOTH
TRIANGULAR
15
VPULSE
Waveform generator
In order to use PSpice for power electronic
circuits, the first thing you have to know is to
program VPULSE to produce these waveforms:
PULSE
Sawtooth
Triangular
16
VPULSE
Waveform Generator Part
has 7 parameters to set
TD can be zero, others can not!
V1= PW
V2= V2
TD=
TR=
TF=
V1 TD
PW=
PER
PER=
know what parameters to adjust and to fix.
17
VPULSE
To Generate Pulse Waveform
Very small values for TR and TF
Duty cycle = PW/PER
PW
V1=0
V2=12 V2
TD=0
TR=10n
TF=10n
PW=10u V1
TR ≈ 0 TF ≈ 0
PER=20u
PER
18
A Typical application
Buck Converter (Open Loop)
M2
IR F15 0
10 0uH
V2 68 0uF 10
V3 MU R1 520
20 V
V+ V-
TD = 0
TF = 1 0n
PW = 10u
PE R = 20u 0
V1 = 0
TR = 1 0n
V2 = 1 2V
A Pulse waveform is used to drive a MOSFET
ON and OFF.
19
Its Pulse (I)
V1=0
V2=12
TD=0
TR=10n
TF=10n
PW=10u
PER=20u
PW 10
Duty Cycle, D 50%
PER 20
20
Its Pulse (II)
V1=0
V2=12
TD=0
TR=10n
TF=10n
PW=5u
PER=20u
Duty cycle of the waveform is adjusted by adjusting PW
PW 5
D 25%
PER 20
21
VPULSE
To Generate Sawtooth
Very small values for TF and PW
TR≈PER
V1=0
V2=12 PW
TD=0
TR={20u-20n}
TF=10n TF
PW=10n
PER=20u
PER
22
A Typical application
Buck Converter (Closed Loop)
M2
IR F15 0
10 0uH
V2 68 0uF 10
E1
Gate
+
-
MU R1 520
+
-
20 V E
Driver GA IN = 4
Comparator 0
-
Sawtooth V4 + For Closed-loop, the control signal
Gen.
is compared with a sawtooth
Control waveform to produce the pulse
0 Signal
waveform.
23
PSpice Implementation
M2
IR F15 0
10 0uH
V2 68 0uF 10
Gate E1
+
-
MU R1 520
+
-
20 V E
Driver GA IN = 1
0
V5
Comparator
E2
Control IN +OU T+
IN - OU T-
Signal
2.5 Vdc
Gate Driver E
ETABL E
V3
0 0
Comparator ETABLE
TD = 0 TA BLE = (0 ,0 ( 200u ,12 )
TF = 1 0n V( %IN +, % IN-)
PW = 10n
0PE R = 20u
Sawtooth VPULSE
V1 = 1 V
TR = { 20u- 20n}
V2 = 4 V
Vpulse Control VDC
24
Its Waveform (I)
Control
Sawtooth
D = 50 %
Pulse
25
Its Waveform (II)
Control
Sawtooth
D = 33%
Pulse
Duty Cycle of the Pulse is adjusted by adjusting
Control Signal.
26
VPULSE
To Generate Triangular wave
Very small value for PW
TR≈TF ≈ PER/2
V1= -1 PW
V2= +1
TD=0
TR= {10u-10n}
TF= {10u-10n}
PW=20n
PER=20u PER
27
VPULSE
Its Triangular Wave
28
Triangular Wave
Typical applications
Bipolar SPWM
TR I SI NE
V V
V1 = -1 V1 VD C*( V(SI NE) -V(TRI))/ ABS (V(S INE )-V( TRI) )
V2 = +1
TD = 0 V2
TR = { (1/(F TRI *2))- 10n} VO FF = 0 SP WM
TF = {( 1/(F TRI* 2)-1 0n)} VA MPL = { Ma}
PW = 20n FR EQ = {F SIN E} V
PE R = {1/F TRI } PH ASE = { -90/ Mf }
Comparator
0 0
PARAMETERS:
Ma = 0 .8
Mf = 2 1
FTRI = {FS INE *Mf }
FS INE = 5 0
VD C = 100
29
Triangular Wave
Typical applications
Bipolar SPWM
1.0V
0V
-1.0V
V(TRI) V(SINE) 0
100
0
-100
40ms 42ms 44ms 46ms 48ms 50ms 52ms 54ms 56ms 58ms 60ms
V(SPWM) 0
Time [ms]
30
Triangular Wave
Typical applications
Unipolar SPWM
TR I SI NE1
V V
V1 = -1 V1 0.5 *VD C*( V(SI NE1 )-V( TRI) )/AB S(V (SIN E1) -V(TRI))
V2 = +1
TD = 0 V2
TR = { (1/(F TRI *2))- 10n } VO FF = 0 A
TF = {( 1/(F TRI *2)-1 0n)} VA MPL = { Ma}
PW = 20n FR EQ = {F SIN E} V
PE R = {1/F TRI } PH ASE = { -90/ Mf }
0 0
Comparator 1
SI NE2
V
PARAMETERS: 0.5 *VD C*( V(SI NE2 )-V( TRI) )/AB S(V (SIN E2) -V(TRI))
Ma = 0 .8
Mf = 2 1 V2 a
FTRI = {FS INE *Mf } VO FF = 0 B
FS INE = 5 0 VA MPL = { Ma}
VD C = 100 FR EQ = {F SIN E} V
PH ASE = { -90/ Mf +180}
0
Comparator 2
31
Triangular Wave
Typical applications
Unipolar SPWM
1.0V
0V
-1.0V
V(SINE1) V(SINE2) V(TRI)
100V
0V
-100V
40ms 42ms 44ms 46ms 48ms 50ms 52ms 54ms 56ms 58ms 60ms
V(A)-V(B)
Time [ms]
32
Analog Behavior Model (ABM)
Makes the Circuit Simpler
Use equations to model circuits
Comparator
Single Phase Rectifier
Three Phase Rectifier
Buck Converter in CCM
Single Phase Inverter
33
ABM
Behavior Model of Comparator
V(-) IF the voltage at the terminal V(+) is
V(out)
- greater than the voltage at terminal
V(+)
+ V(-) the output V(out) is HIgh,
otherwise the output is LOw.
(1) Using IF-Then-Else function
IF(V(+)>V(-),HI, LO)
(2) Using signum function
(V(+)-V(-))/ABS(V(+)-V(-))
34
ABM
Behavior Model of Comparator
V(-)
V(out)
-
V(+)
+
(3) Using I/O graph (4) Using Op-amp alike
V(out) V(+) V(out)
+
0 V(+)-V(-) - A*(V(+)-V(-))
V(-)
0
35
ABM
Comparator in PSpice
IF (V(S INE )>V( TRI) ,10, -10)
TR I SI NE
ou t1
V1 = -1
V2 = +1
V1
V V
1
V
TD = 0 V2
TR = { (1/(F TRI *2))- 10n } VO FF = 0 SI NE E1
TF = {( 1/(F TRI *2)-1 0n)} VA MPL = { Ma} ou t2
IN +OU T+
PW = 20n
PE R = {1/F TRI }
FR EQ = {F SIN E}
PH ASE = { -90/ Mf } 2 IN - OU T-
ETABL E V
TR I
0 0 V( %IN +, % IN-) 0
PARAMETERS: TA BLE = (- 100 u,-10 ) (1 00u, 10)
Ma = 0 .8
Mf = 2 1 VD C*( V(SI NE) -V(TRI)) /ABS (V(S INE )-V( TRI ))
FTRI = {FS INE *Mf }
FS INE = 5 0
ou t3
VD C = 10
3
NO 2 is implemented using ETABLE V
LIMIT( 10k* (V(S INE )-V( TRI) ),10 ,-10)
Others are implemented using ABM part
NO 2 & NO 4 are suitable for Op-amp 4
ou t4
(Error Amplifier) V
36
ABM
Behavior Model of Comparator
1.0V
0V
-1.0V
V(TRI) V(SINE)
10V
0V
These waveforms come from the outputs of four comparators
-10V
40ms 42ms 44ms 46ms 48ms 50ms 52ms 54ms 56ms 58ms 60ms
V(OUT3) V(OUT2) V(OUT1) V(OUT4)
Time [ms]
37
ABM
Behavior Model of Rectifier (I)
D3 D4
Db reak Db reak
V1 a
VO FF = 0
VA MPL = 3 40 R1 a
FR EQ = 50
1k
D5 D6
Db reak Db reak
0
in
V(out)=ABS(V(IN))
V1 E1
VO FF = 0 R1 b
VA MPL = 3 40 IN +OU T+
FR EQ = 50 IN - OU T- 1k
EV ALU E
ABS(V(IN))
0 0
38
ABM
Behavior Model of Rectifier (II)
+
Van
V(out) = 0.5*(ABS(V(an)-V(bn)
Vbn
+ABS(V(bn)-V(cn))
Vcn +ABS(V(cn)-V(an)))
-
39
ABM
Behavior Model of Buck in CCM
IR F54 0
10 0uH
+
V2
68 0uF RL
20 Vdc V3
MU R1 520 Vd
TD = 0 - Vd = d*Vin
TF = 1 0n
PW = 10u
PE R = 20u 0
V1 = 0
TR = 1 0n
V2 = 1 2V
10 0uH
+
d is a PWM signal d
E1
IN +OU T+
68 0uF RL
with 1V amplitude. Vin IN - OU T-
EV ALU E
Vd
V(%IN+)*V( %IN-)
-
0
40
ABM
Behavior Model of Inverter
a
+
VDC Vab
-
b Bipolar SPWM
E1 +
SINE
IN+ OUT+
IN- OUT-
Vab
TRI
EVALUE -
VDC*(V(%IN+)-V( %IN-))/ABS(V(%IN+)-V( %IN-))
0
41
#TIPS
There are many different ways
to model the same thing. So, be
creative!
Use a simple model wherever
possible to reduce modeling time
and make simulation run faster
and converge better!
42
Quote about Model !
“Models are like shoes; there is no one-size-
fits-all model.”
43
Our Case Study
A Buck Converter with VMC
A Simple PWM Controller IC Model
A PWM IC Controller IC Model including
Soft-start
A PWM IC Controller IC Model Including
Soft-start, Duty Cycle Max and Current
Limiter
44
Our Case Study
A Buck Converter with VMC
+
-
+
-
0
SG3525
PWM Controller IC 0
45
SG3525
PWM Controller IC
Key Functions:
Oscillator
(Sawtooth Generator)
PWM Comparator
and SR Flip-flop
Error Amplifier
5.1 V Reference
Pulse Steering
Logic
Shutdown and
Soft-start Circuitry
46
SG3525
We do not need to have SG3525 model in
PSpice‟s library to simulate buck converter with
VMC.
To verify the controller design, all we need are
functional models of these:
Error Amplifier
Comparator
Sawtooth generator
47
SG3525
A Simple Model
Sawtooth
-
+ To MOSFET
+ Driver
-
Comparator
Error Amp.
48
A Buck Converter with VMC
Buck Converter
+
-
+
-
Consider we know all 0
circuit parameters.
Our interest is to Comparator Error Amp.
0
-
simulate the system. +
- +
The controller is used VP ULSE
Vref
to regulate the output 0
Sawtooth 0
voltage at 5 V.
49
A Buck Converter with VMC
The controller is a linear controller and the
design is based on a small-signal model.
So, the controller can not cope with large
signal scenario such as start-up.
Initial values, which are equal to their steady
state values, for the inductor current and the
capacitor voltage must be set.
50
Load Disturbance
How to set a load disturbance ?
Let the load disturbance is:
3A
1A
0A
8 ms 8.5 ms
R = 1.666 W
R=5W
R=5W
R is changed from 5 W to 1.666 W
51
Our Case Study
How to set load disturbance ?
Using IPULSE
I1 = 1 I1
1
I2 = 3
ILOAD
TD = 8m
TR = 0.1u
TF = 0.1u
PW = 0.5m
PER = 1m
Allocate enough times for TR and TF
52
Load Disturbance
How to set load disturbance ?
Using SW_tclose and SW_topen
N
TOPE = 8.5m
1 2
E
TCLOS = 8m
2 5 2 .5
5//2.5 =1.666
53
Load Disturbance: PSpice
M1
IRF150 R1av L1
i nput out
{L}
50m V 0Vdc ILOAD
I
I
IC = 1A R2av
V2
15Vdc D5 {Resr}
E1 Dbreak I1 = 1 I1
+
-
GA IN = 3 + I2 = 3
- E C1av TD = 8m
TR = 0.1u
{C} TF = 0.1u
IC = 5V PW = 0.5m
PE R = 1m
0
C3av
R6av{C3} C2av R7av C4av
{R2} {C2} {R1} {C1}
E2av E1av R4av
OUT+ IN+ OUT+ IN+
OUT- IN- OUT- IN- V2av {R3}
(0,0) (250u,5) V1 = 0 V1 ET ABLE
ET ABLE V2 = 3 -V(%IN+, %IN-) R2
V(%IN+, %IN-) TD = 0 (0,0) (250u ,6)
0 TR = {10u-20n} {Rbias}
TF = 10n {Vref }
PW = 10n 0 0
PE R = 10u 0 0
54
Load Disturbance: Results
5.2V
Output Voltage
5.0V
4.8V
V(OUT)
4.0A
2.0A Inductor Current
0A
7.8ms 7.9ms 8.0ms 8.1ms 8.2ms 8.3ms 8.4ms 8.5ms 8.6ms 8.7ms 8.8ms
I(L1) I(ILOAD)
Time [ms]
55
Input Disturbance
How to set an input disturbance ?
Let the input disturbance is:
25 V
15 V
0V
8 ms 8.5 ms
56
Input Disturbance
How to set an input disturbance ?
Use VPWL (Piece-Wise Linear Voltage Source)
25 V
15 V
0V
8 ms 9 ms
PWL(T1,V1)(T2,V2)(T3,V3)(T4,V4)(T5,V5)
PWL (0,15) (8m,15) (8.0001m,25) (9m,25) (9.0001m,15)
57
Input Disturbance
Responses
30V
25V
20V
Input Voltage
10V
V(INPUT)
5.1V
5.0V
4.9V Output Voltage
4.8V
V(OUT)
2.0A
Inductor Current
1.0A
0A
7.8ms 8.0ms 8.2ms 8.4ms 8.6ms 8.8ms 9.0ms 9.2ms 9.4ms 9.6ms 9.8ms 10.0ms
I(L1)
Time [ms]
58
Start-up Scenario
Previous simulation skips start-up scenario.
To know how the controller handles start-up, set the initial
values for iL and vc to zero.
20
15
Inductor Current
10
Output Voltage
5
0
0s 100us 200us 300us 400us 500us 600us 700us 800us
I(L1) V(OUT)
Time [s]
59
Start-up Scenario
A very large overshoot and undershoot occur in inductor current.
The duty cycle is at first at 1 for a long time and later at 0 for a long
time too, then after that it gradually increases.
Convergence problem can easily occurs at this extreme condition.
5.0V
2.5V
Gate Signal
0V
V(E1:1)
20
15
10
5
0
0s 100us 200us 300us 400us 500us 600us 700us 800us
I(L1) V(OUT)
Time
60
Start-up
In practical circuit, another auxiliary controller is
required to handle start-up.
This circuit is known as soft-start.
Soft start VMC
5.0V
Controller Controller
2.5V
Gate Signal
0V
V(E1:1)
20
15
10
5
0
0s 100us 200us 300us 400us 500us 600us 700us 800us
I(L1) V(OUT)
Time [s]
Soft-start circuit works by gradually increasing the duty
cycle. So do the inductor current and capacitor voltage.
61
Soft-start
To add Soft-start
The previous PWM IC model is very useful and it is
simple to set-up in PSpice.
It is enough to verify the design of controller based on
small signal model.
However, to add soft-start controller and other
protection circuits, we need a more flexible PWM IC
model.
62
A Modified PWM IC Model
Oscillator Clock
Sawtooth
Comparator SR Flip-flop
+ S
+ R
- Q
-
Error Amp.
The output of SR flip-flop is set by the Clock.
The output of SR flip-flop is reset by Comparator.
63
A Modified PWM IC Model
Oscillator Clock
Sawtooth
Error Amp.
Comparator SR Flip-flop
+
+ S
- R
- Q
-
Analog R
- R
Signals Digital
Signals
Analog signals can be added at minus terminals of the
comparator.
Digital signals can be added at the input Resets of FF.
64
Soft-start
To add Soft-start Signal
Sawtooth
+
Error Amp. To R of SR
-
Control Output Flip-Flop
Signal
Soft-start -
Sawtooth is still compared with the control signal.
But, Control Signal can be either Error Amp. output
(EAO) or Soft-start signal (SS), whichever is lower.
65
Soft-start
To add Soft-start Signal
Sawtooth
50 A +
Soft-start (SS) To R of SR
-
Flip-Flop
Error Amp.
C
Output (EAO) -
The soft-start voltage is the capacitor voltage.
The capacitor C is charged by a constant current
source of 50 A. The result is a ramp voltage.
C determines the duration of soft-start.
66
Soft-start
How Soft-start works?
Soft-start
V
I C
Voltage
t
4V
50
Slope =
C
C = 125 nF
10 ms t
Use PWL to emulate soft-start voltage
For the graph, PWL(0,0)(10ms,4V)
67
Soft-start
To add Soft-start Signal
Sawtooth
50 A +
SS To R of SR
Control - Flip-Flop
EAO Signal
C
Selector
We need a selector to select either SS or EAO,
whichever is lower, to be Control Signal.
We can use IF-Then-Else function
IF(SS < EAO, SS, EAO)
68
Soft-start
In PSpice
C3av Error Amplifier
SELECTOR
IF-Then-Else R6av{C3} C2av R7av C4av
-V(%IN+, %IN-) IF( V(%IN2)<V(%IN1),
(0,0) (250u,5) V(%IN2),V(%IN1) ) {R2} {C2} {R1} {C1}
E1av R4av
R E2av ET ABLE 1 err_out
OUT+ IN+
Vout
control 3
OUT+ IN+ 2 OUT- IN- V2av {R3}
OUT- IN- Sawtooth ET ABLE
-V(%IN+, %IN-) R2
Comparator SoftS (0,0) (500u ,5) {Rbias}
V1 = 0 V1
V2 = 3 {Vref }
0 TD = 0 V3 0
TR = {10u-20n} 0 0
TF = 10n TRAN = PWL(0,0)(10m,4)
PW = 10n 0
PE R = 10u 0
Sawtooth
Generator
69
Soft-start
Start-up Signals
Control = IF(SS < EAO, SS, EAO)
5.0V
2.5V Error Amplifier Output
0V
5.0V
2.5V
Soft-Start Signal
0V
2.0V
Control Signal
1.0V
0V
0s 1.0ms 2.0ms 3.0ms 4.0ms 5.0ms 6.0ms
Time [ms]
70
Soft-start
C = 125 nF (Too Small!)
7.5V
5.0V
2.5V
V(OUT) tstart-up = 1ms
0V
4.0A
2.0A
I(L1)
0A
0s 1.0ms 2.0ms 3.0ms 4.0ms 5.0ms 6.0ms
Time [ms]
Soft-start signal ramps up too fast
71
Soft-start
Start-up Current and Voltage
7.5V
5.0V
C = 25 nF
2.5V
V(OUT) tstart-up = 3.2 ms
0V
2.0A
1.0A
I(L1)
0A
0s 1.0ms 2.0ms 3.0ms 4.0ms 5.0ms 6.0ms
Time [ms]
Still has a small overshoot and undershoot in
inductor current
has a room for improvement by increasing C.
72
Soft-start
Start-up Current and Voltage
6.0V
4.0V
2.0V V(OUT)
0V
V(OUT)
2.0A
1.0A
I(L1)
SEL>>
0A
0s 5ms 10ms 15ms 20ms 25ms 30ms 35ms
I(L1)
Time
C = 125 nF ; Start-up time is 30 ms.
73
A Modified PWM IC Model
Oscillator Clock
Sawtooth
Error Amp.
Comparator SR Flip-flop
+
+ S
- R
- Q
-
Analog R
- R
Signals Digital
Signals
To add digital signals for protection.
For examples, Maximum Duty Cycle and Current Limiter
Flip-flop can be reset either by PWM comparator, or
Maximum duty cycle, or Current Limiter.
74
To Add Digital Signals
DutyMax and CurrentLimit
Maximum duty cycle limiter is in digital form. It can be
applied directly to the Reset of FF.
The switch current (or inductor current) must be compared
with its limit value to produce a digital signal.
Dutymax
V1 = 0 Vdutymax
V2 = 5V
RESET 3 (DMax) TD = {10u*0.85 }
TR = 10n
1 TF = 10n
2 3 U12A PW = {(10u-10u*0.85)-20n}
Q 1 U10A 7432 2 PE R = 10u 0 I(L1)
7402 3 Ecurr_l imit
OUT+ IN+
RESET 2 (CL) OUT- IN-
8A
1 ET ABLE
2 3 U16A 0 +V(%IN+, %IN-)
1 U11A 7432 2 R
7402 3 SET
S
(0,0) (250u,5)
V1 = 0 VClock
RESET 1 (EAO)
V2 = 5V
TD = 0 Set only by one i. e. the clock
Reset can be done by three, whichever
TR = 1n
TF = 1n
PW = 0.1u
PE R = 10u 0
comes first.
75
To Add Digital Signals
DutyMax and CurrentLimit
5.0V
CLOCK
2.5V
0V
5.0V
V(S) DUTYMAX
2.5V
0V
V(DUTYMAX)
4.0V
SAWTOOTH
2.0V
0V
0s 20us 40us 60us 80us 100us 120us 140us 160us 180us 200us
V(SAWTOOTH)
Time
DUTYMAX signal will only reset FF if the duty cycle is more than 0.85
This DUTYMAX is to make sure that the MOSFET always turns-off for
each cycle
CurrentLimit signal will only appear and reset FF if the peak switch is
greater than pre-specified value.
76
To Add Digital Signals
DutyMax and CurrentLimit
10
Output Voltage
5
Inductor Current
0
5.6ms 5.7ms 5.8ms 5.9ms 6.0ms 6.1ms 6.2ms 6.3ms 6.4ms 6.5ms 6.6ms
V(OUT) I(L1)
Time
We want to limit this current at 8A
77
To Add Digital Signals
DutyMax and CurrentLimit
What do we expect ?
10
8A Limiter
Output Voltage
5
Inductor Current
0
5.6ms 5.7ms 5.8ms 5.9ms 6.0ms 6.1ms 6.2ms 6.3ms 6.4ms 6.5ms 6.6ms
V(OUT) I(L1)
Time
Reset by EAO Reset by Reset by Reset by EAO
DutyMax CurrentLimit
78
To Add Digital Signals
DutyMax and CurrentLimit
5.0V
2.5V
0V
V(CLOCK)
5.0V
2.5V
0V
V(PWMCOMP) V(Q)
5.0V
2.5V
0V
V(CURRENTLIM) V(Q)
5.0V
2.5V
0V
5.90ms 5.95ms 6.00ms 6.05ms 6.10ms 6.15ms 6.20ms
V(DUTYMAX) V(Q)
Time [ms]
A Load disturbance
at 6.0 ms
79
Knowing
“There is no substitute for knowing
what we are doing”
80
CONCLUSION
In order to simulate power electronic circuit:
Know how to program VPULSE for Pulse,
Sawtooth, and Triangular waveforms.
Avoid discontinuity at any cost
Use the simplest model possible
Use a simple model first, and add
complexity in stages.
No replacement for good understanding
81
Q&A
82
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