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Dual Path Ethernet Transceiver Team Members: Advisor: William Donat Dr. John Chandy Calvin Zulick Sponsor: Donville Riley ECE Department Outline Why Dual Ethernet Transceiver? Background Our Solution Specifications Project Schedule Budget Conclusion Why a Dual Ethernet Transceiver? Redundancy Reliability Security Existing Technology is too costly Overview SIDE SIDE System System Input / Input / Output Output PATH A Design Design Solution Solution PATH B Background Information What is Ethernet? Developed in mid 1970’s by Xerox Corporation IEEE 802.3 CSMA/CD LAN technology Ethernet/802.3 maintains greatest market share of LAN CSMA/CD Carrier Sense Multiple Access/Collision Detection Broadcast Network Transmission Medium Coax, Fiber Optic or Twisted Pair Our project will be point-to-point OSI Model Seven Layers Application Presentation 7 Application E-mail or file transfer Translates Data 6 Presentation Session 5 Session Manages Dialogue Transport 4 Transport Optimization of Data 3 Network Network Ensure proper routing 2 Data Link LLC, MAC Data Link Transmission, error detection and 1 Physical flow control Physical Pin outs, voltage levels, bit timing and transceiver. Data Frame Layout Example Data Frame Preamble SFD Destination Address Source Address Length Data CRC 7 Bytes 1 Byte 6 Bytes 6 Bytes 2 Bytes 46-1500 Bytes 4 Bytes Preamble Indicates the beginning of frame transmission. Start Frame Delimiter Indicates the start of information. Destination Address Source Address Length Indicates the length of the data field. Data Cyclic Redundancy Check (Frame Sequence Check) Specifications Specifications Ethernet Standard Compliance IEEE 802.3 Power AC 110V Operational Configuration Standalone Number of Data Channels 1 Operational Environment o 10 C to 50oC Transmission Rate 10Mbps (Minimum) Size No Larger than ATX Form-Factor Visual Display LED will light to indicate which channel is active. Number of Redundant Paths 2 Our Solution Hardware Solution • Incoming signal is split, but otherwise unmodified by system • Ethernet Microcontrollers “snoop” the signal and perform CRC Check • CRC status is passed to digital logic to determine which signal is passed by the switch. Block Diagram Splitters Tested successfully Freescale MC9S12NE64 Ethernet Microcontroller •Built in Ethernet connectivity •Widely available evaluation and demo boards within our budget •Abundance of documentation and application notes, as well as a university support team. Freescale Demo Board Pinged it successfully Compiled software and programmed the microcontroller. Still learning the Code Warrior software. MAX301 Analog Switch •Designed to be a precision, high-speed analog switch •Digital logic signal controls operation of chip •Available for ~$10 Expectations for Design Advantages • Not much programming required • Fairly simple solution to meet design goals Disadvantages • At 100 Mbps we have to consider E&M effects. • Switch must preserve signal so that it is useable for output • Microcontroller was not intended for such a high throughput application so our design must be verified in practice Project Schedule Fall 2004 Spring 2005 October November December January February March April Tasks Wk1 Wk2 Wk3 Wk4 Wk1 Wk2 Wk3 Wk4 Wk1 Wk2 Wk3 Wk4 Wk1 Wk2 Wk3 Wk4 Wk1 Wk2 Wk3 Wk4 Wk1 Wk2 Wk3 Wk4 Wk1 Wk2 Wk3 Wk4 Research Ethernet Microcontrollers Research Alternative Designs Research and obtain Splitters Integrity testing for switching Research and Design CRC logic Learn how to detect CRC errors Obtain device that switches based on logic Prototyping Testing Presentations Primary Secondary Work in Milestones Key: Schedule Schedule Progress Budget Part Estimated Price Quantity Total Price Ethernet Microcontroller Evaluation Board 300 1 300 Ethernet Microcontroller Demo Board 100 1 75 Ethernet Microcontroller 25 6 150 Standard Microcontroller 15 2 30 Printed Circuit Board 75 4 300 Miscellenous Chips and Cables 100 1 100 Physical Data Channels ? 2 ? Estimated Total Price 955 Conclusion • Either design will meet our project goals, providing the desired function at a low cost. • It will be fairly easy to test each component of the primary design, giving us plenty of time to switch designs if necessary.
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