Dual Path Ethernet
Team Members: Advisor:
William Donat Dr. John Chandy
Calvin Zulick Sponsor:
Donville Riley ECE Department
Why Dual Ethernet Transceiver?
Why a Dual Ethernet
Existing Technology is too costly
System Input /
Input / Output
Output PATH A
What is Ethernet?
Developed in mid 1970’s by Xerox
CSMA/CD LAN technology
Ethernet/802.3 maintains greatest market
share of LAN
Carrier Sense Multiple Access/Collision
Coax, Fiber Optic or Twisted Pair
Our project will be point-to-point
E-mail or file transfer
Translates Data 6 Presentation
Transport 4 Transport
Optimization of Data
Ensure proper routing 2 Data Link
Transmission, error detection and 1 Physical
Pin outs, voltage levels, bit timing
Data Frame Layout Example
Preamble SFD Destination Address Source Address Length Data CRC
7 Bytes 1 Byte 6 Bytes 6 Bytes 2 Bytes 46-1500 Bytes 4 Bytes
Indicates the beginning of frame transmission.
Start Frame Delimiter
Indicates the start of information.
Indicates the length of the data field.
Cyclic Redundancy Check (Frame Sequence
Ethernet Standard Compliance IEEE 802.3
Power AC 110V
Operational Configuration Standalone
Number of Data Channels 1
Operational Environment o
10 C to 50oC
Transmission Rate 10Mbps (Minimum)
Size No Larger than ATX Form-Factor
Visual Display LED will light to indicate which channel is active.
Number of Redundant Paths 2
• Incoming signal is split, but otherwise unmodified by
• Ethernet Microcontrollers “snoop” the signal and
perform CRC Check
• CRC status is passed to digital logic to determine which
signal is passed by the switch.
Freescale MC9S12NE64 Ethernet Microcontroller
•Built in Ethernet connectivity
•Widely available evaluation and demo boards within our budget
•Abundance of documentation and application notes, as well as a university
Freescale Demo Board
Still learning the
MAX301 Analog Switch
•Designed to be a precision, high-speed analog switch
•Digital logic signal controls operation of chip
•Available for ~$10
Expectations for Design
• Not much programming required
• Fairly simple solution to meet design goals
• At 100 Mbps we have to consider E&M effects.
• Switch must preserve signal so that it is useable for output
• Microcontroller was not intended for such a high throughput
application so our design must be verified in practice
Fall 2004 Spring 2005
October November December January February March April
Tasks Wk1 Wk2 Wk3 Wk4 Wk1 Wk2 Wk3 Wk4 Wk1 Wk2 Wk3 Wk4 Wk1 Wk2 Wk3 Wk4 Wk1 Wk2 Wk3 Wk4 Wk1 Wk2 Wk3 Wk4 Wk1 Wk2 Wk3 Wk4
Design CRC logic
Learn how to
based on logic
Primary Secondary Work in
Key: Schedule Schedule Progress
Part Estimated Price Quantity Total Price
Ethernet Microcontroller Evaluation Board 300 1 300
Ethernet Microcontroller Demo Board 100 1 75
Ethernet Microcontroller 25 6 150
Standard Microcontroller 15 2 30
Printed Circuit Board 75 4 300
Miscellenous Chips and Cables 100 1 100
Physical Data Channels ? 2 ?
Estimated Total Price 955
• Either design will meet our project goals, providing the desired function at
a low cost.
• It will be fairly easy to test each component of the primary design, giving
us plenty of time to switch designs if necessary.