Group
Name of Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
Start address
Interrupt control Type Register 0xE000E000
(system control space)
0xE000E004 Reserved
0xE000E008
SCS_Base
0xE000E00C
SysTick Control and Status Register 0xE000E010 Reserved COUNTFLAG
SysTick Reload Value Register 0xE000E014 Reserved RELOAD Value (between 1 and 0x00FFFFF
SysTick Current Value Register 0xE000E018 Reserved Current Value
SysTick Calibration Value Register 0xE000E01C NOREF SKEW Reserved TENMS
Reserved 0xE000E020 - 0xE000E0FC
Set Enable Bits IRQ 0 to IRQ 31 0xE000E100 I2C1_EV TIM4 TIM3 TIM2 TIM1_CC TIM1_TRG_COM TIM1_UP TIM1_BRK EXTI9_5 CAN_SCE CAN_RX1 USB_LP_CAN_RX0 USB_HP_CAN_TX ADC1_2 DMA1_CH7 DMA1_CH6 DMA1_CH5 DMA1_CH4
Set Enable Bits IRQ 32 to IRQ 63 0xE000E104 Reserved DMA2_CH14_5 DMA2_CH13 DMA2_CH12 DMA2_CH11 TIM7 TIM6 UART5 UART4 SPI3 TIM5 SDIO FSMC ADC3 TIM8_CC
Set Enable Bits IRQ 64 to IRQ 95 0xE000E108 Reserved
Set Enable Bits IRQ 96 to IRQ 127 0xE000E10C Reserved
Set Enable Bits IRQ 128 to IRQ 159 0xE000E110 Reserved
Set Enable Bits IRQ 160 to IRQ 191 0xE000E114 Reserved
Set Enable Bits IRQ 192 to IRQ 223 0xE000E118 Reserved
Set Enable Bits IRQ 224 to IRQ 239 0xE000E11C Reserved
Reserved 0xE000E120 - 0xE000E17C Reserved
Clear Enable Bits IRQ 0 to IRQ 31 0xE000E180 I2C1_EV TIM4 TIM3 TIM2 TIM1_CC TIM1_TRG_COM TIM1_UP TIM1_BRK EXTI9_5 CAN_SCE CAN_RX1 USB_LP_CAN_RX0 USB_HP_CAN_TX ADC1_2 DMA1_CH7 DMA1_CH6 DMA1_CH5 DMA1_CH4
Clear Enable Bits IRQ 32 to IRQ 63 0xE000E184 Reserved DMA2_CH14_5 DMA2_CH13 DMA2_CH12 DMA2_CH11 TIM7 TIM6 UART5 UART4 SPI3 TIM5 SDIO FSMC ADC3 TIM8_CC
Clear Enable Bits IRQ 64 to IRQ 95 0xE000E188 Reserved
Clear Enable Bits IRQ 96 to IRQ 127 0xE000E18C Reserved
Clear Enable Bits IRQ 128 to IRQ 159 0xE000E190 Reserved
Clear Enable Bits IRQ 160 to IRQ 191 0xE000E194 Reserved
Clear Enable Bits IRQ 192 to IRQ 223 0xE000E198 Reserved
Clear Enable Bits IRQ 224 to IRQ 239 0xE000E19C Reserved
Set Pending Bits IRQ 0 to IRQ 31 0xE000E200 I2C1_EV TIM4 TIM3 TIM2 TIM1_CC TIM1_TRG_COM TIM1_UP TIM1_BRK EXTI9_5 CAN_SCE CAN_RX1 USB_LP_CAN_RX0 USB_HP_CAN_TX ADC1_2 DMA1_CH7 DMA1_CH6 DMA1_CH5 DMA1_CH4
Set Pending Bits IRQ 32 to IRQ 63 0xE000E204 Reserved DMA2_CH14_5 DMA2_CH13 DMA2_CH12 DMA2_CH11 TIM7 TIM6 UART5 UART4 SPI3 TIM5 SDIO FSMC ADC3 TIM8_CC
Set Pending Bits IRQ 64 to IRQ 95 0xE000E208 Reserved
Set Pending Bits IRQ 96 to IRQ 127 0xE000E20C Reserved
Set Pending Bits IRQ 128 to IRQ 159 0xE000E210 Reserved
Set Pending Bits IRQ 160 to IRQ 191 0xE000E214 Reserved
Set Pending Bits IRQ 192 to IRQ 223 0xE000E218 Reserved
Set Pending Bits IRQ 224 to IRQ 239 0xE000E21C Reserved
Reserved 0xE000E220 - 0xE000E27C Reserved
Clear Pending Bits IRQ 0 to IRQ 31 0xE000E280 I2C1_EV TIM4 TIM3 TIM2 TIM1_CC TIM1_TRG_COM TIM1_UP TIM1_BRK EXTI9_5 CAN_SCE CAN_RX1 USB_LP_CAN_RX0 USB_HP_CAN_TX ADC1_2 DMA1_CH7 DMA1_CH6 DMA1_CH5 DMA1_CH4
NVIC_Base
Clear Pending Bits IRQ 32 to IRQ 63 0xE000E284 Reserved DMA2_CH14_5 DMA2_CH13 DMA2_CH12 DMA2_CH11 TIM7 TIM6 UART5 UART4 SPI3 TIM5 SDIO FSMC ADC3 TIM8_CC
Clear Pending Bits IRQ 64 to IRQ 95 0xE000E288 Reserved
Clear Pending Bits IRQ 96 to IRQ 127 0xE000E28C Reserved
Clear Pending Bits IRQ 128 to IRQ 159 0xE000E290 Reserved
Clear Pending Bits IRQ 160 to IRQ 191 0xE000E294 Reserved
Clear Pending Bits IRQ 192 to IRQ 223 0xE000E298 Reserved
Clear Pending Bits IRQ 224 to IRQ 255 0xE000E29C Reserved
Active Bits IRQ 0 to IRQ 31 0xE000E300 I2C1_EV TIM4 TIM3 TIM2 TIM1_CC TIM1_TRG_COM TIM1_UP TIM1_BRK EXTI9_5 CAN_SCE CAN_RX1 USB_LP_CAN_RX0 USB_HP_CAN_TX ADC1_2 DMA1_CH7 DMA1_CH6 DMA1_CH5 DMA1_CH4
Active Bits IRQ 32 to IRQ 63 0xE000E304 Reserved DMA2_CH14_5 DMA2_CH13 DMA2_CH12 DMA2_CH11 TIM7 TIM6 UART5 UART4 SPI3 TIM5 SDIO FSMC ADC3 TIM8_CC
Active Bits IRQ 64 to IRQ 95 0xE000E308 Reserved
Active Bits IRQ 96 to IRQ 127 0xE000E30C Reserved
Active Bits IRQ 128 to IRQ 159 0xE000E310 Reserved
Active Bits IRQ 160 to IRQ 191 0xE000E314 Reserved
Active Bits IRQ 192 to IRQ 223 0xE000E318 Reserved
Active Bits IRQ 224 to IRQ 239 0xE000E31C Reserved
Reserved 0xE000E320 - 0xE000E3FC Reserved
Priority Bits IRQ 0 to IRQ 3 0xE000E400 RTC TAMPER P
Priority Bits IRQ 4 to IRQ 7 0xE000E404 EXTI1 EXTI0 R
Priority Bits IRQ 8 to IRQ 11 0xE000E408 DMA_CH1 EXTI4 E
Priority Bits IRQ 12 to IRQ 15 0xE000E40C DMA_CH5 DMA_CH4 DM
Priority Bits IRQ 16 to IRQ 19 0xE000E410 USB_HP_CAN_TX ADC1_2 DM
Priority Bits IRQ 20 to IRQ 23 0xE000E414 EXTI9_5 CAN_SCE CA
Priority Bits IRQ 24 to IRQ 27 0xE000E418 TIM1_CC TIM1_TRG_COM TIM
Priority Bits IRQ 28 to IRQ 31 0xE000E41C I2C1_EV TIM4 T
Priority Bits IRQ 32 to IRQ 35 0xE000E420 SPI1 I2C2_ER I2C
Priority Bits IRQ 36 to IRQ 39 0xE000E424 USART3 USART2 US
Priority Bits IRQ 40 to IRQ 43 0xE000E428 TIM8_BRK USBWakeUp RTC
Priority Bits IRQ 44 to IRQ 47 0xE000E42C ADC3 TIM8_CC TIM8_T
Priority Bits IRQ 48 to IRQ 51 0xE000E430 SPI3 TIM5 S
Priority Bits IRQ 52 to IRQ 55 0xE000E434 TIM7 TIM6 U
Priority Bits IRQ 56 to IRQ 59 0xE000E438 DMA2_CH4_5 DMA_CH3 DMA
Priority Bits IRQ 60 to IRQ 239 0xE000E43C Reserved Reserved Re
CPUID Base Register 0xE000ED00 IMPLEMENTER Arm is 0x41 VARIANT number Constant 0xF PAR
Interrupt control state register 0xE000ED04 NMIPENDSET Res. PENDSVSET PENDSVCLR PENDSTSET PENDSTCLR Res. ISRPREEMPT ISRPENDING VECTPENDING
SCB_Base
Vector Table offset Register 0xE000ED08 Res. Code(0) or RAM(1) TBLOFF vector table offset field. Offset from the bottom of the SRAM or CODE space
Application Interrupt and Reset Control 0xE000ED0C
…
…
see reference manual 0xE000EFFC
13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTLINESNUM Number of interrupt lines of device b00000=> 0…32, b00001 => 33-64, …, 0b00111 => 225…256
Reserved CLKSource TickINT Enable Systick control register
D Value (between 1 and 0x00FFFFFF) SysTick Interrupt and COUNTFLAG is active by counting from 1 to 0
Current Value
TENMS Reloadvalue for 10ms timing
DMA1_CH3 DMA1_CH2 DMA1_CH1 EXTI4 EXTI3 EXTI2 EXTI1 EXTI0 RCC FLASH RTC TAMPER PVD WWD enables the corresponding interrupt by stetting to 1
TIM8_TRG_COM TIM8_UP TIM8_BRK USBWakeUp RTCAlarm EXTI15_10 USART3 USART2 USART1 SPI2 SPI1 I2C2_ER I2C2_EV I2C1_ER
DMA1_CH3 DMA1_CH2 DMA1_CH1 EXTI4 EXTI3 EXTI2 EXTI1 EXTI0 RCC FLASH RTC TAMPER PVD WWD disable the corresponding interrupt by stetting to 1
TIM8_TRG_COM TIM8_UP TIM8_BRK USBWakeUp RTCAlarm EXTI15_10 USART3 USART2 USART1 SPI2 SPI1 I2C2_ER I2C2_EV I2C1_ER
DMA1_CH3 DMA1_CH2 DMA1_CH1 EXTI4 EXTI3 EXTI2 EXTI1 EXTI0 RCC FLASH RTC TAMPER PVD WWD 1 => pend Interrupt
TIM8_TRG_COM TIM8_UP TIM8_BRK USBWakeUp RTCAlarm EXTI15_10 USART3 USART2 USART1 SPI2 SPI1 I2C2_ER I2C2_EV I2C1_ER 0 => interrupt is not pending
DMA1_CH3 DMA1_CH2 DMA1_CH1 EXTI4 EXTI3 EXTI2 EXTI1 EXTI0 RCC FLASH RTC TAMPER PVD WWD 1 => clear pending Interrupt
TIM8_TRG_COM TIM8_UP TIM8_BRK USBWakeUp RTCAlarm EXTI15_10 USART3 USART2 USART1 SPI2 SPI1 I2C2_ER I2C2_EV I2C1_ER
DMA1_CH3 DMA1_CH2 DMA1_CH1 EXTI4 EXTI3 EXTI2 EXTI1 EXTI0 RCC FLASH RTC TAMPER PVD WWD Interrupt active flag
TIM8_TRG_COM TIM8_UP TIM8_BRK USBWakeUp RTCAlarm EXTI15_10 USART3 USART2 USART1 SPI2 SPI1 I2C2_ER I2C2_EV I2C1_ER 1 => Interrupt is active, pre-empted and stacked
PVD WWD 4 MSB are for the priority
RCC FLASH 4 LSB are for subpriorities
EXTI3 EXTI2
DMA_CH3 DMA_CH2
DMA_CH7 DMA_CH6
CAN_RX1 USB_LP_CAN_RX0
TIM1_UP TIM1_BRK
TIM3 TIM2
I2C2_EV I2C1_ER
USART1 SPI2
RTCAlarm EXTI15_10
TIM8_TRG_COM TIM8_UP
SDIO FSMC
UART5 UART4
DMA2_CH2 DMA2_CH1
Reserved Reserved
PARTNO Cortex family, version, M, family member Implementation defined revision number
RETTOBASE Res. VECTAKTIVE, currently running ISR
Reserved