Software Interrupts
INT nn instruction
INT 21H - DOS INTERRUPT
INT 10H – BIOS INTERRUPT
8086 Hardware
8086 Pinout MN/MX’ (33)
VCC (40)
GND (1, 20)
CLK (19)
AD0 – AD15
ALE (25)
A16/S3 – A19/S6
RD’ / WR’ (32, 29)
M/IO’ (28)
RESET (21)
NMI (17)
INTR (18)
DT/R’
DEN’
8086 microcomputer’s detailed block diagram:
Signal Activities on buses of 8086 microcomputer during
simple read and write operations:
Instruction Execution
Instruction Cycle
Machine Cycle
T states
CLK is crystal controlled clock sent to 8086 from an external
clock generator device such as 8284.
One cycle of this clock is called a state.
A state is measured as falling edge of one clock pulse to
falling edge of next clock pulse.
Different versions of 8086 have maximum clock frequencies
of between 5MHz and 10MHz, so the minimum time of one
state will be between 100nS to 200nS.
A basic operation such as reading a byte from memory or
writing a byte to a memory or port is called a machine cycle.
Memory Read Machine Cycle
In Read Machine Cycle:
During T1 asserts DT/R signal low to put data
buffers in receive mode.
( why buffers needed?)
When 8086 finishes using the data bus to send
address ( lower 16 bits), it asserts DEN low to
enable the data bus buffers
Data put on the data bus by an addressed port or
memory will then be able to come in through the
buffers to 8086 on the data bus.