FIB Specification

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					  Link Specification
  Trigger Input Data Link


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May 26th, 2006;revised July 9th, 2006
            Version 1.1

         Originator: J. Anderson
          Document #TBA
1.      GENERAL INFORMATION ........................................................................................................................... 4
1.1      SYSTEM INTRODUCTION ................................................................................................................................... 4
1.2      DESCRIPTION OF COMMUNICATIONS LINK & HOW IT FITS INTO THE SYSTEM ................................................... 4
   1.2.1   Overall Timing of the System ...................................................................................................................... 5
1.3      PHYSICAL IMPLEMENTATION ............................................................................................................................ 5
2.      THEORY OF OPERATION ............................................................................................................................. 6
2.1         OVERALL SYNCHRONIZATION OF DATA RELATIVE TO COMMAND LINK ............................................................. 6
   2.1.1       Specific timing of response to the Demand Slow Data command at the front end ..................................... 6
2.2         OVERALL TIMING CONSIDERATIONS THROUGHOUT THE GRETINA SYSTEM .................................................... 7
2.3         DATA STRUCTURE ............................................................................................................................................ 7
   2.3.1       Overall Structure of the data frame ............................................................................................................ 7
2.4         “FAST” DATA DISC BIT .................................................................................................................................... 8
2.5         “FAST” DATA ERROR BIT ................................................................................................................................ 8
2.6         “FAST” DATA PILEUP BIT................................................................................................................................ 9
2.7         “SLOW” DATA FLAG BIT.................................................................................................................................. 9
2.8         “SLOW” DATA WORD GRAY COUNT (BITS 12..9).............................................................................................. 9
2.9         “SLOW” DATA ACTUAL DATA BYTES............................................................................................................... 10
2.10        INITIALIZATION AND ERROR CONSIDERATIONS............................................................................................... 11
2.11        DC BALANCE ................................................................................................................................................. 11
3.      NOTES ON HIGH SPEED TRANSMISSION LINES ................................................................................. 12
3.1         LVDS SIGNAL LEVELS .................................................................................................................................... 12
3.2         PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS ..................................................................................... 12
                                  Change Log
1.  Fixed typos in section 1.2.1.
2.  Fixed typo in first sentence of 1.3.
3.  Need to cross-link to timing & control spec once numbers are issued.
4.  Typo (eight, should be eleven) fixed in 2.1
5.  Typo (four, should be five) fixed in 2.1.1
6.  Rewrote 2.2 to remove reference to GRETA per request
7.  Timing numbers in 2.1.1 adjusted due to change (5) above.
8.  Cleaned up format of table and 2.4 header. Incorporated the polarity bit function of bit 0
    as agreed, to match the way it‟s done in the timing and control link.
9. Modified table definition to allow last few words to be “DC Balance/Spare” rather than
    forced to be DC balance.
10. Added verbiage in 2.4.4 indicating that in words 17..20 the FLAG bit indicates whether
    bits 8..1 are Spare (FLAG set) or DC Balance (FLAG clear).
11. Matching verbiage in 2.4.6 about spare words.
12. Implied structure of data made explicit in 2.0, various other places.
13. Cleaned up the discussion of whether Crystal ID, Spare, Buffer count are sent every frame
    or not.
14. Redid the table of contents – note, section numbers have changed.
15. Modified Table 1 so that words 13 & 14 are the “spare”, 15..20 are the DC balance. Gray
    code notes modified to match.
16. Word three of Table 1 now explicitly named STATUS, not “Spare”.
17. Changed font size of footnote 2 for better page formatting.
18. Figure of connector pinout in Section 1.3 was not given a figure reference. Corrected.
    Text in section 2 modified as a result to reference adjusted figure numbers.
19. Table 1 shading modified to highlight gray code changes.
20. Rearrangement of which words are “spare” causes text changes in 2.7 to make it all
    match.
21. Bullet point 2 of section 2.8 modified to define that FLAG =1, bit 12 = 1 means hit
    pattern or spare data.
22. Section 2.9 reference that Crystal ID, Buffer count and Spare “may be transmitted”
    changed to “shall be transmitted” per discussion. “Spare” changed to “Status”.
    Explanatory text regarding digitizer response when there is no data amplified.
23. July 9th: Updated Figure 1 to newer version.
1. GENERAL INFORMATION
        This document describes the Trigger Data link used in the GRETINA data acquisition
system. The trigger system receives a continuous stream of data from various front end units.
Some portions of the data are continuously varying and need be processed in “real time”. Other
portions of the data are sent in bursts at fixed times, allowing for more complex processing of the
data to occur between bursts.
        This Trigger Data link is unidirectional, traveling “upward” from the front end data
acquisition units to the top of the hierarchical tree of trigger modules. A second unidirectional
link, the Trigger Timing and Control link, is described in a separate document.
1.1 System Introduction
       The GRETINA electronics system is described in GRETINA document #GRT-3-060412,
“GRETINA Electronics System”. That document contains an overall cartoon of the electronics
system, copied here as Figure 1.
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                                                                                                                                                                                                                                                                               Figure 1

1.2 Description of Communications Link & How it fits into the System
        The Trigger Data link receives information from all front end acquisition units. Data
from all front ends is required to be sent in bursts of 20 16-bit words using a commercial
SERDES (SERializer-DESerializer). Each front end unit is required to send a few bits of
information with every word informing the trigger of the current state of any discriminator
level(s) for fast triggering. When requested by the Trigger Timing & Control link, front ends
also send energy, hit pattern and associated timing information. Thus, two flows of data – “fast”
and “slow” – are intermingled within a single data link.
        Data from the front ends is sent continuously. The “fast” data is contained within a few
reserved bits of each data word. The “slow” data is contained within the rest of the bits in the
data words, but only appears on occasion, in response to commands. When “slow” data is not
being transmitted, fill patterns take up the bits allocated to “slow” data.
1.2.1 Overall Timing of the System
          The Trigger Data Link is presumed to run at a word rate of 50MHz (20nsec/word). The
Trigger Timing & Control Link demands a burst of “slow” data once every two microseconds.
Thus, the front ends will under normal conditions send four 20-word frames without “slow” data
and then one 20-word frame with “slow” data, synchronized to the commands received over the
Trigger Timing & Control link. There may have been no interactions within a section of the
detector in the last two microseconds since the last command from the trigger. The front end
shall still respond with the “slow” data in this situation, but shall report all zeroes for hit patterns,
energy and other measurements. This allows the trigger to continuously verify that the front end
is still communicating by verifying the header information in the “slow” data.
1.3 Physical Implementation
        The commercial chipset selected for this communications link utilizes the National
Semiconductor DS92LV18 as the SERDES, with the National Semiconductor DS90LV004 cable
driver/receiver providing the physical interface between the SERDES and the cable itself. Hard
metric (2mm pitch, IEC 61076-4-101) connectors and matching twisted pair cable sets with 100
ohm characteristic impedance are used throughout.
        The typical physical implementation of the Trigger Timing & Control link is intermingled
with that of the Trigger Data link. An obvious choice, as the normal system connections require
one of each between each front end board and the trigger system, it also makes sense in terms of
the connector design. IEC 61076-4-101 connectors utilize a 5-row (or 7-row) design that, at the
front panel, allows for insertion of dual-twisted-pair connectors using the following pinout:


                                            G     +     -     S     +     -    G
                                                            Figure 2

        In the cartoon of Figure 2, „G‟ indicates connection to ground, „S‟ to a shield common to
the two pairs, and the „+‟ and „-„ indicate the wire pairs themselves.1 This “wafer” is how the
cable assemblies are manufactured. Multiple wafers may be stacked upon each other to make
larger cables. In the case of this link, one twisted pair of each “wafer” may be used for the
Trigger Timing & Control link, and the other used for the Trigger Data link to make a most
convenient assembly. The usual front panel connector provides connectivity for 22 or 25 of these
“wafers” in one unit, with polarization and strain-relief clips part of the standard.




1 Whether “ground” and “shield” are the same or not depends upon the choice of wafer end on the cable, the choice of connector
used on the printed circuit board and the design of the circuit board itself. Before these specifications can be finalized, the
overall grounding and shielding specifications of GRETINA must be reviewed.
2. THEORY OF OPERATION
       The exchange of information between the front end module and the trigger system is
synchronous and the trigger system determines the synchronization. The trigger runs in a series
of two microsecond time-slices called “trigger cycles”. Once in each trigger cycle a command is
issued named Demand Slow Data. When this command is received each front end is required to
send as its next data frame one containing the “slow” information. The timing interplay between
the Trigger Data Link and the Trigger Timing and Control Link is such that the front ends send
exactly five data frames over the Trigger Data Link every “trigger cycle”. After sending the data
frame containing the “slow” data in addition to the continuously transmitted “fast” data in
response to the Demand Slow Data command, the front ends will have time to send exactly four
more frames that contain only “fast” data.
2.1 Overall synchronization of data relative to command link
        The expectation is that front ends will transmit their data with data frame boundaries a
fixed number of word clocks after the end of a command frame boundary. A front end is
expected to begin transmission of the requested data frame type beginning 220 nsec (eleven clock
ticks) after the beginning of the command frame in which the frame type is requested. This
implies and assumes that all front ends are synchronous devices that operate from the clock
received over the Trigger Timing & Control link.
2.1.1 Specific timing of response to the Demand Slow Data command at the front end
         Assume a Demand Slow Data command is issued by the trigger beginning at time Ttrig=0.
It will take five words to send that command. The first will be serialized starting at time Ttrig=0
and ending at time Ttrig=20nsec. The last word of the command will be completely transmitted to
the front end at Ttrig=100nsec, plus the inherent delay of the SERDES, plus the delay of the cable
connection. Since this delay may vary slightly from front end to front end, we shall define the
clock edges of the SERDES receiver in the front end as occurring at times Tfe=0, 20, 40, 60, 80
and 100nsec. The front end shall use the following clock tick (Tfe=120ns) to decode the
command. The next four clock edges (Tfe=140ns, 160ns, 180ns and 200ns) may be used to
prepare the data frame. The first word of the data frame shall be loaded into its SERDES on the
next clock edge (Tfe=220ns, or the sixth edge following the receipt of the last word of the
Demand Slow Data command). “Slow” data is then sent for 20 ticks of the clock following the
structure defined below. Figures 3 and 4 provide an overall sketch of the process.
       Note that this timing description has only to do with the “slow” data that is presented in
response to commands. The “fast” data is always loaded as promptly as possible and sent with
minimal, consistent delay.
                  Figure 3 – overall timing of command reception and response




                         Figure 4 - continuation of response from Figure 3


2.2 Overall timing considerations throughout the GRETINA system
        Presuming an inherent SERDES & cable delay in both directions of up to 100nsec, plus
the allowed 200nsec for front-end turn-around, the receipt of “slow” data by the trigger may be
delayed 400nsec or so from issuance of the Demand Slow Data command. Assuming another
100nsec SERDES delay in each communications link between boards in the Trigger itself plus
allowing for a few clocks of internal delay in each trigger module, it is likely that a full
microsecond will elapse before the “slow” data has all been collected by the top-most trigger
module. Still, this is small relative to the size of the buffers in the front end digitizers; it is not
expected to cause any issues.
2.3 Data Structure
        The Trigger Data consists of an endlessly repeating series of data frames. Each data
frame is composed of 20 eighteen-bit words, following the format shown in Table 1. Shaded
cells in Table 1 indicate specific patterns of interest. These are related to the discussions in the
following subsections and are highlighted simply for the ease of the reader.
2.3.1 Overall Structure of the data frame
        Bit 17 is fixed to act as guard bits for the clock transition. Bits 16, 15 & 14 form the
“fast” data; they are continuously updated every word irrespective whether a Demand Slow Data
command is being processed or not. The remaining bits (13..1) are the “slow” data. Each bit
group is detailed below. Exactly as was done for the Trigger Timing & Control link, bit 0 is a
polarity bit that indicates whether the data in bits 16..1 is presented as “true” or “inverted” data.
This allows the sender of data to manage the bit disparity on a word-by-word basis to maintain
the DC balance of the transmission line.
Bit     17      16       15         14       13     12 11 10 9                   8..1            0
Word            By-sample fast trigger bits   Flag   Word Grey Count   “Slow” data
1       0       Disc.   Error     Pileup      1      0   0    0    0   Crystal ID                T/F
2       0       Disc.   Error     Pileup      1      0   0    1    0   Buffer Count              T/F
3       0       Disc.   Error     Pileup      1      0   0    1    1   Status                    T/F
4       0       Disc.   Error     Pileup      1      1   0    1    1   Hit Pattern A             T/F
5       0       Disc.   Error     Pileup      1      1   0    0    1   Hit Pattern B             T/F
6       0       Disc.   Error     Pileup      1      1   1    0    1   Hit Pattern C             T/F
7       0       Disc.   Error     Pileup      1      1   1    1    1   Hit Pattern D             T/F
8       0       Disc.   Error     Pileup      1      1   1    1    0   Hit Pattern E             T/F
9       0       Disc.   Error     Pileup      1      0   1    1    0   Timestamp (low byte)      T/F
10      0       Disc.   Error     Pileup      1      0   1    1    1   Timestamp (high byte)     T/F
11      0       Disc.   Error     Pileup      1      0   1    0    1   Central Contact Energy    T/F
                                                                       (low byte)
12      0       Disc. Error       Pileup      1      0   1    0   0    Central Contact Energy    T/F
                                                                       (high byte)
13      0       Disc.   Error     Pileup      1      1   1    0   0    DC Balance /Spare         T/F
14      0       Disc.   Error     Pileup      1      1   0    0   0    DC Balance /Spare         T/F
15      0       Disc.   Error     Pileup      0      0   0    0   0    DC Balance Word           T/F
16      0       Disc.   Error     Pileup      0      0   0    0   0    DC Balance Word           T/F
17      0       Disc.   Error     Pileup      0      0   0    0   0    DC Balance Word           T/F
18      0       Disc.   Error     Pileup      0      0   0    0   0    DC Balance Word           T/F
19      0       Disc.   Error     Pileup      0      0   0    0   0    DC Balance Word           T/F
20      0       Disc.   Error     Pileup      0      0   0    0   0    DC Balance Word           T/F
              Table 1 – Trigger Data Link word format (for frame containing slow data)

2.4 “Fast” data DISC bit

       The DISC bit provides the current state of the leading-edge discriminator for the central
contact of the germanium crystal (as sampled every 20nsec – once per word). Each front end
device asserts the DISC bit to „1‟ when the input energy of the crystal transitions above the
programmable threshold and holds the bit at „1‟ for a programmable amount of time afterwards.
The holding of the DISC bit for a programmable time is critical – this allows for the formation of
multiplicity triggers over the length of the interaction period. Within the trigger system, the
number of DISC bits that are set in any 20nsec period is evaluated against a programmable
threshold. If enough DISC bits are set, a multiplicity trigger occurs.
2.5 “Fast” data ERROR bit

        The ERROR bit is set to „1‟ if the front end internally determines it is in an error state;
additionally, the default of any front end should be to hold the ERROR bit set at initialization and
only release it when correct operation is achieved. If the ERROR bit is set in any given front
end, the trigger may, in real time, internally mask the DISC bit to „0‟ until the ERROR bit is
cleared to avoid false triggering. The trigger may pass on the ERROR bit to the slow control and
monitoring system; this system may react to the ERROR bit by issuing a reset.
2.6 “Fast” data PILEUP bit

         The PILEUP bit is set to „1‟ if two interactions occur within the same crystal center
contact too quickly; the amount of time is assumed to be programmable at the front end. If the
PILEUP bit is set in any given front end, the trigger may, in real time, internally mask the DISC
bit to „0‟ until the PILEUP bit is cleared to avoid false triggering. The trigger may pass on the
PILEUP bit to the slow control and monitoring system; this system may take statistics on the
occurrence of pileup conditions. It is assumed by the trigger that a PILEUP bit will always clear
itself, given enough time.
2.7 “Slow” data FLAG bit

        The FLAG bit is set to indicate that the rest of the “slow” data field in the current word
has been sent in response to a Demand Slow Data command. The front end shall set this bit to
„1‟ for words 1,2 & 3 of the frame in all data frames; if the front end digitizer has energy and hit
pattern data to send, then the FLAG bit shall also be set for words 4 through 12. The FLAG bit
shall always be set to 0 in words 15 through 20 of the data frame, irrespective of whether the
front end digitizer is responding to a Demand Slow Data command or not. The FLAG bit, if set
in words 13 or 14, shall indicate that the “slow” data section of those words contains spare or
additional information (function to be determined at a later time). If the FLAG bit is clear in
words 13 or 14, the “slow” data section of those words shall be assumed to be additional DC
Balance values.
2.8 “Slow” data Word Gray Count (bits 12..9)
       The Word Gray Count, in conjunction with the FLAG bit, provides a sanity check and
optional address information for the actual “slow” data found in bits 8..1. Note that bits 12 & 11
provide simplified decoding information indicating the type of “slow” data present in each word:
              FLAG = 1, bits 12,11 = 0,0 indicates identification information.
              FLAG = 1, bit 12 = 1 indicates hit pattern or spare information.
              FLAG = 1, bits 12,11 = 0,1 indicates energy/pattern information.
              FLAG = 0 indicates filler words (no “slow” data relevance).
        The trigger system will look for the word with FLAG = 1 and bits 12..9 equal to 0000 as
the first word in the data frames and will lock onto that pattern for synchronization. This
synchronization requirement is why the FLAG bit is always set in the first three words of all
frames.
        The Word Gray Count must be sent in words 1, 2 and 3 of all data frames. The front end
digitizer may send the Word Gray Count in words 4 through 12 of all data frames, but is only
required to send the Word Gray Count in the data frames sent in response to the Demand Slow
Data command.
2.9 “Slow” data actual data bytes

        The Crystal ID, the Buffer Count and the Status byte shall be transmitted every data frame
to provide a data consistency check. The other hit pattern, timestamp and energy values are
transmitted only in the one out of every five data frames sent in response to the Demand Slow
Data command, and only if the front end digitizer has data to send. If there is data to send, then it
shall be sent in the order specified in Table 1.
        In the case where a Demand Slow Data command has been received but there is no data
to send, the front end digitizer may fill the “slow” data byte of words 4 through 12 with any data
pattern desired so long as the FLAG bit is set to zero. If the FLAG bit is „1‟ but there is no data
to send, then the front end digitizer must fill the “slow” data byte of words 4 through 12 with all
zeroes. The conflicting desires of DC balance and explicit representation of no data using zeroes
will have to be resolved as the system evolves. Use of the FLAG bit as specified here allows for
either decision.
        In the 80% of data frames that are not sent in response to the Demand Slow Data
command, words 4 through 12 of may be filled with any data desired. It is recommended that the
byte be filled with varying values (calculated on the fly) that minimize the total disparity of all
data sent within the data frame. In similar vein, the “slow” data byte in words 17 through 20 of
the frame are explicitly reserved for DC Balance Words that contain arbitrary bit patterns
calculated on an as-needed basis to minimize total bit disparity across the data frame. The
“slow” data byte in words 13 through 16 is defined as “DC Balance/Spare” to allow for future
expansion. The interpretation of the “slow” byte in words 13 through 16 is tied to the FLAG bit
as described in section 2.4.4 above.
2.10 Initialization and Error Considerations
        As specified in the Trigger Timing & Control link document, initially no Demand Slow
Data commands will be issued in response to system startup or reset. Only Sync and End-of-
Cycle commands are issued at this time. With no Demand Slow Data command to synchronize
to, the Trigger Data Link must have another synchronization mechanism. To insure clean
startup, the Trigger Data Link shall be further constrained to respond to the Sync command by
issuing a data frame without “slow” data with identical timing requirements to those imposed
upon the response to the Demand Slow Data command enumerated above.
         The front end digitizer modules shall maintain a simple word counter initialized by the
Sync command that monitors when the Demand Slow Data command is received. Under all
normal operating conditions, the Demand Slow Data command should arrive at a fixed delay, an
integer number of Trigger data frames, relative to the Sync. Should an out-of-time Demand Slow
Data command arrive, the ERROR bit shall be set and shall persist until the system is re-
initialized.
2.11 DC Balance
        The front end digitzers are assumed to calculate the disparity of each data frame‟s words
by counting how many 1s and 0s are in each word. All data frames contain many spots where a
DC Balance Word may be inserted. The DC Balance Words are expected to compensate for the
disparity engendered by the required data in each word such that the frame, overall, is DC
balanced. This is considered sufficient to insure robust data transmission. The format of the DC
Balance byte, when generated, shall be a string of continuous 1s or 0s, as required, starting with
bit 1 and proceeding upwards towards bit 8. Once the requisite number of 0s or 1s is packed, the
remaining bits shall be filled with alternating 1s and 0s until the word is full.
3. Notes on high speed transmission lines
        The Trigger Timing & Control link is a high speed transmission line. With a bit rate of
1Gbps and edge transition times in the 100psec range, very careful attention to high speed
signaling concerns is paramount. This section will provide some basic information to assist
designers and users in coping with these concerns.
3.1 LVDS signal levels
       The chipset selected for the Trigger Timing & Control link uses LVDS (Low Voltage
Differential Signaling) technology. This circuit architecture uses current steering to create 1s and
0s by driving a current one way or the other in a pair of conductors, developing voltage across a
terminating resistor at the end of the line. The standard has been extended to use in bussed
applications, but it was originally designed for, and it still best used in, point-to-point
applications such as the Trigger Timing & Control link.
       In normal usage the transmission line is chosen to have an odd-mode characteristic
impedance of 100 ohms, and a 100 ohm resistor is used across the conductor pair as the
terminator. With typical LVDS currents (5mA), this generates a differential voltage of about 500
millivolts at the input of the receiver.
3.2 Printed Circuit Board layout considerations
         The high speed of the system requires that differential traces on printed circuit boards be
very well matched. Vias and package pins have to be viewed as potentially self-resonant circuits.
Even the mismatch in the length of right-angle connector pins becomes a concern; this means
that if the „blue‟ conductor of a twisted pair in board „a‟ has the longer connector pin path, the
other board at the other end of the line has to be designed such that the „red‟ conductor of the
twisted pair gets the longer path. Boards cannot be developed in isolation – the designers at both
ends of the cable must work together. Chapter 3 of National Semiconductor‟s “LVDS Owners
Manual” (found at http://www.national.com/appinfo/lvds/files/lvds_ch3.pdf) is a good general
reference. If a copy of the MECL System Design Guide from Motorola can be found, it is also a
good reference work, especially chapter 7.

				
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