Computer Design I
Professor Sharif, Ph.D.
FINAL COMPUTER PROJECT
Table of Contents:
EXPERIMENT ABSTRACT ..........................................................1
HARDWARE DESIGN CONSIDERATIONS/SPECS ..................3
THE 8086 PROCESSOR .................................................................6
LCD DISPLAY: INTERFACING
LCD DISPLAY: INITIALIZING
LCD DISPLAY: TIMING
SOFTWARE DESIGN PRINCIPLES .............................................4
SOFTWARE / ASSEMBLY............................................................5
ASSEMBLY: INITIALIZING THE SEGMENTS
MAIN PROGRAM ..........................................................................6
SYSTEM CONTROL PROCEDURES
PROCEDURE CALLS ....................................................................7
INSTRUCTOR SIGN-OFF SHEET
This is a computer design course, and often in design courses, the students are asked to build something
based on their own individual designs. More bluntly speaking, the students become more than just
monkeys wiring circuitry for the instructor. The emphasis in this course, and equivocally this project, is
on the design of the system. After all, in this day and age, all the time is spent in the design process. It is
important that each of the students use their own methods of meeting the design requirements. Generally,
the designs are scarcely limited to simple minimum design requirements. In this case, there were only a
handful of these requirements:
Intel® 8086 System
64k RAM / 64k ROM
(2) Output ports
(1) keypad (minimum 20-key)
(1) LCD display (minimum 16x4)
For this project, I saw an entire realm of possibilities. One avenue I sought was incorporating a pair of 7-
segment displays. Since the two output ports were required for the course, I set up two ports for a series
of 16 LEDs, and used a third port for the 7-segment displays. This is discussed further in this report, and
added very little design time to the mix, because it operated on the exact same principles as my initial
The processor used in this experiment was Intel®‟s very own 8086. Released in 1978, this processor was
the first step into an entire realm of computing possibilities. Much of the architecture used internally in
this processor are still used in high speed processors today. This is an excellent processor to use to give
an introduction to the intricacies of processing technology and its fundamentals. The 8086 has a 16-bit
multiplexed ADDRESS/DATA bus, with an additional 4-bit multiplexed ADDRESS/STATUS bus,
yielding a total of 20 ADDRESS lines and 16 DATA lines.
The memory requirements for this project were to make available 64k (65536) byte-size memory
locations. Since we were using the 8086 processor (in the minimum mode), the memory most suitable
was two separate 16k memory banks. This was accomplished by setting an EVEN and ODD bank for
both RAM and ROM. This made the MEMORY MAP design simple, because the difference of FFFF
and 0000 is 64k; therefore, the logical SEGMENT address corresponded nicely with the RAM and ROM
The keypad used was a standard 20-key keypad. The interface to this device was 9 pins: 5 pins
corresponding to the 5 rows, and 4 corresponding to the 4 columns. These form a grid below the keys,
and connections are made across rows and columns when buttons are pressed. This is explained in more
detail inside this report.
The LCD provides the graphical user interface necessary for the average person to use this device. The
LCD display used is 20x4 (a bit larger than the required 16x4) with NO LED backlight. The display is
operated in Character Mode for this project, allowing simple ASCII-to-display conversion, and VERY
A technique used in this project for interconnection of these devices is wire-wrapping. Wire wrapping is
exactly what it‟s name implies. Small wires and special “long-post” sockets are used to make this
technique possible. The wires are stripped, and „wrapped‟ around these long posts for a clean, solid,
robust connection. Since these wires are very small, the 20 address lines and 16 data lines can be sent to
several different memory devices without occupying a significant amount of space. This is an excellent
learning tool as well, because the wrapping can be easily removing by reversing the wrapping procedure.
Much time spent on this project is in the writing and debugging of Intel Assembly code. Since Assembly
is one-to-one with machine code, the instructions are very low-level and very high speed. This assembly
code is stored into the ROM devices, and essentially guides, or „instructs‟ the processor. Once the
hardware is built, the software must be written to control it.
Programmable Logic Devices
PLDs are used in this project to control the logic for the processor/memory glue logic, and very possibly
other reasons. The GAL22V10-10LP and GAL20V8B-15LP logic devices are easily programmed using
VHDL and the DATAMAN Universal programmers available in the lab. In this project, two
GAL22V10B-25LP ICs were used to decode the 7-segment displays. These are extremely versatile
devices, and open an entire window of opportunity for creative inspiration.
Logic Analyzer 1693A
Because of the incredible speed (relative to human perception) of the internal circuitry of the processor,
the only way to successfully monitor its activity is through the logic analyzer. This device is very handy
in troubleshooting a defective circuit, or a misfiring chip select line. These devices capture data at a very
high rate to give the user a one-on-one relationship with the processor.
EconoROM III ROM Emulators
The EconoROM III Emulators, equipped in the laboratory, are used to simulate ROM ICs in the processor
circuit. These devices are able to be programmed with the provided computer software, and emulate a
ROM chip. These are very important because they offer a fast and easy way to program and reprogram
the data in the ROM chips without having to insert and remove ROM chips, and erase them in the 20-
minute UV eraser. After all, programming the ROM chip and getting it right the first time does not
happen very often! The EconoROM allows us to finish the software design before “hard-programming”
the ROM chips.
OrCAD Schematic Capture
This CAD suite is very very useful in the design of the hardware. This software environment provides
schematic symbols for almost every conceivable electronic device, and allows for the virtual
interconnection and simulation of these components. This allows for the user to „test‟ the circuit before
any hardware is physically wired. This way, any bugs in the hardware can be ironed out using this
fabulous design tool.
HARDWARE DESIGN CONSIDERATIONS/SPECIFICATIONS
Since the design requirements for this project included 64k of RAM, 64k of ROM, and 2 I/O ports, along
with the keypad and LCD display, there is quite a bit of hardware design necessary to make these devices
interact with each other. One essential aspect of coordination in a microprocessor circuit is timing. The
8086 processor has a specific timing scheme (or protocol) that it uses for each of it‟s instructions. For
instance, when a MOV instructions requests data from memory, the processor sends an ALE signal to
announce that the multiplexed ADDRESS/DATA bus contains ADDRESS information. Likewise, when
the processor feels enough time has elapsed to latch that ADDRESS and retrieve memory cells, the
processor sends a DEN signal to announce that bus contains DATA information (the data at the memory
location). This is all coordinated using a timing diagram.
Timing Diagrams are very useful waveforms to the designer. This is because the external (not inside the
processor) circuitry has to be designed to use this information in an effective way to cooperate with the
processor. The following is an example of a timing diagram for a MEMORY READ instruction:
TIMING DIAGRAM PLEASE
As can be seen, these are the requirements of our system. We must construct the system that latches that
memory address, and retrieves/latches that data information, so that the processor can use it!
BUS LATCHING / DEMULTIPLEXING
This sounds like a complicated procedure—but it is not. The only piece of hardware necessary for the
demultiplexing of the ADDRESS/DATA bus is a set of D Flip Flops. These can be purchased in octal
DIP form, in the case of the 74HC573 and 74HC244. These are CMOS chips, so they are a little more
susceptible to spurious electrostatic charge—it can damage the chips. Now this handles the ADDRESS
bus, but the DATA bus needs something else—something that can work bidirectionally—because
remember, the data can be received on this bus, just as it can be sent. This calls for the 74HC245. This is
an octal bidirectional latch. Two of these will take care of the data bus. As the schematic for the
microprocessor shows, the outputs of these devices contain the demultiplexed ADDRESS and DATA
Since the Addressable Memory is 64k for both RAM and ROM, it requires 16 bits of internal addressing
on the memory devices. These leaves ADDRESS lines A19-A16 to be used to select the appropriate
memory chip. These lines are called CHIP SELECT lines, and they are generated using the manipulation
of logic on these 4 address lines. Now, an important realization is that this 64k of memory is split into 2
separate chips, an ODD and an EVEN bank. Fortunately, since the width of the data bus is 16 bits, and
the output of each memory device is 8 bits, the EVEN bank is interconnected to DATA lines D0-D7,
while the ODD bank is interconnected to DATA lines D8-D15.
Furthermore, when a MEMORY WRITE occurs (in RAM only—ROM is read-only), the decoding logic
must signal the appropriate bank of memory to write; therefore, the A0 bit is used in cooperation with the
BHE output line from the processor( along with the WR- signal ) to select the correct memory device. All
of this decoding logic is programmed into the PLD. The GAL22V10B-10LP is the appropriate logic
device for this purpose.
Because all of the I/O mapping in this project was done on the memory map, the I/O ports, as well as the
keypad, and LCD display were all mapped using similar decoding logic. The I/O map was not used at all
in my design.
LED (Light Emitting Diode) BARS
The LED bars are interfaced to the processor using two important ideas; one, a buffer must be used to
store the data displayed indefinitely by the LED bars, and two, an enable line must be used to latch the
data from the DATA bus to this buffer. These two needs can be satisfied, once again, with the 74HC573
Octal Latch. This chip has an active high LATCH ENABLE input that causes the incoming data to
„latch‟ to the output. There is also an active low OUTPUT ENABLE input that can be tied to ground,
such that the LEDs are always showing the condition of the output port data. There must be a chip select,
addressed on the system ADDRESS MAP, that is decoded in the glue logic that enables this latch to
From a design standpoint, one has two options in reading from a keypad: Use a predistinguished, multi-
functional keypad controller, or design your own. The 8279 is a very valuable chip to have, because it
has in it a memory buffer, status register, LCD controller, and many other functions that make controlling
a keypad simple. I declined to use this shortcut in my project, to further welcome the challenges that
come with learning to design digital circuitry.
Because I chose not to use the 8279 interrupt controller, a serious look into the functionality of a keypad
was required. The keypad‟s operation is not particularly what one might think. The keypad is wired as
Figure 2. Keypad Hardware Structure
When any one of the switches is pressed, a short circuit is created between the Row and Column of the
respected button. Using this logic, the keypad circuit must be designed in such a way that the processor
must write to one dimension of the grid, and read from the other. The circuit shown here was used to
build such a circuit.
Figure 3. Keypad Interfacing Example.
As shown above, the scan of the keypad for pressed keys is a slightly involved process. It involves
writing a series of sequences (one line LOW, the rest HIGH) to one output port, and reading the data from
the input port. This value read in can then be compared to determine which button is being pressed.
One significant problem with setting up your own personal keypad controller is key bounce. The problem
is this: when the user presses a key, the switch contacts crossing the rows and columns do not make an
immediate short. In fact, the switch settle time is often several hundred clock cycles, during which the
logic levels are indeterminate. This activity is called switch bouncing, and can be handled using a
debounce technique. Inside the 8279 keypad controller is hardware debounce circuitry, in the situation
presented here, a software debounce routine must be written to control this undesirable activity.
In order to use the LCD display, it must be initialized. This is because the functions of the LCD stretch
far beyond our use in this project. For one instance, the LCD has a graphical mode, used to display
graphical data by offering pixel-by-pixel addressing—we are using the character mode, which uses 40x2
character addressing and an assortment of pre-determined characters(mostly ASCII equivalent).
The LCD panel that we are using in this project has the built in controller circuitry—and therefore, takes
instructions much like the 8086 microprocessor does—only much slower. The display requires a series of
instructions, with adequate interim delay times, to initialize. This can all be implemented using software
written in assembly.
It‟s important to understand what your hardware is supposed to be doing. It‟s also important to
understand the reasons why it‟s not doing it. Sometimes, the possibility could be, that the hardware is
simply not functioning properly internally. Certainly devices of the CMOS nature have the risk of
electrostatic interference, and RAM chips have been proven to be bad on occasion.
THE 8086 PROCESSOR: INTERFACING
The Intel® 8086 microprocessor has two different modes of operation: minimum mode and maximum
mode. For this project, we will use the processor in its minimum mode of operation. This simply means
that the processor is a stable system on its own, where in maximum mode, the processor uses a co-
processor to handle many of its functionality. The way that the processor determines its mode of
operation is through its input pin 33 (MN/MX-). With this in mind, the pinout of the 8086 in minimum
mode is shown here:
Figure 4. The 8086 microprocessor pin-out
Notice that the lines shown in red indicate the multiplexed ADDRESS/DATA bus. The lines in purple
show the CONTROL bus, and lines in black show the processor command pins. Notice the double GND.
It is important that both GND pins are grounded. This caused an early error in my design when one of
these pins was floating (not connected).
INTERFACING THE 8284 CLOCK CHIP
The timing controller used to synchronize the entire computer system is the 8284 clock chip. This chip
has many functions. First, it can choose between a timing crystal or an external oscillator device. In this
project, an external crystal oscillator of 12MHz was used as a frequency input to the 8284 clock chip.
The 8284 clock chip then processes this frequency input and outputs three separate clock signals: CLK,
which operates at 1/3 the external input frequency with a 33% duty cycle, PCLK, which operates at ½ the
CLK signal with a 50% duty cycle, and OSC, which operates tandem with the external frequency input.
CLK is the signal we will use to controller our 8086 microprocessor, and it will run at approximately
This 8284 clock chip is also responsible for synchronizing the active low RST- input with the processor
as an active high output RESET (8086 pin21 above). This is shown on the schematic on the following