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					    Department of Electronics Engineering Institute of Electronics


Title : Study on Optoelectronic and Quantum Device
Principal Investigator : Chun-Yen Chang
Sponsor : National Science Council

Keywords :δ-Doped Gainp, Strained Quantum Well, Electron-Beam Direct Writing,Gainasp,

             Gan
By utilizing LP-MOCVD, this three-years project is aimed at the study and development of the
optoelectronic and quantum devices. The research is divided into three main items.

Item 1:Growth and chacterization of δ-doped GaInP material and its device applications.

The first year: Investigation of material quality and structure characterization

   (1)Material growth and characterization of δ-doped GaInP by LP-MOCVD.

   (2)Growth and characterization of InGaAs quantum well.

   (3)Growth and characterization of δ-doped GaInP/GaAs HEMT and

GaInP/InGaAs pseudomorphic HEMT.
The second year: Device fabrication
   (1)Fabrication of submicron devices, including etching, ohmic contact and electron-bean
   direct writing.
   (2)Device characterization and modeling.
   (3)Application of GaInP buffer layer.
The third year:Parameter optimization and reliability study
   (1)Fabrication of the whole 2-inch-wafer devices.
   (2)Improvement of the device high-temperature performance.
   (3)Optimization of process parameters and analysis of device reliability.
Item2:A1-exclusive GaInP/InGaAs strained quantum well laser
The first year:
   (1)Growth of GaInP material and impurity doping.
   (2)Growth and characterization of InGaAs/GaAs quantum well.
   (3)Growth and characterization of GaInAsP material.
The second year:
    (1)Fabrication of low threshold current and high quantum efficiency
InGaAs/GaAs/GaInP quantum well laser.
The third year:
    (1)Fabrication of low far-field angle InGaAs/GaAs/GaInP quantum well laser.
    (2)Study of the optimization the far-field angle and threshold current of
InGaAs/GaAs/GaInP quantum well laser.
Item 3: Study of the short-wavelength material and its devices.
The first year: Design of two-flow reactor and growth of undoped GaN.
The second year: Growth of n-and p-type GaN, InGaN, and A1GaN.
The third year: Development of the process parameters, including the RIE
and ohmic contact metalization.
NSC86-2215-E009-018
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Title : The Development of Si/SiGe Material and Devices
Principal Investigator : Chun-Yen Chang
Sponsor : National Science Council

Keywords :


      The goal of this project is to study the growth mechanism, doping properties, material
properties and physical phenomena of the Si and SiGe. Using SIMS, X-Ray Diffraction, RBS,
TEM, SEM, AFM and FTIR ets., the material and physical characteristic of the Si/SiGe quantum
will and superlattice structures will be investigated. On the basis of these results, will fabricate
the short channel Si/SiGe MOSFET's. The innovative idea of substrate engineering will be
implemented.
      The characteristics of these new devices will be evaluated with subsequent electrical
measurements. Meanwhile, we will develop SiGe HBT suitable for wireless communication and
implement SiGe HMIC(Hybrid Microwave Integrated Circuit). After completion, a SiGe RF IC
will be made in Taiwan for the first time.
      After finishment of this project, we will obtain a complete understranding of the Si/SiGe
material and applications for short channel MOSFET and HBT.
NSC86-2215-E009-019
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Title : Short Channel Si/SiGe MOSFET's
Principal Investigator : Chun-Yen Chang
Sponsor : National Science Council

Keywords :


       The goal of this project is to study the low temperature Si and SiGe growth technology for
the applications on the short channel MOSFETs. The innovative idea of substrate engineering
will be implemented. The characteristics of these new devices will be evaluated with subsequent
electrical measurements.
      We plan to promote this project during 3 years. In the first year, the basic processing data
of n-type and p-type epi-layers will be built and the characteristics of these devices will be
simulated by the 2-D device simulator, MEDICI. Masks of device process will be also
manufactured. Because the Si/SiGe film is sensitive to the process temperature, the low
temperature process must be performed. It takes much time to develop the low temperature
processes. We plan to finish the process development for the first two years. The fabrication
process include several important module technologied, such as, the isolation technology, the
low temperature oxide growth , and the Source/Drain junction formation etc., In the second year,
except developing the important module technologies, we want to obtain an optimized device
fabrication methodology and fabricate short channel devices. In the last year, we will focus on
the improvement of the device performance. Extracting and measuring the device parameters
will be performed. Meanwhile, the reliability of these new devices will be studied.
NSC86-2215-E009-021
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Title:A Research Program on Micro-electromech-anical Components and Systems

Principal Investigator:Kow-Ming Chang

Sponsor:National Science Council

Keywords:MEMS, Micromachining, Sensors, Actuators, Microdevices



      This joint project is an interdisciplinary research program to work out
Micro-Electro-Mechanical Systems (MEMS) related materials technology, processing
technology , devices structure design, testing technology and interface circuit design. The
researchers in this proposal are from different research fields in the university ,and are competent
in electronics materials ,physics, mechanics and applied chemistry. The subprojects proposed
are :
Subproject 1. Capacitive sensors and actuators
Subproject 2. Materials and process development and research
Subproject 3. Piezoresistive force sensors
Subproject 4. : Micro-machining in optical sensors and high speed devices
Subproject 5. : Si-Based Integrated ARROW-Type Waveguide Chemical And
Biochemical Sensors
Subproject 6. Wettability, internal stress, adhesion and mechanical properties of various thin
films on Si wafer
Subproject 7. : Design and Fabrication of Thermal-Driven Compliant Micromechanisms
Subproject 8. : The Design, Fabrication And Test Of Micro-Heat Exchanger
Subproject 9: Micro-Hall Sensor Array
Subproject 10: Si-Based Integrated Optical Fiber Coupled Pressure Sensors
NSC86-2221-E009-037
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Title: Capacitive Microsensors and Microactuators Device Structure Design and Fabrication

Principal Investigator:Chang, Kow-Ming

Sponsor:National Science Council

Keywords:MEMS, Microsensors, Microactuators, Microdevices



       This project is an interdisciplinary research program to work out silicon-based capacitive
microsensors, microactuators and Micro-Electro-Mechanical Systems (MEMS). The researchers
in this proposal are from different research fields in the university, and are competent in
electronics materials, physics, mechanics and applied chemistry. This project proposed is :
Subproject 1 : Capacitive microsensors and microactuators device structure design and
fabrication a. Sensors - high sensitivity sensors for medical hearing aid, air flow control etc.. b.
Actuators - gas and fluid flow valves and switches as well as optical communication systems. c.
Self calibration sensors and actuators with sensors feedbacks. d. Surface micromachined sensors.
This subprogram consists of three phases, the phase 1 is to establish bulk micromachined
microsensor technologies and fabrication, and microsensor structure design with feedthrough.
phase 2 continues on the device fabrication and evaluation capability, and surface
micromachined microsensor design development and IC with sensor integration. Finally, in
phase 3 the actuators and surface micromachined devices will be fabricated and studied. The
results of these experimental investigations hopefully provide high-performance microsensors,
microactuators and MicroElectro-Mechanical Systems (MEMS) technologies to electronics
industry.
NSC86-2221-E009-038
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Title:ULSI Devices Related Refractory Metal and Dielectrics Technologies(II)

Principal Investigator:Chang, Kow-Ming

Sponsor:National Science Council

Keywords:



       Aluminum, polysilicon, polycide and silicide as contacts or vias materials, high
temperature thermal dielectrics and reactive ion etching techniques are often used in very large
scale integrated(VLSI) circuits applications.These materials and processing technologies are no
longer acceptable for high-performance ULSI circuits due to larger aspect ratio, higher inter
connection resistance, electromigration, high interdiffusion and high damage defects problems.
In this proposal, we will do a systematic studies of the design, growth, fabrication and
characterization of the W/TiSi2 or TiN or TiW or WSix/Si contacts and Al / W / Al vias
metallization by selective CVD-W and of dielectrics deposition and etching (including poly-Si)
by (Electron CyclotronResonance) Ultra High Vacuum low temperature and low pressure
processing (ECR-UHV-CVD) techniques for ULSI circuits applications. Both blanket and
selective tungsten CVD technologies will be compared. The tasks will also include new reactor
design (cold wall), new deposition chemistries, new dry etching technology, adhesion layer, step
coverage, planarization, low temperature oxide and nitride. The effects of gas flow rate and
charged pattern, pressure, wafer temperature, holder rotation and microwave power on material
characteristics will be considered. Experimental analysis will include SEM, TEM, SIMS, RBS,
SRM, RGA, C-V, I-V, DLTS, TDDB, purity roughness(grain size), and contact reliability. The
results of these experimental investigations hopefully provide high-performance ULSI CVD-W
and ECR-CVD technologies to electronics industry.
NSC86-2215-E009-047
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Title:Fabrication Process of A Planar Coil Using IC Technology

Principal Investigator:Kow-Ming Chang

Sponsor:Mechanical Industry Research Laboratories, ITRI

Keywords:Planar Coil, Micro Mass Flow Controller, Si-glass Bond, Etching



       This project is a research program to work out the IC fabrication technology of a planar
coil and micro valve (actuator). The project proposed is :

    (a) The structure design and fabrication process of a planar coil using IC technologies.
    (b) A Silicon-based micro mass flow controller (actuator) structure design technologies and
    fabrication
    (c) The related technologies including polyimide reactive ion eching, glass/pyrex etching,
    Si-glass bonding, Si diaphram formation and Si KOH etching etc.
     The results of these experimental investigations hopefully provide high-performance
Micro-Electro-Mechanical Systems (MEMS) technologies to electronics industry.
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Title:Cu-CVD System

Principal Investigator:Mao-Chieh Chen

Sponsor:National Science Council

Keywords:Cu-CVD, Cu-CVD System, Cu-CVD Process Simulation



       Copper chemical vapor deposition (Cu-CVD) is a key technology for multilevel
interconnection in the future deep sub-half micron integrated circuits. Thus, the development of
Cu-CVD system as well as processing technology has a variety of highly potential applications
in the micro-electronic industry. Based on a previous experience of building a prototype system
for the study of Cu-CVD, we are planning to develop and build, with the cooperation of Branchy
(倍強) Vacuum Technology Co., Ltd., an improved new model of Cu-CVD system equipped
with in situ substrate pretreatment and automatic control capabilities. Practical Cu film
deposition and metallization process will be developed using the newly built CVD apparatus.
This is designed to be a three-year project which consist of three sub-projects geared to the same
purpose of building the Cu-CVD system. The topics of the studies include
    1. Cu-CVD process simulation ;
    2. Development of a Cu-CVD system and process technology ;
    3. Real time multitasking control kernel for Cu-CVD system.
NSC86-2215-E009-040
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Title : Hot Carrier Related Deep Submicron MOSFET Reliability Issues:Band-

to-Band Tunneling, ESD, and Latch-up
Principal Investigator : Ming-Jer Chen

Sponsor:National Science Council

Keywords:Band-to-Band Tunneling Hot Carriers, Flash Memory, Deep Submicron, ESD,

                Latch-up, VLSI


       The project will extensively investigate the three important topics concerning the hot
carrier related deep submicron VLSI reliability : Band-to-Band Tunneling, ESD, and Latch-up.
To be performed for the band-to-band tunneling issue are (1) characterization, analysis, and
modeling of band-to-band tunneling induced drain leakage and performance degradation in deep
submicron MOSFETs; and (2) fabrication, characterization, analysis and modeling of p-channel
MOSFET based flash memory employing band-to-band tunneling induced hot electrons injection
into the floating gate. The following achievements involved with latch-up will be created: (1)
steady-state and transient characterization of hot-carrier induced latch-up from a wide variety of
the testkeys fabricated by CMOS processes; (2) 2-dimensional simulation and analytic model for
comparison with experimental data as well as the predictions for CMOS latch-up susceptibility;
(3) chip implementation and characterization of substrate bias generator circuits for suppression
of latch-up; (4) quantitative evaluation of latch-up susceptibilities of commercial chips; and (5)
quantitative suppression methods against latch-up as well as practical show. For the ESD topic,
we will (1) quantitatively evaluate the ESD susceptibility of the existing commercial chip
products along with failure analysis; (2) design and implement several ESD I/O protection
circuits including pnpn latch-up paths as sensing components along with measurement
evaluation and failure analysis; (3) perform 2-dimensional simulation and analytic model
considering mechanisms such as hot carriers, traps, and interface state generation along with
experimental comparisons; and (4) propose quantitatively suppression techniques against ESD
with practical show demonstrated.
NSC86-2215-E009-029
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Title : Implementation and Methodology for Low Power/Low Voltage Digital and Analog
Integrated Circuits.
Principal Investigator : Ming-Jer Chen

Sponsor:National Science Council

Keywords:Low Power, Low Voltage, Digital-Analog, IC, Mixed-Mode, Subthreshold,Match,

                Portable


      As highlighted by the research achievements over the past years, this project will
extensively investigate the low power/low voltage integrated circuits. The topics concerned are
to be performed:(1) implementation, measurement, and design methodology of a new SRAM
chip based on a high-gain gated lateral BJT structure; (2) chip implementation, measurement and
design methodology of new digital circuits in terms of a ring oscillator by means of back-gate
controlled dynamic threshold voltage; (3) experimental study and design methodology of
sample/hold chips for low power/low voltage mixed mode IC; (4) new match improvement
techniques and analytic design model for enhanced circuit quality; and (5) basic analog
computation circuits and voltage references utilizing subthreshold CMOS. The achievements
created from the project will be demonstrated in terms of paper, patent, and also practical show.
In addition, our work will be a great aid to our semiconductor industry in the new field of low
power/low voltage integrated circuits.
NSC86-2215-E009-038
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Title:Audio Signal Processing of Network Interactive Video/Audio System for Client End

Principal Investigator:Sau-Gee Chen

Sponsor:National Science Council

Keywords:Karaoke, Pitch Shifting, Special Sound Effect, Blind Signal Processing, Digital

                Signal Processor, Audio Code, Virtual Reality


       The project is aimed to study audio signal processing techniques related to client
interactive karaoke-on demand system. This project spans three years, In the first ongoing year,
we are now studying the following audio signal processing techniques: (1) pitch shifting of audio
signal subject to constant playing rate, (2) play rate modification subject to constant pitch, (3)
special sound effects, (4) separation of vocal and instrument sound signals, (5) real-time
implementation issues of audio processing algorithms and (6) audio coding and decoding
algorithms. In the end of the first year, we will propose low-complexity and high-performance
algorithms for these techniques and their DSP implementation. In the second coming year, we
will continue improving the algorithms and implementations of the first year's results and at the
same time proceed ASIC audio processor designs for those algorithms. In the third year, in
addition to continuing research on audio techniques and chip realization, integration and
verification of the project with the other projects will also be a major task. In the fourth year, the
research topics will be dynamically adjusted to the ever fast changing multimedia technologies.
An interesting topic is the audio signal processing techniques for virtual reality.
NSC86-2221-E009-018
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Title:Design of Computation & Postprocessing Cores for Graphic

Principal Investigator:Sau-Gee Chen

Sponsor:National Science Council

Keywords:ALU, Floating-Point Multiplier and Divider, 3-D Graphic Geometric Transformer,

                Virtual Reality


       This subproject spans three years. The goals of the project are designing computation and
postprocessing cores for VLSI graphic, and finally synthesizing these module cores to obtain a
special-purpose demonstration geometric processor for 3-D resizable graphic display. The core
modules to be investigated include:(1)special-purpose ALU,(2)high-speed floating-point
multiplier,(3)special-purose datapath for 3-D graphic display and (4)graphic algorithms and
architectures for virtual reality. Three different target clock rates of 25Mhz, 100Mhz and
250Mhz will be tried and simulated. The first (currently ongoing) year is investigating 3-D
graphic algorithms and specifications and correspondingly their architectures. Some trial designs
based on designing 0.8 micron process are also ongoing. The coming project year will then
synthesize a 0.8 micron demonstration graphic processor based on these modules. In addition,
Possibly this demonstration system can display a resizable 3-D rotated, projected, translated and
zoom in/out graphic. In the third year, based on 0.6 micron process the demonstration processor
will be further fine tuned and improved. Meanwhile, in the third year, we will continue study
new graphic algorithms and refine the core module designs in the first two years.
NSC86-2221-E009-015
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Title:Investigation & Design of PC-based Digital Imaging Systems

Principal Investigator:Sau-Gee Chen

Sponsor:View Com Technology Inc.

Keywords:



      This project is aimed to investigate the concepts and techniques behind digital camera,
then to devise a PC-based digital imaging system for general image processing, editing and
moreover video conferencing. In particular, the problems to be addressed include: grabbing of
the CCD-sensed imaging, black level compensation of the sampled signals, pixel interpolations,
white balancing and correction of the signals, Gamma correction, and those postprocessing
operations including: edge enhancement, color space conversions, resolution conversion,
half-and multi-toning for low-resolution color, and signal compression. We will devise fast and
high-performance algorithms and architectures for these operations. Finally, various digital
camera architectures under different specification and applications will be proposed.
       Further, in order to verify our designs we will build a PC-based demonstration system. For
fast prototyping and verifications, we will port the required signal processings on T1320c2x DSP
chips and design its resident circuit board. The imaging system will communicate with the PC
via PC’s serial port and follow standard TWAIN protocol. Accordingly, software driver and
API will be also developed. In the end, a prototype digital imaging demonstration system for
video conferencing will be built.


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Title : Growth Technology Polycrystalline Silicom Film for Poly-Si-Thin- Film Transistors ()
Principal Investigator : Huang-Chung Cheng

Sponsor:National Science Council

Keywords:Polysilicon Thin-Film, Thin-Film Transistor, Rapid Thermal Process,

                Recrystallization
      This project is one of subprojects of the master plan “Study and Development of Thim
Film Transistor (TFT) Technologies”. Its aim is to develop high quality poly-Si thin film for the
poly-Si TFT applications.
       TFTs have been widely need in electronic systems such as liquid crystal display (LCD)
and static randem access memory (SRAM). However, the TFT Technologies have not been
established in Taiwan. The project is to with a period of three years, develop the growth
technology for poly-Si thin film for the poly-Si TFTs.
1st year :
         (1) To make the poly-Si thin film by using the Si2H6 low pressure chemical vapor
         deposition (LPCVD) to be compared with these made by using SiH4 LPCVD.
         (2) To Study the crystallization techniques for poly-Si thin film, and to compare the
         recrystallized thim films in terms of grain size, and defect densities, prepared by using the
         conventional furnace annealing (CFA) and the rapid thermal annealing (RTA)
         Techniques.
         (3) To purchase, set up and test an excimer laser annealing system.
2nd year :
         (1) To apply the excimer laser annealing to poly-Si thin film and comparethe prepared
         films with CFA and RTA films in terms of the structure, size, and defect density of poly
         grains.
         (2) Apply the passivation techniques to the prepared films and to make Schottky diodes
         to study their electrical properties by using the deep level transient spectroscopy (DLTS).
3rd year :
         Incorporating with the techniques developed in two other associated subprojects, to make
         high performance TFT for the applications of LCD and SRAM.
NSC86-2215-E009-023
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Title:Research and Development for a-Si:H Thin-Film Transistors for Liquid Crystal Display

         (3/3)-The Reliability Analysis of Amorphous Silicon Thin Film Transistors

Principal Investigator:Huang-Chung Cheng

Sponsor:UMC

Keywords:



       The project is one of subprojects of the master plan: Research and Development for a
-Si:H Thin-Film Transistors for Liquid Crystal Display (3/3). Its ain is to study the reliability of
a-Si:H TFTs for different AC gate bias and temperatures.
      In LCD panels the TFTs, used as switching element, is operated under AC signal.
Therefore, it is most important to understand the reliability of a-Si:H TFTs. At the project of this
year:
    1. To study the reliability of the temperature effect
    2. To study the reliability of a-Si:H TFTs after AC operation
    3. To compare the reliabilty of a -Si:H TFTs for DC and AC stress and to establish the
    data-bank of the reliability for a-Si:H TFTS
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Title:The Study of Process and Characteistis、Stability of Package for Presser Sensor

Principal Investigator:Huang-Chung Cheng

Sponsor:Republic of China Industrial Technology Research Institute

Keywords:Pressure Sensor, Sensor Package



      Silicon pressure sensor is well known for silicon single crystal’s high mechanical
strength, which is comparable to steel, and low hysteresis. These properties, combined with the
well developed electronic and high piezoresistivity, make it one of the best products for pressure
sensor market. After years of study and development in silicon micro-machining, process
integration, and package technology, silicon piezoresistive pressure sensor has become the first
commercialized product in the micro mechanical system. Although it has been long developed,
there are still many factors, such as process parameters, package design, etc., affected its final
characteristics and stability.
      In the present study the process control factors, which strongly influence the silicon
pressure sensor characteristics, are thoroughly discussed and determined to fit into the
experimental design strategy. In order to determine those most critical, two to four process
parameters are selected and designed in process integration, micro-machining and packaging
parameters. The sensors characteristics are analyzed and calculated to determine the best
parameter combination.
      Results of those experiments are provided to give pressure sensor designer best reference
for device improvement and process control. It also is helpful in building the technology and
experience basis for the domestic silicon pressure sensor capability.


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Title:Process Study of ECR Plasma Equipments
Principal Investigator:Huang-Chung Cheng

Sponsor:Chung-Shan Institute of Science & Technology

Keywords:



     This project utilize the high density plasma equipments in NDL to study the process and
damage of plasma etching, The aims of this project are:

    1. Utilize the ECR system developed by the CSIST to perform the photoresist etching with
    O2 plasma, measure the plasma density and uniformity, and photoresist etching rate and
    uniformity.
    2. Help CSIST to study the structure of ECR system, referring to the metal CVD available in
    NDL and the MRC structure.

    3. Two studies about ECR damages:

         (1) Study the etching damage using the equipments available in NDL.
         (2) Study the wafer damage by Ar plasma employing the ECR system in CSIST.


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Title:Research of Ferroelectric Tactile Sensing Materials

Principal Investigator:Bi-Shiou Chiou

Sponsor:National Science Council

Keywords:Batio3, Ferroelectricity, Piezoelectric Transducer, Tactile Sensing Material



      Ferroelectric barium titanate is a multi-functional material. With appropriate additives
and/or appropriate processing conditions BaTiO3-based ceramics can be fabricated as PTCR
thermistor, capacitor sensing element...etc.. In addition, ferroeletric ceramic/polymer composite
has great potential in application of piezoelectric transducer.
     The objective of this research is to study the feasibility of fabricating BaTiO 3/polymer
composite tactile sensing material.
This project includes:
    1. Process study of BaTiO3/polymer composite
    2. Dielectric behavior of heterogeneous BaTiO3/polymer composite
    3. Fabrication and measurement of tactile sensing pad
NSC86-2216-E009-019
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Title:A development of Bonding Technology and Test Vehicle for High-Density Electronic
Packaging

Principal Investigator:Bi-Shiou Chiou

Sponsor:National Science Council

Keywords:Electronic Packing, Multi-Chip Module, Thin Film, Multilayer Interconnection

                Structure, Filp-Chip Connection


       Recently the Multi-Chip Module (MCM) has become a new packaging and
interconnection approach to overcome the barriers of progress created by conventional
packaging technology. It provides electronic equipments with significant reduction in size and
weight, together with increases in circuit density, reliability, and high speed electrical
performance. The substrate used for MCM packaging containing a multilayer inter-connection
structure can be fabricated by thick film, thin film , or the co-fired multilayer ceramic (MLC)
technology. Among these, the silicon substrate covered with multiple layers of metal conductor
and dielectric provides many advantages such as the substrate coefficient of thermal expansion is
an exact match with VLSI chips, and thereby becomes the most promising type of substrate for
MCM packaging bonding technology.
      In this proposed research, high density packaging will be investigated and a testing vehicle
is chosen for the demonstration of the high density packaging.
NSC86-2221-E009-061
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Title:Enhanced Cu Interconnection Reliability (Ι) : Electromigration Of Cu With TiN As

         Interfacial Bonding Layer

Principal Investigator:Bi-Shiou Chiou

Sponsor:National Science Council

Keywords:Cu Metallization, Electronic Package, Diffusion Barrier Layer, Electromigration



      In this research, radio frequency sputtered TiN film will be employed as the interfacial
bonding layer between Cu metallization and substrate. The effect of TiN on the electromigration
of Cu will be investigated. This project includes:
    1. Process study and mechanism investigation of TiN in the preventation of Cu oxidation.
    2. Study on the effect of TiN layer on the electromigration of Cu metallization.
    3. Improvement of Cu interconnection and reliability.
NSC86-2221-E009-062
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Title:The Mechanism of Atmosphere Influence on Dielectric and Endterminat-Ion for MLCC

         During Curing

Principal Investigator:Bi-Shiou Chiou

Sponsor:Philips EBEI (Taiwan) Ltd.

Keywords:



       The influence of moisture on BaTiO3 and Cu end-termination during curing will be
investigated. To understand the interactions between different atmosphere (such as moisture,
organic binder, PbO, ZnO.....etc) and physical properties (such as mechanical behaviors,
electrical properties and microstructure), this proposal is concentrated on the mechanism study of
moisture with BaTiO3 and glass of Cu end-termination. In addition, unclear part of previous
cooperated project will be successfully investigated from theoretical point of view. Basically,
more understanding on Cu firing in nitogen with moisture will be expected during our studies.


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Title:Construct a Simple Multimedia Communication System Using Java

Principal Investigator:Hsueh-Ming Hang

Sponsor:Industrial Technology Research Institute, ITRI

Keywords:Java, Interactive TV, Multimedia Communication, DAVIC



      Java is a new comer to the world of programming languages. Its platform-independent,
multi-tread and multimedia abilities make it a good candidate for constructing multimedia
communication applications. It is thus the goal of this project to study Java and using it to
implement a simple DAVIC-like multimedia communication system. A large portion of our
work would be on the client side. We plan to build a multimedia presentation runtime engine
(similar to the MHEG runtime engine), a simple authoring tool, and a user interface. We also
need to construct a simple server offering several basic services such as browsing, downloading
and playing back MPEG video. With the aid of Java, it may be possible to construct a flexible
and efficient system at a minimum cost of time and effort. Through this study, we like to test the
capability of Java and at the same time build a simple (simulated) demonstration system.
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Title:Spatially Adaptive Interpolation of Image Using Fuzzy Inference and Its Applications

Principal Investigator:Hsueh-Ming Hang

Sponsor:National Science Council

Keywords: Image Interpolation, Fuzzy System, Nonlinear Interpolator



       Our goal in this project is to design a novel adaptive interpolation method for digital
images and present its applications on image multi-layer coding. This new method can reduce
dramatically the blurring and jaggedness artifacts on the high-contrast edges, which are generally
found in the interpolated images using conventional methods. This high performance is achieved
via two proposed operators: a fuzzy-inference based edge preserving interpolator and an
edge-shifted matching scheme. The former synthesizes the interpolated pixel to match the image
local characteristics. Hence, edge integrity can be retained. However, due to its small footage, it
does not work well on the sharply curved edges that have very sharp angles against one of the
coordinates. Therefore, the edge-shifted matching technique is developed to identify precisely
the orientation of sharply curved edges. By combining these two techniques, the subjective
quality of the interpolated images is expected to be significantly improved, particularly along the
high-contrast edges.
      Both computer-synthesized images and natural scenes will be tested for demonstration.
Natural scenes are taken by camera or film recorder, they often contain noises. Also in natural
images, shadows due to photographic exposure appear along the edges of objects. Therefore, we
need to study their characteristics and impact on image interpolation. To select the optimal
parameters for our interpolation and orientation detection schemes, we plan to conduct statistical
analysis on noise effect for further investigation. For practical applications, in addition to still
image magnification for viewing comfort or detail browsing, we can also use this interpolation
method to improve the efficiency of multi-layer image coding. Because additional high
frequency components are recovered by the proposed interpolation method, the higher layer
images should be coded with fewer bits than the conventional interpolation methods.
NSC 86-2213-E009-064
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Title:2D/3D Conversion

Principal Investigator:Hsueh-Ming Hang

Sponsor:Opto-Electronics and System Labs./Industrial Technology Research Institute

             (8/1996~5/1997)

Keywords:
      We plan to build a stereo image simulation environment in this project. In addition, we
like to review the processing techniques for stereo images and investigate the conversion
methods of video from a monocular (one channel) image sequence to a stereo (two channel)
image sequence. There are three major items in our plan. We first set up a stereo simulation
environment using polarized light display. By attaching a polarized screen to a high quality, high
frequency monitor, the viewer can see stereo images with a pair of polarized glasses. The second
item is to conduct a comprehensive survey on various stereo image processing techniques, find
out their current status, and explore the promising applications of using high precision digital
camera. Candidates are geometric stereo, motion stereo, shape form focus, etc. The third item is
to convert a sequence of 2D images ito a pair of sequences, each corresponding to one channel of
stereo video. An inital approach is to segment objects and add in pseudo depth information based
on the global and local motion information.


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Title:Karaoke-on-Demond System Integration and Video Encoder System-Level Design

Principal Investigator:Hsueh-Ming Hang

Sponsor:National Science Council

Keywords: Koraroke-on-Demond, Interactive TV, Video VLSI, DAVIC



       This project is a sub-project of the Interactive Audio/Video Networks group project. The
entire project will continue for four years and this year is the second year. The goal we wish to
accomplish in this year are as follows: (1) continue to build a basic Karaoke-on-Demand (KOD)
testbed; (2) study interactive TV standards such as DAVIC; and (3) evaluate encoder algorithms
and hardware structures for efficient VLSI implementation.
      Learned from our previous year experiences, we found constructing a real-time ITV
testbed is severely limited by the available components in the market. Hence, we are unable to
implement protocols and operations that are essential in a large-scale ITV system. In order to
have a through understanding of a complete ITV system, it is necessary to study the international
ITV standards. If time and man power permit, we may be able to simulate portions of the
DAVIC specfications. In addition, there are few real-time video encoder systems in the market;
therefore, we plan to study the high level architectures that would facilitate the development of
encoder VLSI design. We will also continue the testbed construction from last year and include
some advanced KOD features. In the third and fourth years, we plan to work on two-way ITV
systems such as distance learning and wireless video.
NSC86-2221-E009-023
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Title:Fabrication and Characterization of Deep Sub-micron Transistors

Principal Investigator:Tiao-Yuan Huang
Sponsor:National Science Council

Keywords:Deep-Submicron Devices, MOS Transistors, Short-Channel Effects



       MOS transistor is the fundamental building block for all ULSI circuits. The main purpose
of this study is to investigate device structures with 0.18 mm to 0.12 mm gate lengths. We plan
to fabricate and study device structures with channel length in the range of 0.18 mm to 0.12 mm.
Various device structures will be analyzed and studied. Promising and feasible device structures
will be fabricated using NDL processing facility. In order to accomplish gate length in the range
of 0.18 mm to 0.12 mm, either ashing or e-beam lithography, together with proper polysilicon
etching techniques (resist or hard mask) will be employed to achieve the desired transistor gate
length. The feasibility of various S/D extension methods, gate dielectric hardening techniques,
and salicidation schemes will be applied to fabricate deep-submicron device structures, if
applicable.
NSC86-2215-E009-046
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Title:Si Based Integrated ARROW-type Waveguide Chemical and Biochemical Sensors

Principal Investigator:Yang-Tung Huang

Sponsor:National Science Council

Keywords:Chemical and Biochemical Sensors, Spectroscopy, Fiber-optic Sensors, Integrated

                Optics, Antiresonant Reflection Optical Waveguides, MEMS


       The purpose of this project is to develop chemical and biochemical sensors based on
optical absorptiometry or refractiometry of evanescent-waves in the integrated antiresonant
reflecting optical waveguides (ARROW). Chemical and biochemical sensors are key elements
for following applications, including (1) medical engineering, (2) biochemical engineering, (3)
environmental engineering, (4) factory auto-processing, (5) gas, petroleum and ground water
monitoring, (6) alarm system, (7) sensors in automobiles, and (8) consumer products. With
microelectro-mechanical techniques developed recently, optical sensors can be miniaturized and
integrated with fiber communication WDM systems to become a multi-processing sensor
systems. The structure parameters of integrated waveguide sensors can be accurately controlled
for mass-production stability. Moreover, these elements in conjunction with the fibers can be
used in remote sensing applications. ARROW-type waveguides are new developed integrated
optical devices which have the following advantages over conventional waveguides: (1) high
coupling efficiency with fibers, (2) single-mode operation, (3) good ability to be integrated on
high refractive-index substrate, and (4) low propagation loss. Our research group has been
investigating ARROW devices on: (1) optimum coupling design with single-mode fibers, (2)
high-efficiency and easy-fabrication power dividers, (3) wavelength multi/demultiplexors, and (4)
optical filters. With these above experiences, we will continue developing (1) integrated taper
couplers, (2) hybrid couplers, and (3) interferometers to design new-type ARROW chemical and
bioche-mical sensors. In the whole 3-year project, we will integrate various ARROW devices to
construct multiprocessing sensor systems. The main aim of the first year is to build the necessary
analysis theories and computer programs to find the most suitable sensing schemes and optimum
designs for sensing various chemicals such as CO, NO2, NH3 and CH4 etc. In the second year,
we will fabricate various individual ARROW sensors and design the multiprocessing sensor
systems, analyze their performance. In the last year, we will build the whole multiprocessing
sensor systems and test their performance.
NSC86-2221-E009-040
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Title:Graphics/Video Hardware and Their High-level Design(II)

Principal Investigator:Chein-Wei Jen

Sponsor:National Science Council

Keywords:Graphics Core, High-level Design, Shading Processor



       Graphics/Video Core Design Methodology is a promising way to develop the system IC’
s in multimedia and interactive TV applications. The main goals of this project are: (1)to build
and maintain this core and their associated design methods cooperating with other two projects;
(2)to develop a programmable shading processor IC by using this core and design method.
      This is a three-year project. In the first year, we will finish the instruction set design,
host-interface and some dedicated function unit core design. And we will also develop a
high-level function simulator and VLIW instruction scheduler. The tasks of the second year will
focus on the design and implementation of the Shading Processor. In the third year, the chip
should be fabricated and tested.
      In this second year, a shading processor in 3D graphics will be designed. The objectives
comprise shading algorithms (vertex/pixel shading, texture mapping) analysis, instruction set
define, architecture design and performance measure, login design and verification. We will
adopt the cores and design methodoloty developed in the 1st year to finish this IC design.
NSC86-2221-E009-014
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Title:The Study on Hardware-Software Codesign for Integrated Systems

Principal Investigator:Chein-Wei Jen

Sponsor:National Science Council

Keywords:System Design, Hardware and Software Partitioning, Integrated Systems



       The research project will investigate an effective approach to the system-level design of
signal processing applications. Such applications tend to have mixed hardware-software
components and are often subject to severe cost, performance, and design-time constraints. To
design these systems, we use the codesign approach, which allows the hardware and software
designs to be tightly coupled throughout the design process.
       Given a specification of system functionality and constraints, we propose a model to
describe the system. After the model has been verified, partitioning is used to determine the parts
of the system functionality that are delegated to application-specific hardware and the software
that runs on the processor. In addition, the ability to quickly explore the design space provides an
opportunity to improve the system performance by applying a series of model transformations.
We also explore issues concerning the implementation of a hardware-software interface to
accommodate communications between various parts of the system.
       This hardware and software codesign approach proposed makes it possible to build
time-constrained signal processing systems using programmable parts and application-specific
units.
NSC86-2221-E009-51
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Title:Texture Mapping Technology

Principal Investigator:Chein-Wei Jen

Sponsor:Macronix International CO., LTD

Keywords:



      Texture mapping is one of the important technologies in 3D Computer Graphics. It makes
the computer to generate the more realistic image. The project is to investigate the related
techniques which comprise the various algorithm analysis and their architecture mapping. The IC
module design and verification are also included and the target goals are high performance and
low cost.


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Title:Low Power Design and CAD Using Mixed-Voltage Design Style

Principal Investigator:Jing-Yang Jou

Sponsor:National Science Council

Keywords:Power Dissipation, Switching Activity, Monte Carlo Approach, Logic Synthesis For

                LUT-Based FPGA
      Average power dissipation has recently emerged as an important parameter in the design
of general-purpose and application-specific integrated circuits. The well perceived formula

                           P= f VddΣ(PiCi)

      is used to perform a quick power estimation(where f is the frequency, Vdd is the power
supply voltage, N is the total number of nodes in the circuits, Pi is the average number of
switching in a clock cycle, and Ci is the ith node capacitance).
      Most of the existing efforts on lowing the average power dissipation have concentrated on
reducing the average switching activities for the entire circuits at several levels of abstraction.
However, From the power estimation formula, it is easy to know that lowing the power supply
voltage can dramatically reduce the power consumption of ICs. while the speed of the design can
be degraded. In order to have low power design still with high speed, several advanced
semiconductor companies offer standard cell libraries that allow mixing cells with different
power supply voltages on the same chip. If we use low voltage cells in the noncritical parts of the
designs and use high voltage cells in the more critical parts of the designs, we can lower the
power consumption while still have high speed for our designs. Based on the above observation,
we plan to develop a circuit partitioner for mixed voltage(e.g. 3V/5V) design styles. The aim is
to minimize the power dissipation while not to sacrify the performance requirement.
       We try to build a power estimator based on an improved Monte Carlo approach. the
resulting method is statistical in nature. It intelligently uses some functional information to guide
the pseudo random pattern generation. It applies these patterns to the circuit and monitors, with a
rather accurate simulator, the resulting power value. The process continues until a value of power
is obtained with a desired accuracy, at a specified confidence level. The speed of the
convergence is expected to be greatly improved by the new method with functional grouping.
This new method combines the accuracy of simulation-based techniques with the speed of the
probabilistic techniques. It is expected to be a practical solution with theoretic innovation.
      A logic decomposition technique, Roth-Karp decomposition, is widely used to optimize
the combinational logic parts of LUT-based FPGA's. There are two key steps of this technique:
The first on is how to select a set of input variables, called the bound set, to decompose the
function. The other is how to encode the compatible classes. In this project, we handle these two
problems by introducing the analysis of the input transition density. The aim is to minimize the
power consumption of the circuit synthesized by this new technique.
NSC86-2221-E009-011
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Title:A Study on Low Power VLSI Design and Computer-Aided Design

Principal Investigator:Jing-Yang Jou

Sponsor:National Science Council

Keywords:



       Low power circuit and system designs are becoming increasingly important in today's
technology as wireless communication and mobility of electronic equipment become increasing
desirable. The objective of this project is to build a design environment to support low power
designs. The design environment includes the hierarchical power characterization system,
hierarchical power analysis system, and hierarchical power optimization system. These systems
will be integrated into the OPUS design framework which is now the common design
environment supported by Chip Implementation Center (CIC). In addition, in order to verify the
effectiveness and correctness of the design environment, the Reed-Solomon codec is used as an
design example to exercise all the low power design techniques and CAD tools developed by this
project.
NSC86-2221-E009-005
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Title:”VLSI Testing and Design for Testability” Course Development— Fundamentals and

            Design Methodology, Combinational Circuit Testing, Sequential Circuit Testing and
            Design Examples

Principal Investigator:Jing-Yang Jou

Sponsor:National Science Council

Keywords:VLSI Design, VLSI Testing, Design for Testability



       This subproject is one of the integrated part of a joint proposal: "A Joint Project to
Develop a VLSI Testing and Design for Testability Course for Universities in Taiwan". The aim
of the developed course is to train students in electrical engineering major to gain the experience
and ability to do system analysis, design and integration on VLSI design by considering testing
issue. The course will include lectures, experiments and term projects. The project includes the
work to modify ad integrate the software tools developed in many local universities to be an
integrated tool set to help students do experiments and projects.
      This subproject will be dedicated to developing lecture, experiment, and term project
materials on the following subjects:
    1. Fundamentals on Testing and Design for Testability
    2. Design Methodology
    3. Combinational Circuit Test Generation
    4. Sequential Circuit Test Generation
    5. Design Examples
       The project is a three-year project: For the first year, the course materials, which include
lecture notes, experiment sets, term project problems and necessary software tools, will be
prepared. For the second year, the course materials will be trial-taught at the undergraduate of
National Chiao Tung University and response from students and results on the teaching will be
evaluated and course materials will be improved. The first draft of the text book in English will
also be written. For the third year, the improved course will be taught again and a formal
textbook in Chinese, will be written. The overall experience and results gained through this
project will be written as a paper to be submitted to a related conference or magazine on testing
education.
NSC85-2512-S009-009
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Title:A Research on AC Source Technologies of EDM

Principal Investigator:Mei-Shong Kuo

Sponsor:Mechanical Industry Research Laboratories, ITRI

Keywords:A.C. Type Electrical Discharge Machining Power Source



       This project is a 2nd year’s extension of the “technology research of WEDM AC
power source” In the 1st year. we had analyzed the measured operation repouts of the existing
standard Japanese WEDM and its' improved WEDM. Explained the actual CKT operating
principles and the relative effects among the parameters of the WEDM stated. We finally
proposed a power effective new CKT to improve the operating power efficiency form that of
lower than 25% to that of higher that 65%. In the 2nd years project well investigate the possiehle
OKTs for the AX type high freq. WEDM power source, analyze the differences of their
operations. The basic requirements of our WEDM air:(1)We must predeposit the required energy
is a chosed capacitor for each discharging in order to control the machine power. (2) To avoid
the electrolytie process to spoil the surface integrality of the machining target, the discharging
current should contain no DC comport. (3) The higher the discharging frequency, the better the
machining quality. It is expected that the disdrarging frequency should be as high as possible. It
is tough to design a high frequency high carrent discharging CKT. Will take the following
measures to meet the challenges: (1) Use the isolation TLT to couple the high speed AC
discharging current. (2) The equivalent CKT of the high speed switching transister is used in the
CKT analysis. (3) To increase the CKT frequency response, will choose the qualified CKT from
the CKT group of resonant inverters, they must also in the type of zero voltage switching (ZUS)
operation or zero current switching operation (ZCS) clase D technology or in the type of low
dv/dt suritching or low di/dt switching operation class E technology. Will implement the selected
CKTs, fixing up the high speed CKT troubles and test the prototyped CKTs their WEDM
operation.


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Title:Surface Effects in Quantitative Analysis of Electron Energy

Principal Investigator:Cheng-May Kwei

Sponsor:National Science Council
Keywords:Electron Energy Spectra, Inelastic Scattering, Surface Excitations.



       Quantitative analysis of electron energy spectra is important in various electron
spectroscopies1-6 such as Auger electron spectroscopy, X-ray photoelectron spectroscopy,
reflected electron energy loss spectroscopy, etc. Information on the electron-solid
interactions7-12 is necessary for this analysis. The accuracy of the analysis relies on the models
of elastic and inelastic interactions.
       Based on the dielectric theory13,14, a more detailed theoretical model of inelastic cross
sections for volume and surface excitations will be developed. A model dielectric function which
satisfies sum rules and agrees with optical data will be established15. In order to characterize the
surface effects, the energy dependent surface excitation parameters11,16 will be calculated from
the interaction cross sections of surface excitations as a function of emergence angle.
       Although Monte Carlo simulation method17-21, a numerical procedure involving random
numbers for the simulation of the electron trajectories, is often used in the treatment of electron
transport. An analytical formalism is desired for practical applications. The simple formalism of
quantitative analysis in common use22-25 is based on the assumption of neglecting the surface
effects. This assumption may not always be valid10,11,26-28. Therefore, we intend to modify the
formalism by including the surface effects. The influence of surface effects on the energy spectra
of electrons for a wide range of possible applications will be investigated.
NSC86-2215-E009-037
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Title:The Study of Hardware Core Designs for Video Coding And 3-D Graphics(II)

Principal Investigator:Chen-Yi Lee

Sponsor:National Science Council

Keywords:Video Coding, 3-D Graphics, Hardware Modules



      As digital video and 3-D graphics applications become more and more popular, it is
necessary to develop cost-effective hardware solutions in a reasonable time interval to realize
complex algorithms using state-of-the-art VLSI technology. Especially in the domain of
video/graphics processors (VGP), how to achieve system-on-chip solution for video/graphics
engine (or accelerator) becomes one of the key research issues in the industry.
       In principle, a VGP consists of several basic modules, such as DCT/IDCT, ME/MC,
VLC/VLD, Rendering Accelerator, Rasterization Engine, ... etc. A VGP can be constructed by
several basic modules as well as memory and controller. This motivates us the research effort in
the 2nd year on part of the basic modules mentioned above. Not only these modules have to meet
the need of MPEG2 data flow, but also interface between modules have to be taken into account
in order to reduce memory size needed in integration. In addition, these modules should have
different versions to meet different data rates so that optimal solutions can be achieved. The
selected modules will be verified on TSMC 0.6um CMOS SPDM process by exploiting the core
designs developed in the first year. Finally, we'll also set up their behavior modelling in
Verilog-HDL and derive VLSI design methodology in order to shorten the development phase of
"video/graphics system-on-chip".
NSC86-2221-E009-016
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Title:The Study of Multi-Casting ATM Switch System for Video-on-Demand

Principal Investigator:Chen-Yi Lee

Sponsor:National Science Council

Keywords:Multimedia System, Communications Networks, ATM Switch, Interactive

                Applications-on-Demand, Multi-Casting


     As multimedia systems and communications advance, many new applications are developed
or highly demanded for real-life applications. This trend also requests the need of more research
and development efforts in the micro-electronics and information technologies. One of the
important keys in so-called multi-media communications is to efficiently use limited channel
bandwidth to meet real-time performance of many digital applications-on-demand systems. The
goal of this project is aimed to provide a systematic design approach for ATM switch
architecture and control strategy, including theoretical analysis and feasible silicon solutions.
       This research proposal mainly contains two parts: (a) for ATM switch system, we plan to
investigate and analyze different available switch architectures and scalability in order to derive
a suitable architectural solution for multicasting and, in the meantime, to solve I/O bottleneck at
server site; (b) for hardware realization, we plan to investigate the feasibility of low-cost solution
based on memory structure as well as state-of-the-art VLSI technology (for logic process).
NSC86-2221-E009-020
---------------------------------------------------------------------------------------------------------------------



Title:VLSI Design for Graphics and Video Processing

Principal Investigator:Chen-Yi Lee

Sponsor:National Science Council

Keywords:



       The goals of this project which consists of three subprojects are to build a graphics/video
core and set up the associated design method. And also some IC's are designed and fabricated in
this project. The abstracts of subprojects are:
   (1) Graphics/Video Hardware and their High-level Design (by Prof. Chein-Wei Jen)
      Graphics/Video Core Design Methodology is a promissing way to develop the system IC's
in multimedia and interactive TV applications.
The main goals of this project are :
           1. to build and maintain this core and their associated design methods cooperating
              with other two projects;
           2. to develop a programmable shading processor IC by using this core and design
              method.
      This is a three-year project. In the first year, we will finish the instruction set design,
host-interface and some dedicated function unit core design. And we will also develop a
high-level function simulator and VLIW instruction scheduler. The tasks of the second year will
focus on the design and implementation of the Shading Processor. In the third year, the chip
should be fabricated and tested. The core and high-level design methods shell also be updated.
      In this second year, a shading processor in 3D graphics will be designed. The objectives
comprise shading algorithms (vertex/pixel shading, texture mapping) analysis, construction set
define, architecture design and performance measure, logic design and verification. We will
adopt the cores and design methodology developed in the 1st year to finish this IC design.
   (2) Design of Computation & Postprocessing Cores for Graphic Processing (by Prof.
   Sau-Gee Chen)
       This subproject spans three years. The goals of the project are designing computation and
postprocessing cores for VLSI graphic, and finally synthesizing these module cores to obtain a
special-purpose demonstration geometric processor for 3-D resizable graphic display. The core
modules to be investigated include: (1) general- purpose ALU, (2) high-speed floating-point
multiplier, (3) special- purpose datapath for 3-D graphic display and (4) graphic algorithms and
architectures for virtual reality. Three different target clock rates of 25MHz, 100MHz and
250MHz will be tried and simulated. The first (currently ongoing) year is investigating 3-D
graphic algorithms and specifications and correspondingly their architectures. Some trial designs
based on designing 0.8 micron process are also ongoing. The coming project year will then
synthesize a 0.8 micron demonstration graphic processor based on these modules. This processor
is targeted for 3-D graphic geometric transformation operations such as translation, rotation,
projection and zooming. In addition, further improvement over the first year's results will be
continued. In the third year, based on 0.6 micron process the demonstration processor will be
further fine tuned and improved. Meanwhile, in the third year, we will continue studying new
graphic algorithms and architectures such as for virtual reality and refine the core module
designs in the first two years.
   (3) Hardware Core Designs for High-Performance Video/Graphics Processors (by Prof.
   Cheng-Yee Lee)
      As digital video and 3-D graphics applications become more and more popular, it is
necessary to develop cost-effective hardware solutions in a reasonable time interval to realize
complex algorithms using state-of-the-art VLSI technology. Especially in the domain of
video/graphics processors (VGP), how to achieve system-on-chip solution for video/graphics
engine (or accelerator) becomes one of the key research issues in the industry. In principle, a
VGP consists of several basic modules, such as DCT/IDCT, ME/MC, VLC/VLD, Rendering
Accelerator, Rasterization Engine, ... etc. A VGP can be constructed by several basic modules as
well as memory and controller. This motivates us the research effort in the 2nd year on part of
the basic modules mentioned above. Not only these modules have to meet the need of MPEG2
data flow, but also interface between modules have to be taken into account in order to reduce
memory size needed in integration. In addition, these modules should have different versions to
meet different data rates so that optimal solutions can be achieved. The selected modules will be
verified on TSMC 0.6um CMOS SPDM process by exploiting the core designs developed in the
first year. Finally, we'll also set up their behavior modelling in Verilog-HDL and derive VLSI
design methodology in order to shorten the development phase of "video/graphics
system-on-chip".
       In the first year, the research efforts will be focused on hardware cores such as high-speed
foreground/background memory, timing controller, address generator, and dedicated hardware
modules which have been identified based on research work in the literature and our experience.
We are going to describe the behavioral model for each module in HDL and, in the meantime, to
investigate corresponding circuit and layout techniques. Also cooperation with other two projects
has to be conducted continuously in order to set up a proto-type design environment for the
development of video/graphics processors. To verify and evaluate the capability of this design
environment, we are going to explore a reconfigurable processor architecture for video/graphics
applications. These core modules will be verified on silicon and tested through MPC services
supported by NSC/CIC. In the 2nd year, the major effort will be focused on the implementation
of this proto-typing processor. In addition fine-tuning the design environment and making
module generators for these cores in OPUS environment will be conducted in order to make the
design environment more powerful. In the 3rd year, the major work will be focused on the
implementation and testing of this demo processor, and the refinement of the design environment
so that design cycle, together with research results from other 2 projects, can be reduced at
different levels.
NSC86-2221-E009-013
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Title:A Chip-Set for ATM Concentrator(II)

Principal Investigator:Chen-Yi Lee

Sponsor:Chung-Hwa Telecommunication Laboratories

Keywords:



       The goal of this research project is to investigate a chip set solution for ATM concentrator.
The complete system has been divided into three parts, namely header translator, shared buffer
memory, and system controller. The header translator is designed as an interface between
line-card and concentrator board. The shared buffer memory is a buffer pool to keep pay load
data of input ports before being transferred out. The system controller is the control kernel of the
concentrator which includes both multicasting function and QoS management. In addition to
developing cost-effective VLSI architectures for these partitioned tasks, design guidelines and
HDL environment suitable for ATM key components will also be explored in this project.
---------------------------------------------------------------------------------------------------------------------



Title:Design and Simulation of DVD Red-Emitting Laser Diodes

Principal Investigator:Chien-Ping Lee

Sponsor:Industrial Technology Research Institute, IRTI

Keywords:



       For future DVD (digital video disk) applications, the light source will be 630nm to 650nm
laser diodes. The material system that can produce such light is GaInP/ AlGaInP lattice matched
to GaAs. However because of the limitation of the materials and the heterostructures, the laser
structure is difficult to design when the wavelength is approaching 630nm. Without proper
design, the lasers will have increased threshold current and increased temperature sensitivity.
       In this project, we will investigate the GaInP/AlGaInP red lasers from the most basic band
structure calculation. After the layer structure is determined, we will investigate the lateral stripe
structure. ITRI will growth the structure and fabricate the laser diodes to verify the theoretical
calculations. The goal of this project is to determine a useful and optimized structure for DVD
applications.


---------------------------------------------------------------------------------------------------------------------



Title:VLSI Testing and Design for Testability

Principal Investigator:Chung-Len Lee

Sponsor:National Science Council

Keywords:Sequential Circuit Testing, Invalid States, Design For Testability, Timing Simulator,

               Power Optimization, Multi-Valued Logic, Current Mode Circuit, Analog Circuit
               Testing, Fault Model, Parallel Pattern Fault Simulation, Sorting Networks, Fault-
               Tolerant Design



       This project is the continuation of the previous year‘s project: “Testing, Design and
Synthesis for Testability of VLSI.”. Based on results obtained from the previous project, it
further studies some important topics related on design and testing for VLSI. The topics and
details are:

1、Invalid States Identification for Sequential Circuits

       During test generation process for sequential circuits, it usually needs to justify states to
activate and propagate faults. On this process, it takes much time to justify a state if it is invalid.
Hence, it is desirable to identify the complete or partial set of invalid states before test generation.
We will develop a new method by transforming the circuit into a graph, and partitioning the
circuit and then simulating the circuit to identify the invalid states. The method is expected to be
very fast and be able to handle large circuits.

2、Design for Testability for Sequential Circuits

       In the last year project, we have developed a method which utlizes “characteristics” to
identify uncontrollable lines and invalid states. The “characteristics” indicate the ability of
flip-flops being initialized to be 1 or 0, hence they can be used for partial scanning for flip-flops
to improve the circuit testability. Also, in the above invalid states identification process, the
information obtained for invalid states can also be used for partial scan design. Partial scan
schemes based on the above information will be implemented.

3、Parallel Pattern Timing Simulator

     In the design and testing of integrated circuits, timing information is indispensable,
especially for the present advanced VLSI. In this sub-topic, we will develop a parallel pattern
timing simulator which can verify the logic design correctness as well as the timing behavior of a
logic circuit. This simulator has the advantage of high speed due to its parallel pattern feature. It
can be used to simulate the timing faults of the circuit and to simulate the transient behaviors
which determine the power dissipation of the circuit.

4、Power Estimation and Optimization

       The continuing increase in the chip density and the operation frequency have made power
consumption a major concern in VLSI design. In this sub-topic, we will develop a power
estimation and optimization scheme to improve the power performance of a circuit. The node of
high power dissipation will be first identified and methods will be developed to redesign the
circuit node to decrease the power. The timing simulator developed in the above sub-topic will
be used to evaluate the results.

5、Fault Model for Current Model MVL Circuit

      The conventional stuck-at fault model is not that appropriate to describe the real faulty
behavior of a circuit, especially for MV-CMCL(multi-valued current mode CMOS logic). In this
sub-topic, a more reasonable and practical fault model for the MV-CMCL will be studied and
proposed. It is to map the faults from the circuit level to the logic level. The more realistic faults
will consist of some for the circuit level and some for the logic level. The test generation based
on the proposed fault model will also be studied. The developed fault model will then be applied
to the analog circuit testing since analog circuit can be considered to be a special case of
multi-valued logic circuit with many levels of logic.

6、Analog IC Testing

      In this sub-topic, we will adopt another approach to establish a analog fault model based
on physical defects of the chip. Subsequently, a complete fault simulation for analog circuits will
be investigated. According to the results of fault simulation, we attempt to deduce a behavior
fault model for the analog circuits. Finally, we will find the appropriate test stimuli from the
behavior fault model we get previously.
      The faulty behaviors of analog circuit modules such as operational amplifiers, A/D and
D/A converters, will be obtained by SPICE-simulating their circuits by injecting circuit element
faults, which are caused by physical defects of the chip. Representation behavior faults will be
categorized for each type of modules. Based on the fault models obtained, appropriate test
stimuli will be developed to test these analogy circuit modules.

7、High Level Parallel Fault Simulation

       To speedup the fault simulation speed, we will propose a methodology of high level
parallel fault simulation. For this fault simulation, for the faulty module, faults will be simulated
with parallel faults at the gate level. For fault propagation, the fault effects will be propagated
through fault-free modules at high level. This will combine the advantages of the parallel fault
simulation and the high level hardware description to increase the simulation speed.
8. Fault Tolerant Design of Odd-Even Sorting Networks
      For high throughput VLSI sorting networks, fault-tolerant design is very important since
un-interrupt operation of the system is desired. In this sub-topic, a fault-tolerant design for
Odd-Even sorting network will be studied and proposed. It is first to identify the location and
type of faults. First we are to study the set of faults which really occur in an Odd-Even sorting
network. Then a procedure to identify the type and location of faults will be proposed. A design
scheme is then proposed to fault-tolerate the single occurrence of the above faults.
NSC86-2215-E009-054


---------------------------------------------------------------------------------------------------------------------



Title:Study and Development on Poly-Si Thin-Film Transistors and Their Related Technologies

Principal Investigator:Chung-Len Lee

Sponsor:National Science Council

Keywords:Poly-Si Thin Film Transistors, Poly-Si Thin Thim, Poly-Si Oxides, Rapid Thermal

                Processing



      This project is composed of three subprojects:(1) Growth Technology of Poly-Si Thin
Films for Poly-Si Thin Film Transistor Applications;(2) Study on Preparation Technologies of
Dielectric Films for Poly-Si Thin Film Transistor Applications ;and (3) The Study and
Applications of Poly-Si Thin Film Transistors.
      The first subproject is proposed and to be executed by Prof. H. C. Jeng. The contents of
the sub-project is to investigate how to prepare, especially at the low temperature, poly-Si thin
films of large grain sizes and a high quality. Laser recrystallization will be investigated as the
main technique to achieve the above purpose.
      The second subproject is proposed and to be executed by Prof. C. F. Yeh. The contents of
the subproject are (1) to improve the liquid phase deposition (LPD) technique to grow LPD
oxide of a high quality to be used in the poly-Si thin film transistors for the application of
AMLCD;and (2) to investigate new thermal oxidation techniques to grow poly-Si or amorphous
oxides of new structures for the applications of VLSI SRAM and NVM.
       The third subproject is proposed and to be executed by Prof. C. L. Lee, The content of the
subproject are to fabricate, based on the results of the above two subprojects, ploy-Si thin film
transistors, and to investigate the device and circuit models and the circuit applications of TFT.
NSC86-2215-E009-022
---------------------------------------------------------------------------------------------------------------------



Title:The Study and Application of Polysilicon Thin-Film Transistors (III)

Principal Investigator:Chung-Len Lee

Sponsor:National Science Council

Keywords:Polysilicon, Thin-Film Transistor, H2-plasma, Rapid Thermal Process, 4-value

                SRAM


       In this subproject, it is to study : (1) to make high performance ploy-Si thin film transistors;
(2) the device and circuit models; and (3) the circuit applications of the ploy-Si thin film
transistor. Specifically, it is to study:

    (1) The fabrication of nitrogen implanted polysilicon thin-film transistors and their physical
    and electrical characteristics;
    (2) The fabrication of fluorine implanted polysilicon thin-film transistors and their physical
    and electrical characteristics;
    (3) The fabrication of polysilicon Si3N4 thin-film transistors and their physical and electrical
    characteristics;
    (4) The application of the rapid thermal annealing process to polysilicon thin-film transitstors
    and the physical and electrical characteristics of the fabricated TFTs;
    (5) The fabrication of thin LPD gate-oxide polysilicon thin-film transistors and their physical
    and electrical characteristics;

    (6) Design and fabrication of a new structure TFT to reduce the anomalous off-current so that
    the TFT can be used in AMLCD as the switching element;
    (7) Design and fabrication of a novel vertical structure polysilicon thin-film transistors and
    their physical and electrical characteristics;
    (8) The device and circuit models of the Single gate and Double gate thin film transistors for
    HSPICE simulation;

    (9) The fabrication of a four-valued double gate SRAM cell.
NSC86-2215-E009-025
---------------------------------------------------------------------------------------------------------------------



Title:Advanced Video Coding Techniques for Interactive Multimedia Servces

Principal Investigator:David W. Lin

Sponsor:National Science Council

Keywords: Object-Based Video Coding, Image Segmentation, Optimal Video Coding,

                  Distortion-Rate Relations


      We investigate advanced video coding techniques for interactive multimedia services,
including object-based coding and suboptimal coding under a given standard. For object-based
coding, subjects of study include image segmentation into objects, coding of the objects, and
comparison with block-based coding. For optimal coding, we attempt to find models for the
video distorion-rate relations that are better than presently available models, and to use them in
quantizer step size control schemes for better video quality.
NSC 86-2221-E009-019
---------------------------------------------------------------------------------------------------------------------



Title:Signal Source Coding for Wireless Communication

Principal Investigator:David W. Lin

Sponsor:National Science Council

Keywords: IS-54/136, VSELP Coding, H.263, Wireless Video



       We consider the North American mobile communications interim standard IS-54/136 and
investigate its speech coding and decoding method. We implement a realtime speech codec in
support of the goals of the integral project. We also investigate standard-compatible ways of
improving the coding and decoding method, in the sense of better speech quality or lower
comlpexity or more graceful degradation under channel fading and noise interference. The
intended length of study is three years. In the first year, we have studied the basic codec
algorithm, begun realtime implementation work, and researched into some codec improvement
methods. In the second (current) year, we are continuing the realtime implementation and codec
improvement studies. In the third (proposal) year, we will focus on system integration for the
integral project. Tunings of the codec algorithm may be needed here and there along the way.
       For this third year, we also consider a forward-looking research subject, namely, wireless
digital video coding and transmission. We will consider ITU-T‘s low bitrate video coding
standard H.263 which is currently in the making. We will investigate its complexity as well as
performance and consider possible ways of improving the codec algorithm. And we will study
the effect on video quality due to wireless transmission and plan for potential future realtime
transmission experiments.
NSC 86-2221-E009-050
---------------------------------------------------------------------------------------------------------------------



Title:VLSI Implementation of a High Speed Huffman Decoder

Principal Investigator:Wen-Zen Shen

Sponsor:National Science Council

Keywords:Huffman Code, Data Compression, Decoder, Programmable Logic Array(PLA),

                Digital Communication


       Huffman coding is a kind of lossless data compression technique. It is widely adopted in
digital video compression system, digital communication network, and High-Definition
Television (HDTV) system etc.. However, the implementation of a high speed Huffman decoder
is very difficult in practice. Since the incoming codelength is variable, the Huffman decoder has
to decode sequentially. Traditional parallel processing techniques can not be applied to
implement the Huffman decoder.
Conventional Huffman decoders can be classified into two types :
    1. Bit-serial decoder : the throughput rate is 1 bit per cycle.
    2. Parallel decoder : the throughput rate is 1 codeword per cycle.
      For modern digital communication networks, the data transmission rate may exceeds 200
M bit/sec. Conventional Huffman decoders can not achieve such a high throughput rate under
current IC technology. The aim of this project is to develop a VLSI architecture for the Huffman
decoder with throughput rate over 200 M bit/sec.
      Conventional parallel Huffman decoders use Programmable Logic Array (PLA) as a
codeword lookup table. Based on the same scheme, we will propose a new architecture which
can decode more than one codeword per cycle. We will also develop new algorithms to modify
the PLA so that a throughput rate of 6 bits per cycle can be achieved. Therefore, when our
proposed decoder is running at 40 M Hz, the throughput rate will easily exceed 200 M bit/sec.
      In this project, we will develop the algorithm and architecture of proposed high speed
Huffman decoder and finish the layout design. All the necessary analysis and simulation will be
carried out to verified the correctness s of our design.
NSC86-2221-E009-052
---------------------------------------------------------------------------------------------------------------------



Title:A Study of Power Estimation and Low Power Synthesis at Gate Level
Principal Investigator:Wen-Zen Shen

Sponsor:National Science Council

Keywords:Power Estimation, Automatic Power Characterization, Estimation Of Transition

                Probability, State Assignment For Low Power


       In this project, we will study four topics about power estimation and low power system.
The first one is to build an automatic power characterization system. We know that power
characterization is a complicated work and cell libraries are renewed very often due to the
continuing advance of semiconductor technology. Thus, it is necessary to develop an automatic
power characterization system. In this topic, we shall build such a system based on the power
consumption models developed in the last year. In the second topic, we would investigate a
transition probabilistic-based algorithms for estimating transition probability considered only
zero delay model. In these cases, power estimations do ignore the glitches and hazards, which are
caused by gate delay, and underestimate the power consumption. In this topic we would estimate
the transition probability by considering the general delay model and the spatio-temporal
correlation of signals.
      The third topic is to modify the power estimation program embedded in the logic synthesis
system SIS which is developed by U.C. Berkeley. In the original program, they use the product
of the signal probability being one and zero as the corresponding transition probability. In face,
this would ignore the temporal correlation of a signal. Thus, we would take the temporal
correlation of signal into account to improve the accuracy of power estimation in SIS. In the last
topic we would develop a state assignment algorithm for synthesizing a low power finite state
machine. Given a finite state machine, we would analyze the state transition probability first
according to the characteristics of input signals. Then, we reduce the Hamming distance between
the binary representations of frequently transition pairs of states. This encoding strategy could
reduce the transition at present state lines and would probably cause fewer gate transitions in the
combination portion of the finite state machine.
       The goal of this project is to build a low power design environment. The four topics above
are the important parts of this environment.
NSC86-2221-E009-009
---------------------------------------------------------------------------------------------------------------------



Title:Discrete Fourier Transform for OFDM Demodulator of Eureka-147

Principal Investigator:Wen-Zen Shen

Sponsor:Computer and Communication Research Laboratories, ITRI

Keywords:DAB (Digital Audio Broadcasting) , OFDM (Orthogonal Frequency Divided

                Multiplex), DFT (Discrete Fourier Transformation)
       The introduction of Compact Disk has increased the audio quality for the consumer
drastically. This ate-of-art quality will become essential for the broadcasting service. In order to
digitalize the communication link in the chain from a digital studio to the digital sound system at
home, the Digital Audio roadcasting system was developed. The DAB system is set to replace
the existing AM/FM broadcast networks. The new system offers superior CD sound quality,
excellent mobile reception, easy program-election and additional data service.
       A standard for the broadcast system has been developed in the European DAB Eureka-147
project. This DAB system uses the COFDM(coded Orthogonal Frequency Divided Multiples)
method as the channel modulation and coded system and supports three transmission mode. In
mode I, which is suited for Single Frequency Network broadcast, each symbol contains 1536
carriers. In mode II, to be used for local broadcasting, the symbols take 384 carriers while in
mode III, or satellite mode, the symbols contain 192 carriers. Each audio symbol takes 1.25ms.
       A key feature of OFDM is that the demodulation can be done using a DFT(Discrete
Fourier Transformation). To implement the real-time channel demodulation function for DAB
Single Frequency Network mode, we must finish the 1536-ponit complex DFT in 1.25ms. Since
we should compute such a long-length DFT rapidly, a dedicate DFT processor chip rather than a
set of general purpose processors is needed.
      In this project, we want to design a DFT processor chip which is dedicated to the channel
demodulation function of DAB Eureka-147 standard. We will choose a suitable algorithm for
long-length computation. high processing speed and various data lengths. Using this algorithm.
an hardware architecture for VLSI implementation will be developed and the chip area gate
count and power consumption are all important design issues. Finally we will finish the circuit
and layout design of this DFT processor under our current VLSI design environment.


---------------------------------------------------------------------------------------------------------------------



Title:A Baseband Chip Set for Digital Cellular Phone(III)

Principal Investigator:Chuen-Shen Shung

Sponsor:National Science Council

Keywords:



       The past few years have seen rapid increase in the demand for personal and mobile
cellular phone and cordless phone products. Each geographical region has developed its own
standard for wireless communications (such as GSM, IS-54, CT2, DECT, JCT, etc.). In this
project, we intend to develop a baseband chip set for IS-54, the North America Digital Cellular
(NADC) standard. Since we will not be developing the RF module, we plan to rely on HP high
frequency equipment to emulate the RF section. Furthermore, due to limitations in manpower
and time, we will focus on the implementation of the digital mode of the mobile station.
      The important topics in our project include speech coding, channel coding and protocol
control, digital modulation, de modulation and timing recovery, equalization, and hardware
integration. This three-year project will be jointly collaborated by seven professors under five
sub-projects. The present application is for the third year. In addition to designing ASIC or
programming DSP for each functional module, we also plan to develop two subsystems --coding
board and modulation board, to perform system development and testing
       There are three possible directions after accomplishing this project : (1) combine with RF
module and perform field test for the whole mobile station, (2) collaborate with industry to
transfer the technology       into product development, (3) work on the baseband chip set for
CDMA (IS-95) standard and compare it with IS-54. the protocol control.
NSC86-2221-E009-049
--------------------------------------------------------------------------------------------------------------------



Title:Power Estimation through Simulation and Low Power Design (II)

Principal Investigator:Chuen-Shen Shung

Sponsor:National Science Council

Keywords:



      Low power circuits and systems design has become an important research topic recently.
The driving force of this includes the demand to increase portability, and to alleviate the
packaging and reliability problems faced by VLSI circuits. The most important attribute in
CMOS power dissipation, the dynamic power, has to do with the supply voltage, total
capacitance, operating frequency and activity factor. Therefore, low power design research can
be con-ducted in various levels, including algorithm, architecture, circuits and processing
technology, etc.
       There are two goals in our project. The first is to perform power estimation through
simulation. Power estimation is the key to low power design and synthesis.The second is to use
the Reed-Solomon codec as an example to exercise some low power design techniques at the
architecture and circuits level. Both of these two tasks are part of our on-going research efforts in
low power design.
       In the first year, we have improved our previous power estimation tool, and started some
efforts on probability based techniques. On the Reed-Solomon codec side, our progress was
slower than previously expected. There were several newly proposed architectures which we felt
that we should look into. Also, previously we thought we would only be working on the
architectural aspects for low power design. However, we found that there was room for
improvement at the circuit level as well. We will be working on these aspects first before
entering architectural level design.
NSC86-2221-E009-012
---------------------------------------------------------------------------------------------------------------------



Title:Modulation Techniques and System Integration for Wireless Communications(II)
Principal Investigator:Chuen-Shen Shung

Sponsor:National Science Council

Keywords:



      Wireless Communications are still in high demand. Our sub-project is focused on the
modulation part in the IS-54 hardware implementation project. The progress in the first two
years has been very well, and we are planning to continue on the integration testing of our
hardware in the third year. In the second year we have spent lots of effort on system integration,
including integrating the simulations at the algorithmic and hardware description level, Verilog
to FPGA partitioning and synthesis, and attempted other related hardware development tasks
such as the PC boards and RF modules. In the third year, we will integrate the results of other
sub-projects, and perform system testing.
NSC86-2221-E009-052
---------------------------------------------------------------------------------------------------------------------



Title:A Study on The Process of Diffraction Device

Principal Investigator:Shyang Su

Sponsor:Electronics Research and Service Organization ITRI

Keywords:



       It is the purpose of this investigation to manufacture an 8-step diffractive component. The
required efficiency of diffraction is above 50%. The step structure where the critical dimension is
above 0.5 μm is finished by the polysilicon etcher with the exposed photoresist mask. For the
structure with the feature size under 0.5μm, the chemical vapor deposition system is utilized to
form the spacer of silicon oxide and then the etching of the last step is accomplished by the oxide
etcher. The exposures are performed through the I-line stepper and the exposure masks are made
by the E-beam lithography.


--------------------------------------------------------------------------------------------------------------------


Title : The Study Of Si/SiGe Material and Physical Characterization
Principal Investigator : Simon M.Sze
Sponsor : National Science Council

Keywords :
      This project is for three years to investigate the material analysis and physical
characterization of SiGe material. We will use the UHV/CVD(Ultra-High Vacuum Chemical
Vapor Deposition) system and CME(Chemical Molecular Epitaxy) to grow SiGe material,
including SiGe quantum well and superlattice structures, and use SIMS、 X-ray diffraction 、
     、
TEM SEM 、           、 、
                AFM PL FTIR 、              、
                                   Raman Hall and PCD to analyze SiGe‘s characterization.
We will also use UHV/CVD system to study the Six Ge1-x/Si heterostructure on Ge(111)
substrate. We study the Ge film deposition, SixGe1-x film deposition, and SixGe1-x/Si superlattice
deposition. The growth condition, material and electical properties is discussed.
      First year, we will study the growth mechanism of SiGe epitaxial layer and characterize
SiGe material. Second year, we will investigate the physical phenomenons of SiGe
material(including the electrical 、optical and quantum characterizations). Third year, we will
study the SiGe quantum well and superlattice structures and fabricate the MODFET 、QWIP and
RTD devices.
The main research topics of this project are given as follows:
    1.Study the growth mechanism of SiGe material by UHV/CVD.

    2.Analyze the SiGe‘s composition using SIMS、 X-ray diffraction.

    3.Analyze the SiGe‘s defects、 dislocations and surface mophology using TEM 、SEM、
    AFM.

    4.Study the physical characterization of SiGe material using PL 、FTIR、 Raman and Hall
    measurements.
    5.Study the minority-carrier lifetimes using PCD(Photo Conductive Decay) technique.
    6.Investigate the quantum phenomenons of low temperature in high magnetic field and
    quantum hall methods.

    7. Study the phical phenomenons of SiGe‘s quantum well and superlattice structures.

    8. Fabricate the devices of MODFET、 QWIP and RTD.

NSC86-2215-E009-020
---------------------------------------------------------------------------------------------------------------------



Title:Physics and Technologies of High Temperature Superconducting Thin Film for Electronic

         Devices Applications

Principal Investigator:Tseung-Yeun Tseng

Sponsor:National Science Council

Keywords:Bandpass filter, Microwave, Anisotropic, Superconductor, London Theory,

               Ginzburg-Landau Theory, Step Impedance Resonator, Bolometer, Microbridge
      This is the third year project of the previous approval three-years research plan. This
project will be aimed to delvelop the high temperature superconducting bolometer applications,
microwave devices and the theory of microwave response of anisotropic high Tc
superconducting crystal. The project is divided into two parts which are described in brief as
follows.
(I) Applications for Microwave Devices and Studies of Microwave response Based on the
superconducting transmission lines, a system of bandpass filter will be established to do some
investigations systematically. It contains four major parts: (1) The simulation and design for the
basic resonant building unit (2) Design and simulation for bandpass filter system (3) Fabrication
of the device (4) Measurements and analysis. In part (1), we shall make use of step impedance
resonator (SIR) as the basic unit. The main reason of using SIR is that it can reduce the size of
the device and consequently enables us to get a better control on the whole system. For part (2),
the bandpass filter will be assembled by using building unit as established in part (I). The
characteristics of superconductors (such as the two-fluid model) will be taken into account
carefully in developing the system. Besides, the computer simulation software will be built
simultaneously. In part (3), we will fabricate the bandpass filter using YBCO as conducting layer
and gold as ground layer. The YBCO thin films will be deposited on [100] LaAlO3 or A12O3
substrate using DC sputtering technique to satisfy the requirements of high critical current
density and low surface impedance. To further reduce the surface impedance, buffer layers such
as CeO2 or YSZ will be employed. In part (4), the surface impedance of the YBCO films will be
measured using parallel resonant technique and can be evaluated with the help of two fluid
model and impedance transformation equations. Also, the dielectric constants of LaAlO3 and
Al2O3 substrates will be measured using ring resonator circuits. The bandpass filter system will
be placed in a test housing and cooled down to 77K and then be measured using HP8510C
network analyzer.
       We will also theoretically study the microwave response of strong anisotropic
superconductor based on the anisotropic theories such as the London theory and various models
in the literature. The geometry influence on microwave response of anisotropic superconducting
crystal in the mixed state such as the vortex-liquid and solid will be investigated in great detail.
Also, by studying superconducting thin film along with substrate, the multilayer structure is
investigated. The various two-fluid models will be utilized to understand some interesting
phenomenon such as the possible substrate resonance behavior and so on.
(II) Applications for Bolometer
In this study, it contains three parts:
      First, a high responsivity of superconducting bolometer will be fabricated by using
prepatterning method. In contrast to conventional process of fabricating bolometer, we pattern
the wafer first and then deposit the superconducting films. Since the film grows all over the
patterned wafer, more incident light will be absorbed and the responsivity is expected to increase.
Such a structure would be further reconstructed by using the so-called meander-line hanging
method.
      The nonbolometric mechanism will be investigated in the second part. This nonbolometric
response as well as the usual bolometric response have been observed. The nonbolometric
response, however, still remains unclear. Many workers have attributed it to quasi-particle
tunneling effects. We will implement a microbridge bolometer to analyze its response and
investigate the possible physical mechanism. The dependences of the wavelength, film thickness,
and thermal conductance on the performance of the bolometer will be treated simultaneously.
The final part in this work is to fabricate large area thin film and bolometer array as possibly as
we can. It is then possible to explore the feasibilities of thermal image process on the basis of the
result of the bolometer array investigation.
NSC86-2112-M009-028
---------------------------------------------------------------------------------------------------------------------



Title:Development of Low-firing Z5U BME Barium Titanate-Based Dielectrics

Principal Investigator:Tseung-Yuen Tseng

Sponsor:Philips EBEI (Taiwan) Lted.

Keywords:



       The main purpose of this two-year research plan is to develop a new dielectrics based on
barium titanates of reduction-resistant compositions which have low sintering temperature and
retain the desired electrical properties after exposure of ceramic to a low oxygen partial pressure
atmosphere.
       The research items of this proposal are as follows:
    (1) Employing a small amount of flux or glass to lower the sintering temperature of Z5U
    BME dielectric ceramics down to~1200℃ in the first year plan and down to 1050℃ which
    are compatible with electrodes of Cu in the second year plan.
    (2) Studies of process-properties interrelationship of the dielectrics having low sintering
    temperature.


---------------------------------------------------------------------------------------------------------------------



Title:Development of Reactive Sputtered RuO2 Thin Film Resisters

Principal Investigator:Tseung-Yuen Tseng

Sponsor:Philips EBEI (Taiwan) Ltd.

Keywords:



       The main purpose of this research plan is to develop RuO2 thin film resistor by using DC
sputtering technique. The interrelationship between the processing conditions and properties of
the films will also be investigated. The research items of this proposal are as follows:

    (1) Employing DC sputtering technique to establish processing conditions of high quality
    RuO2 thin films.
    (2) Studies of structure-properties interrelationship of the films.
    (3) Assist PEBEI to establish the DC sputtering system.


---------------------------------------------------------------------------------------------------------------------



Title:Study on Fast Browsing and Indexing of Video Date

Principal Investigator: Sheng-Jyh Wang

Sponsor:National Science Council

Keywords:Karaoke-On-Demand, Interactive Audio/Video Over Networks,Image Processing,

                Image Compression



      This project is a subdivision of the integrated project: “Interactive Audio/Video over
Networks”. The goal of this project is to develop the necessary technique for browsing and
indexing video data, so that clients can quickly find the information they need among a huge
amount of data.
      In a complicated interactive system, servers have to provide a huge amount of data full of
variety. In this case, traditional ways for indexing and searching data are no longer suitable; new
methods are highly needful. In this project, with the help of image processing technique,we are
trying to find new methods for solving this problem.
       This project consists of 3 major stages. In the first stage, by using existing image
processing algorithms, a primitive system will be build to help clients to quickly browse and
search video data. The performance of this system is expected to be limited; defects, like block
effect and discontinuous movement, are expected to be common. However, this primitive system
can help us in understanding the major difficulties and estimating the complexity of a complete
system. In the second stage, efforts will be made to improve the performance of the system. New
methods for doing region-based compression and image segmentation will be studied and
implemented too. In the last stage, these newly developed algorithms will be combined with the
KOD (Karaoke-on-Demand) system and final adjustment will be made.
NSC 86-2221-E009-022
---------------------------------------------------------------------------------------------------------------------



Title:NSC Central Region Telecommunication Research Center Planning

Principal Investigator:Che-Ho Wei

Sponsor:National Science Council

Keywords:Telecommunication Research Center
      The purpose of establishing a NSC Telecommunication Research Center in the central
region of Taiwan is to coordinate the research manpower in universities for promotion of
telecommunication research and cooperation between academia and industry.
The aims and major tasks of the center are:

         (1) Collecting the data of the professors‘ expertise for planning the research directions

         (2) Proposing the telecommunication research direction and important topics
         (3) Enhancing the interaction between academia and industry to accomplish the
         cooperation between them
         (4) Strengthening the manpower development, and sponsoring technical conferences,
         workshop and training courses in telecommunication technology
         (5) Providing a channel for technology transfer between universities and industry
      In the first year, we put our emphasis on the area of wireless communication and then
extend to digital subscriber loop and communication network technologies in the later years.
NSC85-2217-E009-008
---------------------------------------------------------------------------------------------------------------------



Title:Demodulation and Synchronization Techniques for TDMA Mobile Radio

Principal Investigator:Che-Ho Wei

Sponsor:National Science Council

Keywords:Frequency Offset Estimateor, Timing Recover, Digital Tanlock Loop, Digital

                Celluar Radio


       The US digital cellular radio systems use a TDMA method and a p/4-DQPSK modulation
scheme. The receiver may use coherent, differential or discriminator technique for signal
demodulation. In the mobile radio, the demodulation of p/4-DQPSK signal is very difficult due
to the effect of Rayleigh fading and Doppler frequency shift in addition to the common additive
white Gussian noise. In the coherent demodulation scheme, we will adopt the digital tanlock
loop(DTL) for carrier tracking. The performance of the DTL will be analyzed and evaluated by
computer simulations. The architecture of DTL will be investigated to simplify the VLSI design.
The differential detection scheme is usually less complex than the coherent demodulator.
However, frequency-offset estimation and symbol timing recovery are still essential in the
differential detector. In this project, we are to investigate the algorithm and examine its
performance by computer simulation. VLSI design of the frequency-offset estimator and timing
recovery circuit will be completed for chip fabrication.
NSC86-2221-E009-053
---------------------------------------------------------------------------------------------------------------------



Title:Investigation and Implementation of OFDM/CDMA Mobile Radio Transceiver

Principal Investigator:Che-Ho Wei

Sponsor:National Science Council

Keywords:Digital Mobile Radio, OFDM, CDMA



       In the past few years, there have been research efforts on the TDMA and CDMA mobile
radio systems. The CDMA system provides a higher efficiency in spectrum reuse. However, the
data transmission rate is still limited by narrowband interference and severe inter-symbol
interference(ISI) in frequency selective fading channel. In this project, we investigate the
feasibility of the mobile radio system employing combined orthogonal frequency division
multiplexing(OFDM) and CDMA technique. The topic of the project include signal design and
coding technique of the down link(base station to mobile station) building blocks, system
simulation, performance analysis, error correcting technique with turbo codes, detection and
equalization technique, synchronization and interference suppression techniques. The three-year
project will be jointly collaborated by four professors and their graduate students. Each group
will design and implement a functional block. The functional blocks will be combined and test in
the final year.
NSC86-2221-E009-057
---------------------------------------------------------------------------------------------------------------------



Title : Theoretical Study and Hardware Implementation of Interference Suppression and
Synchronization Technique for OFDM/CDMA Mobile Radio (I)

Principal Investigator:Che-Ho Wei

Sponsor:National Science Council

Keywords:CDMA/OFDM, Frequency Offset Correction, Frame Synchronization, Narrowband

                Noise Suppression


       In this project, we shall investigate some new frequency offset correction, frame
synchronization and narrowband noise suppression techniques for OFDM/CDMA system in
mobile fading channel. In the OFDM system, the carrier synchronization is the most important
topic. A small frequency offset will cause great degradation of the BER performance. In the
study of frequency offset corrections, various frequency detection techniques for OFDM system
will be investigated. We shall compare their performance, complexity, acquisition range and
tracking speed. In addition, a new frequency offset acquisition method that can enlarge the
frequency acquisition range with fast speed will be presented. For frame synchronization,
emphasis will be put on the practicability of hardware implementation. A low-complexity frame
synchronization in OFDM system will be investigated. Besides, we will study the performance
impact caused by the narrowband interference on the OFDM system. Also we will investigate a
new scheme utilizing signal processing technique to suppress the interference.
NSC86-2221-E009-059
---------------------------------------------------------------------------------------------------------------------



Title:Data Formatting for Video on Demand

Principal Investigator:Kuei-Ann Wen

Sponsor:National Science Council

Keywords:Video on Demand, Digital Data, Data Format, Multimedia Compression



       For video on demand, excessive digital data include video, image, graphics as well as text
are combined and are being transmitted on limited networking resources, The information to
transmitted may be originated from different sources including VCR,V8,computer....etc. Thus, to
digitize them and to combine them as suitable format for video on demand is the project goal of
this subproject. In the second project year, we'll first aim at the demo system, the so called
Karaol on demand. Signals for this application including video, audio and text only. Being
grabbed from conventional MPEGI card, the video and audio data can be distinguished while the
text can't. We'll extract the text and make it the third accessible data.
       In consideration of real time. Hence, various compression will be applied to various data
and protocol should distinguish the priority for transmission. Thus, the project content for the
first year includes (1) Text ectraction (2) Multimedia compression (3) Simple protocol for
Karaok (4) Authoring.
      At the 3rd project year, we'll extend the multimedia compression to be a well define VOD
code and the protocol for VOD. And at the final year, we'll derive hardware implementation of
the VOD codec including the protocol control.
NSC86-2221-E009-073
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Title:Design of Error Control Codes for Wireless

Principal Investigator:Kuei-Ann Wen

Sponsor:National Science Council

Keywords:Cellular Mobile, Viterbi Decoder, Chip Design, Simulation System



     Abstract -- The group special mobile (GSM) digital cellular radio system, introduced in
European in 1991, is the first standardized cellular radio system to use digital transmission.
Among which channel coding is one of its key elements and convolutional coding was used for
GSM as it gives a good performance, that is the error correcting capability is high considering
the extra redundancy that the code has added. However, compared with the more common block
codes they do have one disadvantage, they are more difficult to decode. The decoding of an
output bit depends on the values of all previous decode Bits and hence heuristic decoding
procedures ( such as Viterbi decoding ) has to be used. All these considerations are the same for
the Dual-Mode Mobile Station -- Base station Compatibility Standard (IS-54).
       Hence the major goal of these project is to derive an optimum architecture of Viterbi
decoder of cellular base band system. The architecture of (a) dedicate chip, (b) microprocessor
and (c) DSP processor will all be designed. In order to make justication in the view of the whole
system, in this project, the simulation system for the whole IS-54 will be built and to fit for the
architecture design, the simulation environment will be based on microprocessor, DSP and
dedicate chip testing board. The simulation systems will focus on digital communication
elements in the first year, that is, speech codec, ECC and protocol control. Of which, speech
codec will be proposed as a coproject chaired by Prof. Lin; as for protocol control, it will be
handled in this project and be cochaired by Prof. Chang.
      To sum up, this sub-project will handle the Viterbi codec design, protocol control design
as well as the simulation system establishment for the cellular mobile based band system design.
NSC86-2221-E009-051
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Title:Interactive Audio/Video Over Networks

Principal Investigator:Kuei-Ann Wen

Sponsor:National Science Council

Keywords:Karaoke-on-Demand, Digital Karaoke, Interactive Video, Interactive TV



       The world of audio and video is going towards digital. One step further, interactive
capability is the trend of future audio /video systems. The goal of this project is to study and
implement an over-network interactive audio/video (A/V) system. Particularly, a
Karaoke-on-Demand (KOD) system is chosen as our first target, not only because Karaoke has
high commercial value in this and many other countries but also because it requires specific
functions that are not included in the ordinary Movie-on-Demand(MOD) system. Therefore,
there exist many research and development subjects to pursue.
       A complete KOD system is rather complicated and can roughly be divided into three parts:
Set-Top Unit (STU), network, and server. In order to construct a fairly complete system, the
entire project is divided into the following 7 sub-projects and a group of people are responsible
for each sub-project.(1)Audio signal processing: It handles MPEG audio compression and the
other specific audio functions of a KOD STU. (2) Video signal processing: It handles MPEG
video compression and the other video related topics.(3) Networking: The KOD network
configuration, communication protocol and security are designed and constructed in this
sub-project.(4) Server:A real-time, high-speed, high-bandwidth A/V sever is one of keys to the
success of an interactive A/V system. (5) Multimedia program authoring: This sub-project
produces the compressed audio /video /data bit streams to meet our system needs. (6) Image
processing part: In this subproject, image process algorithms will be applied to demanded image
browsing and fast search such that user interaction will be enhanced. (7) Prototype integration
and MPEG system design: The job of this sub-project is to integrate the products produced by
the other sub-projects into a working system. Although the common goal of all the above
sub-projects is together to build a KOD prototype, a portion of the related topics studied in some
sub-projects may not be included in the hardware prototype due to hardware constraints.
       The entire project would continue for four years. The target of the first year is to build a
basic KOD system using the off-shelf components with the help from all the sub-projects.
However, because of the time constraint, the enhanced components designed by the sub-projects
may not be completed in the first year. Therefore, in the second year, we assemble the advanced
features obtained from all the sub-projects and put them into the KOD prototype. These
advanced features may include vocal/instrumental music separation, local lyric display, local key
(tone) control etc. In the third year, we like to study the more advanced and complicated
problems associated with two-way real-time A/V communications, and implements a (nearly)
balanced two-way interactive A/V system for distance learning. In the final project year, we'll try
to transfer all the prototype system to mobile cellular and replace the speech signal to media
signal. The severe bandwidth constrain will stimulate great topics on wireless multimedia
transmission.
NSC86-2221-E009-017
---------------------------------------------------------------------------------------------------------------------



Title:Design, Characterization and Modeling Techniques of Deep-Submicrometer Devices (I)

Principal Investigator:Ching-Yuan Wu

Sponsor:National Science Council

Keywords:ULSI, Deep-Submicrometer Devices, Design, Characterization, Reliability

                Modeling


      This research project is proposed for the advanced studies on future ULSI devices,
including device scaling rules, reliability problems, device structure optimization, device
simulation and modeling, parameter extraction and RLC delay. The advanced devices under
studies include bulk MOSFETs, Flash EEPROM, SOI/MOSFET and MESFET.
NSC86-2215-E009-034
---------------------------------------------------------------------------------------------------------------------



Title:ESD Protection in Deep-Submicron CMOS Technology

Principal Investigator:Chung-Yu Wu

Sponsor:United Macroelectronics Corp.
Keywords:



       In the advanced CMOS technology, it is more difficult to design the ESD protection
circuits. This is because some process techniques like LDD (Lightly doped drain) and salicide
(Self-Aligned Silicide) used in deep-submicron CMOS technology cause serious degradation in
the ESD robustness OF CMOS ICs. Many IC fabrication companies have tried to solve the
problem of reliability issues. So far, some preliminary improvement techniques have been
developed, such as the use of silicide-blocking mask, ESD implant mask, and LVTSCR devices.
But there are still many ESD protection circuits to be explored to improve the ESD immunity of
future deep-submicron CMOS technologies. The aim of this project is to develop suitable ESD
protection techniques circuits for UMC 0.25               m advanced CMOS technology.


---------------------------------------------------------------------------------------------------------------------


Title:Design and Testing of Submicron High-Frequency Standard Cells for

         Telecommunications(II)

Principal Investigator:Jieh-Tsorng Wu

Sponsor:Chung-Hwa Telecommunication Laboratories.

Keywords:Integrated Circuits (ICs), Mixed-Singnal ICs, Standard Cells, BiCMOS, CMOS



       What very large scaled integrated circuits (VLSI) have done for the computers in the
1980's, digital/analog mixed-signal VLSI is doing for the telecommunications and signal
processing in the 1990's. However, the design techniques for high-speed mixed-signal ICs are
still not well developed in Taiwan. This project is a joint effect between the National Chiao-Tung
University and the Telecommunication Laboratories to develop a multi-purposed standard cell
library. The focus will be on the interface circuit cells and the high-frequency circuit cells. Those
mixed-signal cells can be integrated with digital VLSI to implement high performance
communication components.
       Circuits to be designed in this project include CMOS 8-bit 50 MHz analog-to-digital
converters, a CMOS Gaussian Minimum Shift Keying (GMSK) modulator, CMOS 100 MHz
Phase-Locked Loops, CMOS high-speed output buffers, CMOS 900 MHz radio-frequency
front-end circuits (including low-noise amplifiers, and mixers), a CMOS 50 MMz current-mode
ladder filter, a BiCMOS 2 GHz radio-frequency frequency synthesizer, and CMOS 40 MHz
gm-C Filters.
       All circuits under investigation will be carefully studied, designed, simulated, layouted,
verified, fabricated, tested, and characterized. Designs will be based on UMC 0.5 μ m
Double-Poly Double-Metal (DPDM) CMOS, TSMC 0.6μm Singl-poly Double-Metal (SPDM)
CMOS and 0.8μm DPDM BiCMOS technologies.
---------------------------------------------------------------------------------------------------------------------



Title:Monitor Multi-sync Circuit Design

Principal Investigator:Jiin-Chuan Wu

Sponsor:GVC Multimedia Technology Inc.

Keywords:



       This project performs the design of the multi-sync circuit of the monitor, and participates
in the testing and characterization of the fabricated chip. The specifications of this chip are:

*Supply voltage VCC=5V±10%。

*Horizontal sync input range:31.5KHz to 56KHz。

*Vertical syn input range:56Hz to 84Hz。

*0.6μm SPDM CMOS process。



---------------------------------------------------------------------------------------------------------------------



Title:Reduction of Pointer Adjustment Jitter in SDH Networks (II)

Principal Investigator:Jiin-Chuan Wu

Sponsor:Industrial Technology Research Institute, ITRI

Keywords:SDH, SONET, STM-4, IC Fabrication



      The innovation of using pointer adjustment to track the virtual container, within SDH
signals, has generated many benefits the will minimize the cost and complexity of network
equipment. However, due to the large inherent phase step associated with a pointer movement,
the SDH network has the potential of creating large jitter transients.
     This project is to analyze the STM-4 of SDH/SONET and try to present a architecuture for
STM-4 desynchronizer. Is the first half a year, we’ll synthesize a STM-1 desynchronizer and
implement by IC fabrication. Finally, we’ll try design a STM-4 desynchronizer too.



---------------------------------------------------------------------------------------------------------------------
Title : Study of High-Quality Dielectrics of Polysilicon Thin Film Transistors()
Principal Investigator : Ching-Fa Yeh

Sponsor:National Science Council

Keywords:Dielectric, Liquid-Phase Deposition, Ion Plating, Poly-Si Oxide



      This proposal is one of the subproject of the master proposal: "Study and Development of
Thin Film Transistor (TFT) Technologies." The aim is to study and develop the high quality
poly-Si dielectrics for TFTs.
       This project is to study and to develop the high quality low temperature and high
temperature dielectric thin films according to the applications in large area active matrix LCD
(AMLCD) and in SRAM as the poly load. For the low temperature dielectric, it is to use the
liquid phase deposition (LPD) technique to deposit Si oxides at the room temperature. The LPD
technique has been proved to be an effective method to prepare high quality oxides in our
previous research. In last year, we have polished the process by improving the deposition
apparatus, optimizing the deposition solutions and conditions, and by employing the post
annealing to further improve the quality of the deposited oxide films. In this year, we will further
improve the deposition apparatus, optimize the deposition solutions and conditions, and study the
reliability of the deposited oxide films. In addition, we will try to deposit oxide films by ion
plating for the application of dielectric in low-temperature-processed poly-Si TFT.
       For the high temperature dielectrics, in last year, we have used three methods to grow
poly-Si oxides. The first is to grow a composite polyoxide by first depositing an amorphous thin
film on the poly-Si film and then to oxide the amorphous thin film. The second is to use the RTP
method to oxidize the poly-Si in order to achieve the better quality polyoxide. The third is to
grow the poly oxide at a lower temperature of 800° C~850° C in N2O ambient. In this year, we
will further investigate the poly-Si oxides grown by N2O and NH3, and treated by hydrogenation,
nitridation and fluoridation.
NSC86-2215-E009-024
---------------------------------------------------------------------------------------------------------------------


Title : Development of Fluorinated Dielectrics()
Principal Investigator : Ching-Fa Yeh

Sponsor:National Science Council

Keywords: Fluorinated Dielectrics, Low Dielectric Constant



      Low-temperature deposited low residual stress and low dielectric constant insulators has
been increasingly important for multilevel interconnection. In order to attain above goals, it is
necessary to incorporate fluorine atoms into the dielectrics. In this project, we plan to develop
the deposition technologies of some fluorinated dielectrics including inorganic and organic
dielectrics in detail. The deposition mechanisms of fluorinated dielectrics and the relationships
between the properties of fluorinated dielectrics and deposition conditions will be investigated.
The optimum deposition conditions will then be developed to meet the requirements for
dielectrics in multilevel interconnection. We also plan to develop some new processes or
equipment to promote the feasibility of fluorinated dielectrics in future.
      The thermal stability and moisture-hardness of fluorinated dielectrics will be deeply
studied. Especially the effects of fluorine atoms on thermal stability and moisture-hardness will
be clarified. At last, the multilevel interconnection including fluorinated, metal and barrier layer
will be formed. The stressmigration and electromigration will perform on such a multilevel
interconnection to investigate the influence of fluorinated dielectrics on interconnection.
NCS86-2215-E009-043

				
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