# Large signal transistor_BJT_ circuit analysis - graphical method-

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```					1 - The dynamic behaviors of transistors – Large Signals analysis –Graphical
analysis

In Electronic I , emphasis was made on the design and analysis of DC transistor circuits
and in particular , methods for biasing these circuits .
In the present part of the electronic course ( Electronic circuits II ) , the dynamic
behavior of the various transistor circuits will be investigated . The word “dynamic
“ refers to the AC response of the transistor circuits . i.e. how will these circuits reacts to
an AC signal ( input ) , which is usually superimposed on the previously discussed
DC bias levels .
Analytically , the amplifying ability of a transistor was demonstrated in part I of the
current Electronic course ( section 4.2 ) . Here , we can further illustrate such ability ,
by using the following analogous hydraulic system , shown in Fig 1.1 .

Water
Tank

Contol input
Valve

Output

Fig 1.1

The liquid level in the tank represents VCC , and assuming that the valve initial status is
quarter opened ( This is equivalent to a bias of 25% of VCC ) , then it is clear that there
will be a steady flow of the liquid ( equivalent to the DC bias current in the transistor )
at the output of the system .
Now , In addition to the initial status , if the valve degree of openness is varied
periodically ( sinusoidal form ) by an amount of 5% , then as might be expected , and
depending on the size of the valve ( equivalent to hfe in transistors ) , the flow of liquid
at the output of the system will vary accordingly , by the same percentage . i.e. . for a
small input signal variation we have a large output variation ( proportional to the input )
, and that is exactly the case in transistor circuits . i.e. large variation in output currents
may be achieved as a results of relatively small variations in input currents .
The methods for analyzing transistor circuits may be classified according to the degree
of exactness of results required . For large signals and low frequency applications ( e.g.
power amplifiers ) , exactness of results are not so critical and thus simplified approach
may be used , however for small signal and or large frequencies applications , exactness
of results become of great importance and thus more advanced analytical approaches are
required .

2 - Large input signals and Mid band frequency transistor circuits analysis .

D.C bias methods for large signals amplifiers were discussed in Electronic I ,
However practical aspects ( how are these type circuits are used in practice ) concerning
these types of circuits were not covered in the same course .
In practice and if we are to use such circuits as amplifiers , then there is a need for
additional measures which have to be taken in order to make sure that such circuits
will perform well . The following are outlines of some of these measures :

2.1 The use of infinite bypass capacitor .

2.1.1 The general case

Recall that in a typical common emitter amplifier circuit , the use of the Emitter resistor
is for providing a better stability of DC bias for the circuit against variations in the value
of HFE . For this reason , including RE is essential for DC biasing purposes . On the
other hand , for AC applications , the use of RE will limit the available output voltage
swing of the amplifier ( Max possible swing will be limited to VCC - VE ) making it
less efficient . i.e. we need a method which will keep RE for DC conditions but will
remove it for AC conditions . Such a task can be achieved using what is called the
infinite bypass capacitor as shown in Fig 1.2 ;

<
iC
RC

iB
VCC
VBB

RB           RE
iE

Fig 1.2
The DC load line can be obtained as before , this is because the capacitor acts as an
open circuit under DC condition . namely the intersection with VCE ordinate at, VCC,
and a slope of    -1/(RC +RE) .
On the other hand the AC load line can be obtained by considering the AC output
voltages and currents components as follows :

ic + v ce / RC      =        0            -----------          (1)
and since                     iC      = ic+ ICQ           -----------                (2)
and                          vCE      = vce + VCEQ        -----------                (3)

then it follows that
iC - ICQ = - 1/RC * [ vCE - VCEQ ]                   ---- (4)
at    vCE =0 ,      iC max = ICQ + VCEQ/ RC                            ---- (5)
and at   iC=0 ,      vCE = VCEQ + RC * ICQ

i.e. the AC load line will have a slope of -1/RC ( - 1/ Rac ) and intersections with the x
and y axis as shown in the following diagram :

iCmax

AC Line
VCC/(RC+RE)

Q Point

Slope=
DC Line
VCEQ
1/Rac

ICQ RC       VCC

And since both the DC and AC conditions have to be satisfied , it follows that the Q
point for both lines has to be the same ( when reducing the AC signal to zero we should
revert back to the Q point of the DC load line ) .
i.e. we can solve the equations of the DC and AC load lines to reveal the Q point . It is
clear that the maximum possible swing of the output current is determined from the
location of the Q point on the lines .

2.1.2     The maximum optimum possible output swing .

Such condition is characterized by the fact that , in the case of common emitter circuit ,
the base resistors ( or base bias voltage VBB ) are allowed to vary to achieve the
absolute maximum possible swing by the amplifier in question .

In order to obtain maximum possible AC swing ( assuming that R1, R2 - or VBB - will
allow that to occur ) , the Q point should be placed at the middle of the AC load line ;

i.e.              iC max = 2 ICQ                                        .....      (6)

from (5) we can write

2 ICQ = ICQ + VCEQ / RC
i.e.              ICQ = VCEQ / RC          ( or VCEQ/ Rac )    ......    (7)

Analytically ICQ and VCEQ may be obtained by solving equations (7) and the

VCC = VCEQ + ICQ ( RC + RE )                    which reveals ;

ICQ ( for Max swing ) = VCC / ( 2 RC + RE )

= VCC / R ac + R dc                     ......    (8)

and            VCEQ = VCC / ( 2 + RE / RC )

= VCC / ( 1+ R dc / R ac )                ......   (9)

Graphically , the Q point ( for maximum optimum swing ) may be obtained by
executing the following procedure:

(1) Constructing the DC load line

(2) Constructing the line iC RC = v CE ( from equation 7 ) ( or iC Rac=vCE)
The intersection of the two lines will yield the Q point

(3) The AC load line is then drawn passing through Q and at a slope of -1/RC
( or -1/Rac )
(4) The operating conditions ( i.e. VCC etc. . ) should be chosen so as not to
exceed the maximum collector power dissipation .

Example :     In the following transistor circuit :
find the Qpoint for maximum optimum possible swing in the output current without and
with an infinite capacitor connected across the Emitter and calculate the values of R1
and R2 under such conditions
R!                1K Ohms
HFE=100

15 V
R2
500 Ohms
CE

Without the inclusion of CE ;

ICQ = VCC / ( R ac + R dc )
and since R ac = Rdc = 1 K + 0.5 k = 1.5k
it follows that ICQ for maximum possible swing = 15 / 3K = 5 mA ( see equation 8
above ) , and the maximum possible swing = 10 mA P-P . The DC and AC load lines are
plotted as follows :

iC (mA)
10

7.5               iC= vCE/1.5

5          o Q point
lines

0    7.5     15           vCE (V)

Including CE ,    then Rac = 1 K and Rdc = 1.5K

The same calculation will apply for determining the value for ICQ ( = 6 mA ) ,
however , the maximum possible symmetrical swing of the output current will increase
to 12 mA Peak to Peak as illustrated in the following diagram :
iC (mA)
12                        iC= vCE/1
10
7.5

6          o Q point
5

vCE ( volts)

0       6    12 15

Note that the values for R1 and R2 will not be equal in both cases and should be
calculated accordingly using the DC. Analysis of Part I of the electronic course .

2.2    Using an infinite coupling capacitor .

In practical amplifier design , it is often required to block the DC component from the
load . This is usually achieved by means of connecting a capacitor ( called the coupling
capacitor ) between the amplifier output and the load . as shown in Fig 2.3 .
The DC load line for the shown circuit can be written as follows :

<

RC
CC
iB
VCC
VBB
Rl
RB            RE        CE
iE
Fig 2.3

VCC = iC ( RC + RE ) + v CE                            ....... (10)

However , the ac load line can be written as follows :

(RL // RC ) ic = vce                                            .......   (11)
( since the resistance seen by the collector is RL // RC )

or
iC - ICQ = - (RL + RC ) ( vCE - VCEQ ) / ( RL * RC )                .... (12)

Similar procedure can be used as the bypass capacitor case , for example , for
maximum possible symmetrical swing :

iC = v CE / ( RL // RC )                            ........       (13)

Also analytically , by solving the above equations we can write :

ICQ = VCC / (R dc +Rac )                              ........       (14)

and VCEQ = VCC / ( 1 + R dc / R ac )                          ........       (15)

It should be pointed out at this stage that the maximum possible load current swing
may be calculated using the current divider principle as shown in the following
equation ;

iL = ic * RC / ( RC + RL )                              ......         (16)

Similar technique can be applied to transistor circuits configurations as will be shown
in the following example .
Example :
In the following circuit , find the operating point for maximum possible swing in the
output current ( max IL swing can be deduced from the max iC swing value )

R2               1K Ohms
IL
>
CC
1K             15 V
R1
500 Ohms
CE

ICQ = VCC / ( R ac + R dc )
and
VCEQ = VCC / ( 1 + R dc/ R ac )
or           VCEQ = ICQ * Rac  This is the equation of the line passing through
the origin and the Q point ( equation 13 )
i.e.           ICQ = 7.5 mA and VCEQ = 3.75 V

A sketch for the AC and DC load lines will be as follows :
AC LD Slope =
(-1/500 )
iC
mA

iC= vCE/500

7.5      Q

DC LD
(slope = - 1/1.5 )

3.75 V                        vCE V

iL max can be found by performing current division of iC max between RC and RL

Examples :

[1] Given the following circuit , find VBB for maximum ( optimum ) collector current
swing :

+6V

1K

HFE=100

1K
0.1 K
vi
VBB

Help ;
Determine the value of ICQ from equation ICQ= VCC / ( Rac + Rdc )
next use DC analysis to find the respective value of VBB

[2] In the following circuit , find :
a- R1 , R2 for ICQ = 10 mA ( not maximum optimum swing )
b- Max symmetrical swing in iC using the values R1 , R2 calculated in (a)
c- Draw the DC and AC load lines

<

0.15 K
R2                                HFE= 100

10 V

R1        0.1 K     CE

Help :
Use the DC analysis to find R1 and R2 when ICQ = 10 mA
Use the rule of thumb RB = HFE * RE / 10
Apply the respective formula for determining ICQ ( for optimum max swing )
Draw the lines as illustrated earlier

[3] In the following circuit determine the maximum ( optimum ) possible load current
swing .

R2              0.9K Ohms           =0.99
IL
>
CC
0.9K          10 V
R1
100 Ohms
CE

Help :
Use similar procedures as in the pervious two questions
Use current division of iCmax to find the maximum iL

[4] In the following circuit , find the maximum possible symmetrical vL swing and draw
the AC and DC load lines .
<         25V

1K
20K
HFE = 60

5K    2K        2K    vL

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