# Leakage DAC

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```					Modeling and Estimation of Full-Chip
Leakage Current Considering Within-
Die Correlations

Khaled R. Heloue, Navid Azizi, Farid N. Najm
University of Toronto
{khaled,nazizi,najm}@eecg.utoronto.ca
Introduction
   Leakage current has been increasing and, in some
cases, has become the design limiter
   Statistical process variations (mainly L and Vth) make
leakage statistical in nature
   Interested in the mean and variance of the chip leakage
   Leakage is also state-dependent, but not too strongly so

   Large leakage variance leads to chip yield loss
   Performance may vary by 30% but leakage varies by 5X
   Thus, leakage may become more yield-limiting than delay

   During process & chip design, we need to control the
leakage spread, i.e., to minimize the leakage variance

2
Low-Leakage Design
   By design:
   process development
   Body-bias
   Sleep transistors and multiple voltage islands
   Low-leakage libraries (circuit design)
   Drowsy states, etc.

   Most of this is standard practice today
   How can EDA help further manage the leakage?
   EDA should be able to accurately model and estimate full-chip
leakage statistics to empower low-leakage design
   This option should be available at an early or a late stage
of design

3
Background
   Full-chip leakage estimation is useful at different points
in the design flow:
   Early estimation: given limited information about the design
 Useful   for design planning (power budgeting)
   Late estimation: complete netlist, possibly circuit placement
 Useful   for final sign-off

   Work on “early estimation”:
   Narendra et al. & Rao et al.
 Did not handle logic-gate/transistor topologies and/or within-die
correlation

   Work on “late estimation”:
   Chang et al. & Agarwal et al.
 O(n2)   complexity (some refinements at the expense of accuracy)

4
Full-chip Leakage Model
   We propose a “Full-chip Leakage Estimation Model”
that considers:
   Logic-gate structures and transistor topologies
   Die-to-Die & Within-Die variations
   Within-Die correlation

   Our model has the following features:
   Accurate
   Computationally efficient (constant-time)
   Can be used early or late in the design flow

5
Hypothesis

   Hypothesis:
   Certain “high-level characteristics” of a candidate chip design
are sufficient to determine its leakage statistics

   All designs that share the same values of these high-level
characteristics have approximately the same leakage,
for large gate count

   Hypothesis confirmed by results

6
High-level Characteristics

7
Early Estimation vs Late Estimation
   Whether in Early or Late modes, the inputs to our
model are the same
   Shown in previous slide

is obtained:
   In Early mode:
 number   of gates, frequency of cell usage, and dimension of layout
are either “specified” or “expected” based on design experience
   In Late mode:
 number   of gates, frequency of cell usage, and dimension of layout
are “extracted” from the fully specified design

8
Process Information
   We focus on leakage variations due to channel length
(L) variations
   The effect of Vth variations on the leakage mean is known
(multiplicative term)
   The effect of Vth variations on the leakage variance is negligible
compared to L

   We assume that the mean (μ) and standard deviation (σ)
of L are known
   Die-to-die and within-die variances of L are also known
σ2 = σ2dd + σ2wd

9
Process Information
   Channel length L variations are correlated due to:
   Die-to-die (D2D) variations are totally correlated
   Within-die (WID) variations are spatially correlated

   We assume that the WID correlation function, r(r),
for L is known
   It gives the correlation coefficient between the lengths of two
devices separated by a distance r

   Total length correlation (D2D + WID) can be easily
obtained

10
Correlation Function

11
Library Information
   Our leakage model works for standard cell type designs
   A library of p standard cells is available

   Characterize every cell in the library for leakage (mean
and variance) using one of two methods:
   Monte-Carlo (MC) analysis, by varying L
 Good   accuracy, costly
   Analytical method, by fitting leakage (X) into functional form,
and determine analytically the exact leakage mean and variance
 Less   accurate, cheap

bL cL2
X  ae
   Result: mean (μi) and standard deviation (σi) of leakage
for every cell in the library, i = 1, …, p

12
Leakage Fitting – “Good”

13

14
Histogram: MC vs Analytical

15
Leakage Correlation
   We previously assumed that channel length correlation
is available from the foundry
   Leakage correlation depends on:
 Distance separating cells
 Types of cells

   Using the fitted functional form for cell leakage:
   We can determine analytically the leakage correlation between
gates of types m and n, where m,n = 1, …, p, given channel
length correlation. We call it a mapping fm,n(.)

rm,n r   f m,n r r 

16
Leakage Correlation: MC vs Analytical

   For all pairs of cells (m,n), we found that leakage correlation is
approximately equal to the channel length correlation

17
   Information about the actual design:

   Expected/extracted number of cells in the design
n   cells

   Expected/extracted frequency of usage of cells in the library
 for   cell i, αi = ni /n

   Expected/extracted dimensions of the layout area (chip core)
 Width      W and Height H

18
Full-chip Model
   The full-chip model
 a rectangular array of
dimensions H and W
 n identical sites, where n is
the total number of gates
 Each site is occupied by a
Random Gate (RG)

   What is a Random Gate?

19
Random Gate
   Similar to a RV, a RG takes as instances or outcomes
gates from the standard-cell library

   We require the discrete probability distribution of the
RG to be identical to the frequency of cell usage
   P{ RG = gate i } = αi       for i = 1, … , p

   Based on the RG, the Full-chip model is a template for
all designs that share the same high-level characteristics
   It covers the set of all such designs (recall hypothesis)
   We’ll show that this set converges (in terms of leakage)

20
Leakage of RG
   If the leakage statistics of the RG are defined,
Full-chip leakage estimation is possible
   Need: mean, variance, and correlation (or covariance) of RG

   These will depend on:
   means and variances of leakage of cells (library information)
   Channel length and Leakage correlation (process information)

21
Leakage of RG
p
   Mean:              i i
i 1
2
          
    i                      
p                               p
   Variance:        2
i
2
i
2
    i i 
          
i 1                              i 1     
p   p
   Covariance:    C r     m n m n f m,n r r 
m 1 n 1

22
Full-chip Leakage Estimation
   Recall the full-chip model is as an array of generic
“sites” to be occupied by RGs
   We determined the mean, variance, and correlation of
the RG leakage
 Call them μ, 2, and r(r)

   Then we can determine the full-chip leakage mean
and variance

23
Full-chip Leakage Estimation
   Assume that r(r) goes to zero at a distance D where D
is less than the chip core height H and width W
   Focus on within-die variations, for simplicity of presentation

   Let P be the chip core perimeter, and A its area
   Let d be the logic gate density per unit area (e.g. n/A)
   Then, the full-chip leakage mean and variance are given
by:
 I  n

 I2  2 2 d 2  r r r 2  Pr   Adr
D

0

24
Confirming Hypothesis: Test plan
   Consider a range of target gate counts
   For a given # gates
   Generate many circuits that share the same high-level
characteristics (satisfy the cell usage frequencies, etc…)
   For each circuit
 Placeit
 Use Monte Carlo on parameters to generate leakage distribution
 Measure the error in mean and standard deviation relative to our
estimate (Integral)
   Find the maximum/min error over all circuits
   Plot the two error extremes against that gate count

   See plot on next slide
26
Results

27
Confirming Hypothesis
   Two conclusions from plot:

   First, the high-level characteristics of a design
(which drive our model) are sufficient to determine
accurately its leakage statistics

   Second, the set of (possibly different) designs that share the
same high-level characteristics have approximately the same
leakage, for large gate count

   Note that this is an example of early estimation
(high-level characteristics were specified a priori)

28
Late Estimation
   We have also tested our model as a full-chip leakage
late estimator
   Synthesized, placed, and routed ISCAS85 benchmark circuits
   Extracted the sufficient high-level characteristics
   Used our model to predict leakage and compared results to MC
sampling
 Listed    error in standard deviation (error in mean is negligible)

c499     c1355   c432    c1908   c880    c2670   c5315   c7552   c6288
1.04%    0.41%   1.14%   0.36%   0.74%   0.52%   0.23%   0.34%   1.38%

29
Conclusion
   Full-chip leakage estimation is possible both at an
Early or a Late stage:
   Based on concept of Random Gate
   Has been verified for standard-cell type layouts
   For large gate count, accuracy is very good

   High-level characteristics of design are all that matters:
   Standard Cell leakage mean and variance
   Cell usage frequencies
   Leakage correlation function
   Chip core area and perimeter (dimensions)
   Number of cells in the design

   Further work is required to handle both timing and
leakage in a single estimator
30
Bibliography
   Siva Narendra, Vivek De, Dimitri Antoniadis, and Anantha
Chandrakasan. Full-chip sub-threshold leakage power prediction
model of sub-0.18μm CMOS. IEEE/ACM International
Symposium on Low Power Electronics and Design, 2002.
   Rajeev Rao, Ashish Srivastava, David Blaauw, and Dennis
Sylvester. Statistical analysis of sub-threshold leakage current for
VLSI circuits. IEEE Transactions on VLSI Systems, 12(2):131–139,
February 2004.
   Hongliang Chang and Sachin S. Sapatnekar. Full-chip analysis of
leakage power under process variations, inlcuding spatial
correlations. IEEE Design Automation Conference, 2005.
   Amit Agarwal, Kunhyuk Kang, and Kaushik Roy. Accurate
estimation and modeling of total chip leakage considering inter-&
intra-die process variations. IEEE International Conference on
Computer-aided Design, 2005.
31

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