A low-cost ASIC process for the future VLSI market
by
Mr Wang Jun
Seminar Notice
Date : April 6, 2005 (Wednesday) Time : 3:00pm
Location : Rm 603, Chow Yei Ching Bldg Abstract:
The rapid development of the integrated circuit (IC) industry has push the minimum line width on a chip into the sub-100nm region. However, the exponentially increased complexity in the mask fabrication process and IC design flow has led to an alarming increase in the ASIC developing cost. The cost of a full mask set for a new 90 nm ASIC fabrication is to reach 1 million US dollars. The high cost has begun to hold back the development of ASIC industry and led to a decrease in the sale of ASICs in the past several years. In our study, we apply design for manufacturability technology (DFM) into IC design and present a novel low-cost process for ASICs for the sub-100nm region, including both physical design methodology and fabrication approaches. Using the current wavelength=193nm microlithography system, the new process enables a minimum dimension as small as 65nm, while keeping fabrication cost of ASICs at the same level as for the current 130nm technology. Having a potential huge market, the new process can push the ASIC industry into the sub-100nm region without costpenalty.
Biography
Jun Wang received his BS degree in 1997 and his MS degree 2000 in electrical engineering from Shanghai Jiao Tong University. He is currently a PhD candidate in the Department of Electrical and Electronic Engineering at the University of Hong Kong. His research areas include ASIC design and process, microlithography, resolution enhancement techniques (RETs), analog IC design, design for manufacturability (DFM), design and process integration (DPI) for microelectronics manufacturing, and radio-frequency integrated circuit (RFIC) performance analysis.