Beyond the 1's and 0's of Digital VLSI Designs by Mr. S. K. Chow Date & Time : 26 June 2006, 11:00 am Location : Rm 603, CYC Building
Seminar Notice
Abstract :
Modern super chips are only possible because of advances in heirarchical abstractions of the igital system and modern CAD tools. However, as we enter the nano era, it takes more than a fancy tool suite to realise a successful commercial design. Technological complications and the sheer complexity of the designs require designers to have an understanding that goes beyond the virtual front. This presentation will attempt to look at some of these considerations and the implications to the designer's training.
Biography:
Mr. S. K. Chow started his career as a design engineer at Intel Corporation in the US working on some of the industry’s first generations of single chip telephony codec, both in NMOS and CMOS. Despite Intel’s legacy in microprocessors, telecom products were a lesser known but important part of Intel’s past. Subsequently he has developed analogue signal processing chips at EG&G Reticon, now part of Perkin Elmer. Since then, he has held various development and marketing positions with different industry leaders, including National Semiconductor and Cadence Design Systems. He has also taught for a few years at the City University of Hong Kong. Currently Mr. Chow works as an independent consultant for consumer and industrial product development. Mr. Chow is a graduate of Washington State University, holding a BS and MS in Electrical Engineering.