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Prelab 7a by stariya

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									Experiment #7

Digital to analog and analog to digital conversion.

In part A of this experiment we will investigate D/A converters. If
time is available we will investigate both an “R-2R” and a
“weighted resistor” D/A converter. If time is insufficient, we will
investigate only one of these D/A converters. Your instructor and
TA will announce in class which D/A converter(s) will be studied.

In part B of the experiment we will look at a “flash” A to D
converter.

Part A

The schematic drawing for the “R-2R” ladder D/A is reproduced
from Figure 1 of the lab manual.



 MSB         2R
                                                  Figure 1
             2R                              R - 2R Ladder D/A

             2R                                           Rf


  LSB        2R      R      R      R    2R            _
                                                                 +
                                                                     VO
                    2R
                                                      +




                                                                          1
The notations LSB and MSB on the left hand side of the figure are
meant to indicate that each of the four bit lines are connected to VR
(if the bit = 1) or connected to ground (if the bit = 0).

A better way to draw the circuit is shown in the following figure.
Note that this circuit is generally available as a single package.

A better way to draw the circuit is shown in the following figure.
Note that this circuit is generally available as a single package.

      +VR

                 MSB

            S3



            S2



            S1

                 LSB
            S0                                              Rf
                        2R   2R          2R   2R
                                                2R
                                                                  +
                         R     R          R          Vi +
                   2R                                            V0


                                   (a)




                                                                      2
                       R         R         R

            2R        2R        2R        2R        2R       2R




        A        S0        S1        S2        S3        B

                              (b)
                       FIGURE 15.2-2
R-2R Ladder: (a) circuit; (b) network available as a package




                                                                  3
The easiest way to analyze the circuit is by superposition i.e. find
the output due to each of the four bits. A bit whose value is zero
produces no output voltage. The output voltage caused by a non-
zero bit can be found by taking a Thevenin equivalent to the left of
the negative terminal of the operational amplifier. For example
let’s analyze the output due to the LSB = 1. The equivalent circuit
for this is shown in part a) of the figure drawn on the next page. In
this equivalent circuit, Vi is actually the voltage between the – and
+ terminals of the operational amplifier. The equivalent circuit is
further analyzed in b), c) and d. From figure d) we can easily see
that the output caused by the LSB is -VR/16 (Rf/3R). Note that if
we desire a positive output then the value of VR must be negative.

Figure e) analyzes the effect of the MSB. As expected the output
due to the MSB is eight times that of the LSB.




                                                                    4
                      d            c              b               a     2R

              2R          R                 R                R               +
VR                                                                               Vi
                 2R           2R             2R              2R



                                       (a)



                      d            c                 b            a     2R

                 R        R                  R               R               +

VR/2                      2R                 2R              2R                  vi



                                       (b)



                                   c                 b            a     2R
                          R                  R               R               +
       VR/4
                                                      2R               2R        Vi



                                                      (c)

                                                                                                                 Rf
                                        b                a       2R
                                                                                                   3R
                              R                  R                      +
                                                                                                        +
          VR/8                                               2R        Vi                                    +
                                                                                                        vi
                                                                                       VR/16



                                                                                      (d)




                                                                                                                 Rf
                 d        c                  b               a    2R
                      R        R                  R                                                3R
     2R              2R       2R                 2R               2R
                                                                                                             +

                                                                                            VR/2



                                                                             (e)




                                                                                                                      5
This experiment asks you to increment the digital input from 0000
to 1111 or from decimal zero to decimal 15. You are to design the
circuit so that the output = decimal input/5 V. This means that the
digital input 0000 should produce zero volts output and that 1111
should produce an output of 15/5 = 3 Volts. If we denote the
decimal input as W, the desired output Vout = W/5

As noted before, if we wish a positive output (3 Volts maximum)
VR must be negative. This presents a problem. The experiment
suggests that we use a counter to cycle the digital input from 0000
to 1111. The output of the counter that we use in the lab is
positive. The nominal value of a logical “1” is +5 volts.

How do we change the circuit to accommodate a positive value of
VR? The obvious solution is to connect the ladder network to the +
input to the operational amplifier. A circuit that can be used is
shown below:
                   Rx




    Ladder
    Network



What is the output from this circuit? As before, we can use
superposition to find the output. The output caused by the LSB is
VR/16 (1 + 0/Rx) = VR/16. (Note: Rx can be chosen to be
anything.)




                                                                      6
Likewise the output from a “1” in the MSB is VR/2. Therefore the
analog output corresponding to 1111 is VR/2 + VR/4 + VR/8 +
VR/16 = VR 15/16. If the counter output corresponding to a “1” is
five volts (it is actually slightly less than 5 volts) this creates
another problem. For VR = 5 V the output corresponding to 1111
is 5 (15/16) or about 4.6875 V. This is greater than the desired
value of 3 Volts. How do we fix this? We can add a voltage
divider at the input to reduce this value to 3 Volts. The appropriate
circuit is shown below.
                Rx




    Ladder
    Network



                      Ry




                                                                    7
The Thevenin equivalent that results for a 0001 input is shown
below:



                    Rx

                          -

                          +
          3R
    VR/16
                         RY




How do we choose the value of RY?

Build the D/A converter and measure the output as the input varies
from 0000 (decimal zero) to 1111 (decimal 15). Is the output
measured as exactly W/5? Plot the output versus input and do a
“best fit” to the data (using Excel) in the form of Vout = Voff + G W.
What is the value of G? Of Voff?

The design of the second D/A converter, the weighted resistor
D/A, should be straightforward. The circuit (copied from the lab
manual) is shown on the next page.




                                                                     8
     LSB
      R1                 Rf


      R2                 If = Is
             Is

      R3                            VO

                     +
      R4


      MSB



Your design requires you to specify the values of all resistors. You
will make the same set of measurements on this D/A converter as
you made on the “ladder” D/A converter.


An important parameter of a D/A converter is its RESOLUTION.
Defined as: The smallest increment in voltage that can be
discerned by the circuit. It depends primarily on the number of
bits in the digital word. In our example [of a 4-bit word R-2R
ladder converter], as we increase the input word from (0000) to
(1111) we form 16 steps of an analogue output from 0V [the first
step] to 3V [the last step] with 15 [number of words (16), minus
one] increases of 0.2 V each. That means the smallest increment in
V(out), the Voltage Resolution of the converter is 0.2 V. The LSB
has the weight of 1/(16-1) of the maximum output [for the (1111)
input]. The Percent Resolution is (1/15)x100 = 6.67%



                                                                   9
If the resolution is not sufficient, one has to use a converter with
more bits in the input word. A 10-bit D/A converter would have a
(1/1023)x100 ≈ 0.1% resolution.


Another specification of D/A converters is the ACCURACY of
conversion. It depends on the difference of the actual analog
output voltage and the theoretical output. This is a function of the
accuracy of the resistors in the ladder, the reference voltage source
(counter-HIGH output voltage) and in our case also the internal
voltage offset of the Op-amp (if not compensated).
As a practical matter
a converter should have accuracy better than ± ½ LSB.
That insures that accuracy and resolution are compatible.
What is the resistor tolerance that is necessary for a 4-bit D/A converter? Is it different
for the MSB and the LSB ? (how about for a 10-bit converter?)



Update: July 9, 2004




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