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A2k3ET_Q_ANS

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									            INDIAN INSTITUTE OF TECHNOLOGY, KHARAGPUR
                 End Autumn Semester Examination 2003
   Subject No. CS 43051             Subject Name : Comp. Org. & O.S.
              Time : 3 Hrs .                                                                  Full Marks: 100
                                    Date of Examination : 28th Nov.2003 (FN)

            No. of Students :130 (One Hundred Thirty) 3rd Yr of ECE ,IE, EE & EG Dept.

                                 [ Question CUM Answer Booklet ]
                                                                                                 Page 1 of 35
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                            Salient Points & important                      Instructions :
1. This Question paper consists of the following parts :

(a) Group A (compulsory) consists of a single question (Q. No.1) which consists of seven(7)
parts [a) . . . g)] of 4(four) marks each spread over two(2) pages. All of these parts are to be
answered in exact sequence as they appear in the question paper. If you happen to omit any of
these parts at least for the time being then you must keep adequate space for the later
answer. Any answer to any part of this (Q. No.1), if made OUT OF ORDER, WILL NOT BE
EVALUATED.

(b) Group B consists of four (4) questions Q 2. . . .Q 5.each of eighteen (18) marks spread over
three (3) pages. You are required to answer at most three (3) questions from this group (Group
B). Answer to each of your chosen question ( Q 2 . . . .Q 5) must begin on a new page. Answers
to all parts /sub parts of the same question MUST be grouped together at one place. If
answer to any part of any one of the questions (Q 2 . . . .Q 5) are found in somewhere else
THEN THAT ANSWERWILL NOT BE EVALUATED.

(c) Group C consists of two (2) questions Q 6 & Q 7 each of eighteen (18) marks spread over
two (2) pages. You are required to answer at least one (1) question from this group (Group C).
Answer to your chosen question (Q 6. OR Q 7) must begin on a new page. Answers to all parts
/sub parts of this question MUST be grouped together at one place. If answer to any part of
this question (Q 6. OR Q 7) are found in somewhere else THEN THAT ANSWER WILL NOT BE
EVALUATED.

(d) Hence you are required to answer a total of five(5) questions, Q.1 of Group A, any three(3)
out of the four(4) questions (Q 2. . . .Q 5) of Group B and one(1) from the two questions of Group
C in the manner as illustrated above.

2. Marks are indicated at the right hand bottom corner of each question.

3. Make your own assumptions wherever necessary clearly writing them at relevant places.

4. This question paper also consists of a five(5) page appendix APPENDIX - I i.e. this question
paper consists of a total of THIRTEEN(13) pages.

                                                                                                                   Contd. 2
            INDIAN INSTITUTE OF TECHNOLOGY, KHARAGPUR
                 End Autumn Semester Examination 2003
   Subject No. CS 43051             Subject Name : Comp. Org. & O.S.

                                 [ Question CUM Answer Booklet ]
                                                                                                 Page 2 of 35
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                                     Group A ( COMPULSORY )
Q1. (a) Compute 10 digit, 8’s complement Octal equivalent of -234(Decimal).
Clearly depict ALL steps.                                           [4]


Ans. 1(a)

    Step 1. Convert 234 to Octal Equivalent.

                   8|    234
                   8|     29 --------- 2
                   8|     3 --------- 5
                   8|     0 --------- 3

    Hence 234 in decimal  352 in Octal                          ------------ Steps = 2 Marks

    0|234 in Decimal in signed magnitude  0|352 in Octal in signed magnitude

      -|352 in 8’s Complement => 7 | 777
                                 0 | 352

                                 7 | 426 in 8’s Complement ---- Step = 1 Mark
         Expanding to 10 digits = 7|777777426
 Ans: - 234 in Decimal  7 | 777777426 in 10digit 8’s Complement in Octal -- 1 Mark




                                                                                                                   Contd. 3
            INDIAN INSTITUTE OF TECHNOLOGY, KHARAGPUR
                 End Autumn Semester Examination 2003
   Subject No. CS 43051             Subject Name : Comp. Org. & O.S.

                                 [ Question CUM Answer Booklet ]
                                                                                                 Page 3 of 35
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Q. 1 (b) Consider the following computer system :

i. It has got three(3) identical CPUs, none of which supports Multi-Tasking.

ii. It possesses a single Centralized O.S. that supports Multi-Programming.

iii. Processes are put in a GLOBAL set of five(5) Ready - Queues each having
     its own priority .

iv. Scheduling policy is round robin among the five(5) Global Ready - Queues
while within the same queue it is First Come First Served (FCFS).

v. Scheduled Processes are dispatched to one of the three(3) identical CPUs
whichever happens to be FREE.

vi. The system has got a centralized Virtual Memory having size of 32
Tera-bytes but a common physical memory of only 512 Mbytes size.

vii. It also possesses two(2) Printers, three(3) Disk Drives one(1) Keyboard
and one(1) Mouse.

Specify schematically a typical Process State Diagram of the aforesaid system.
Clearly label all states as well as transitions.                                            [4]
----------------------------------------------------------------------------------------------------
 Ans. 1(b)
                                                                                                      Running ON CPU # 2
                                                                   Running ON
             Ready Q#1                                             CPU # 1

                                                                                           Running ON
                                                                                           CPU # 3
               Ready Q#2
                                                                   Disk#1 Wait                              Printer #1 Wait
               Ready Q#3
                                                                   Disk#2 Wait                              Printer #2 Wait
               Ready Q#4
                                                                   Disk#3 Wait
                                                                                                            Keyboard Wait
               Ready Q#5

                                                                                                            Contd. 4
            INDIAN INSTITUTE OF TECHNOLOGY, KHARAGPUR
                 End Autumn Semester Examination 2003
   Subject No. CS 43051             Subject Name : Comp. Org. & O.S.

                                 [ Question CUM Answer Booklet ]
                                                                                                Page 4 of 35
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Ans. 1(b) [Contd.]

Possible State Transitions

  From State                                                                To State

  Any of the five (5) READY States                        Running State
                                          ( Whichever of the three CPUs is Free)
---------------------------------------------------------------------------------------

Any of the three (3) Running States     Any of the Six (6) Wait States
                                 ( Depending on the Service Requests)

N.B: Assumed that there is no WAIT state corresponding to the Mouse .

-----------------------------------------------------------------------------------------

 Any of the Six (6) Wait States               To the original Ready State
                                           ( On completion of Peripheral Service )
------------------------------------------------------------------------------------------
 Any of the three (3) Running States                     Terminate State



Marking Policy : States = 2 Marks,                          Transition Table = 2 Marks .


                                                                                                                 Contd. 5
            INDIAN INSTITUTE OF TECHNOLOGY, KHARAGPUR
                 End Autumn Semester Examination 2003
   Subject No. CS 43051             Subject Name : Comp. Org. & O.S.

                                  [ Question CUM Answer Booklet ]
                                                                                                  Page 5 of 35
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Q.1. (c) Depict schematically the structure of the ALU along with all its associated
optimal number of registers & F/Fs (Operand , Result & Status) which can be
a part of the CPU specified in APPENDIX I. Clearly justify the inclusion of each
storage unit attached with your ALU.                                                [ 2+2=4]
---------------------------------------------------------------------------------------------------------
Ans 1 (c )
                                                                                                  32 Bit Bus


                                                                   32
                                 32

                     Tri-State                       Operand                             32 bit
                     Buffer                          Register # 1

                                                                   32




                                                                32 bit Purely
                                                                Combinational
                                 32                                  ALU


                                                                              32


                                                                   Result (R)                         Flag F/Fs
                                                                   Register




               Marking Policy : Organization = 2 Marks , Associated Blocks = 2 Marks
                                                                               Contd. 6
            INDIAN INSTITUTE OF TECHNOLOGY, KHARAGPUR
                 End Autumn Semester Examination 2003
   Subject No. CS 43051             Subject Name : Comp. Org. & O.S.

                                 [ Question CUM Answer Booklet ]
                                                                                                 Page 6 of 35
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Q.1(d) Specify the complete memory hierarchy of the CPU specified in
APPENDIX I. What are the reasons (if any) that prevents each level of the
memory hierarchy from being split into two (2) separate parts namely Data
Memory & Program Memory?                                                                    [1+3=4]
-----------------------------------------------------------------------------------------------------------

Ans. 1(d) . The Memory Hierarchy for the given CPU [ 2 Marks ]
                                          CPU Registers

                                               Split Cache
                                                Memory

                                               Unified Main
                                                 Memory

                                           Unified Secondary
                                                Memory


Reasons that prevent each level of the aforesaid Memory Hierarchy from being split into
two (2) separate parts namely Data Memory & Program Memory are the following :

1. CPU Register Level : Lack of chip area to hold more than one instruction , however
in some modern day CPUs some on CPU instruction storage like Instruction Queue
exists.

2. Main Memory & Secondary Memory Levels : In order to have separate Program
Memory & Data Memory at these two levels , the system should possess dedicated /
separate Bus connectivity (Program Address Bus, Instruction Transfer Bus, Instruction
Fetch/Store Control as well as Data Address Bus, Data Transfer Bus & Data Read/
Write Control Buses) at each of these two levels which is expensive in terms of
additional hardware & controllability.

Marking Guideline : Each point 1 Mark
                                                                                                                  Contd. 7
            INDIAN INSTITUTE OF TECHNOLOGY, KHARAGPUR
                 End Autumn Semester Examination 2003
   Subject No. CS 43051             Subject Name : Comp. Org. & O.S.

                                 [ Question CUM Answer Booklet ]
                                                                                                 Page 7 of 35
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Q.1.(e) Assume that a Hard disc drive having the following specification is
connected to the CPU specified in APPENDIX I .

i. It has got two(2) disc platters i.e. three(3) recording surfaces.

ii. On each surface , a set of two(2) sectors each having a capacity of 1 KByte
forms a cluster.

iii. Data is transferred between the physical memory and the disc drive using
burst mode DMA .

iv. Data transfer unit between the physical memory and the disc drive happens
to be one cylinder at one go.

Specify the number as well as size in bits of ALL the interface registers that
need to be present in the disc drive interface, clearly highlighting the role played
by each of those registers in the data transfer activity.               [2+2=4]

-----------------------------------------------------------------------------------------------------------

Ans. 1(e) The following interface Registers are needed to be present in the disc drive
interface :

1) A Memory Address Register, 32 bit wide, needed to address the Memory via the
   Address Bus.

2) The write only Command Register , 32 bit wide, to receive commands via the Data
   Bus.

3) The read only Status Register, 32 bit wide, to signify the status via the Control Bus.

4) A Byte Count / Word Count Register , that keeps a count on the number of bytes
   transferred so far.

Marking Policy : Mentioning each of the above registers = 2 Marks.

                                                                                                                   Contd. 8
            INDIAN INSTITUTE OF TECHNOLOGY, KHARAGPUR
                 End Autumn Semester Examination 2003
   Subject No. CS 43051             Subject Name : Comp. Org. & O.S.

                                 [ Question CUM Answer Booklet ]
                                                                                                 Page 8 of 35
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Ans. 1 (e) [Contd.]

      Calculation of Byte Count Register Size :

      Data Transfer Unit = Capacity of 1 Cylinder

            = Storage capacity of 3 Tracks (one on each of the recording surfaces)
            = 3 X 2 [Sectors per Cluster] X 1 Kbyte [ Sector Capacity ] = 6 K Bytes

      Now to address 1 K byte one needs 10 bits , hence a minimum of 13 bits in order to
      access 6 K Bytes.

      Therefore size of the Count Register = 13 bits . [ Calculation = 1.5 Marks
                                                                     Correct Size = 0.5 Mark ]
 ---------------------------------------------------------------------------------------------------------
Q.1.(f) Specify by a diagram with appropriate labels, the typical structure of a
process control block (PCB). Isolate out the context of the process from within
the PCB.                                                                                    [3+1=4]
------------------------------------------------------------------------------------------------------------
Ans. 1 (f) The typical structure of a process control block (PCB)
                                              Process Identifier (PID)

                                           Process Priority & Privileges

                                             Current Process State &
                                              Communication Info.

                                          Pointer to Next Process in the
                                                      Queue

                                        Current Execution Status
                                        ( CPU Registers, Flags) +
                                         [ User Stack & System Stack ]
                                              + The LOCALS
                                           { THE THREAD }

                                                 The Virtual Space
                                              { Code + Global Data }

                                        Resource Usage Map & Pointers



                             Marking Policy : Thread Portion = 1 Mark            Contd. 9
                            Other Portions = 3 Marks to be awarded proportionately
            INDIAN INSTITUTE OF TECHNOLOGY, KHARAGPUR
                 End Autumn Semester Examination 2003
   Subject No. CS 43051             Subject Name : Comp. Org. & O.S.

                                 [ Question CUM Answer Booklet ]
                                                                                                 Page 9 of 35
----------------------------------------------------------------------------------------------------------------------

Q.1. (g) Suppose the CPU specified in APPENDIX I supports paged segments
memory management. The following information is also available about it’s
memory hierarchy :

i. Cache Line size = 4 bytes.
ii. Program Cache Capacity = Data Cache Capacity = 512 Kbytes.
iii. Approximately 30% of Program Cache and 40% of Data Cache remains
occupied at all time by the resident O.S. & other system programs.
iv. Main Memory Size = 1 GByte out of which 200 Mbyte remains occupied
at all time by the resident O.S. & other system programs.
v. Page Size = 4 Kbytes.
vi. User Program specifications :
• Single Code Segment of 1 Gbyte size.
• Two(2) Data segments each having 4 Gbytes size.
• Single Stack Segment of 512 Mbyte size.
Compute the following along with elaboration of ALL the computation steps:

i. The size of the Page Map Table (PMT) for each of the user segments.

Ans 1(g) i.
                       Page size = Frame Size = 4 Kbytes.

   User Code Segment Size = 1 Gbyte = 1024 Mbyte = 1024 X 1024 Kbyte

  No. of pages in the User Code Segment (Code PMT Size)= 1024 X 1024 / 4 = 256 K

     User Data Segment Size = 4 Gbyte = 4096 Mbyte = 4096 X 1024 Kbyte

  No. of pages in each User Data Segment (Data PMT Size)= 4096 X 1024 / 4 = 1024 K

   User Stack Segment Size = 512 Mbyte = 512 X 1024 Kbyte

  No. of pages in the User Stack Segment (Stack PMT Size)= 512 X 1024 / 4 = 128 K

Marks allocation : 2 Marks [ For any 2 Correct Answers award at least 1 Mark ]

                                                                                                                 Contd. 10
            INDIAN INSTITUTE OF TECHNOLOGY, KHARAGPUR
                 End Autumn Semester Examination 2003
   Subject No. CS 43051             Subject Name : Comp. Org. & O.S.

                                 [ Question CUM Answer Booklet ]
                                                                                                 Page 10 of 35
----------------------------------------------------------------------------------------------------------------------

Q. 1(g) ii. The maximum number of user frames that can be accommodated in
the Program Cache as well as in the Data Cache.                                   [2+2=4]
------------------------------------------------------------------------------------------------------------
Ans. 1(g) ii.

 Program Cache Capacity = 512 K bytes, 30% of which is occupied by the resident
O.S. & System Programs i.e. 70 % of it is free to hold user pages.

Therefore size of Program Cache available for user frames = 0.7 X 512 = 358.4
                                                       = 358 K bytes

 Frame size = 4 Kbytes, hence number of user frames that can be accommodated in the
Program Cache = 358 / 4 = 89 [ Eighty Nine (approx.) assuming No fractional
allocation ]

Data Cache Capacity = 512 K bytes, 40% of which is occupied by the resident O.S. &
System Programs i.e. 60 % of it is free to hold user pages.

Therefore size of Data Cache available for user frames = 0.6 X 512 = 307.2
                                                       = 307 K bytes

Frame size = 4 Kbytes, hence number of user frames that can be accommodated in the
Data Cache = 307 / 4 =76 [ Seventy Six (approx.) assuming No fractional allocation ]


                                                                                                                 Contd. 11
            INDIAN INSTITUTE OF TECHNOLOGY, KHARAGPUR
                 End Autumn Semester Examination 2003
   Subject No. CS 43051             Subject Name : Comp. Org. & O.S.

                              [ Question CUM Answer Booklet ]
                                                                                        Page 11 of 35
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                                                           Group B
This group consists of four(4) questions Q 2. . . .Q 5.each of eighteen (18) marks spread over
three (3) pages. You are required to answer at most three (3) questions from this group. Answer
to each of your chosen question (Q 2 . . . .Q 5) must begin on a new page. Answers to all parts
/sub parts of the same question MUST be grouped together at one place. If answer to any
part of any one of the questions (Q 2 . . . .Q 5) are found in somewhere else THEN THAT
ANSWER WILL NOT BE EVALUATED.
----------------------------------------------------------------------------------------------------------
Q. 2.(a) Consider the CPU specified in APPENDIX I. Specify a suitable
representation scheme for representing 32 bit signed BCD integers in this CPU.
Your scheme must enable its existing ALU to handle 32 bit signed BCD
operands normally i.e. without employing any additional hardware. Clearly justify
your choice with appropriate arguments.                                             [3+3=6]
----------------------------------------------------------------------------------------------------------
Ans. 2 (a) Assumptions:

 1. The BCD implies Binary Coded Decimal in which each decimal digit (0..9) is
      represented by a group of 4 (four) binary bits [ 0000 .. 1001 ].
 2. The CPU adopts r’s complement scheme to represent any type of signed data but its
      ALU essentially handles binary operands.
 3. The BCD is treated as essentially a special representation scheme for decimal
      numbers. Hence the best way to represent signed BCD is using 10’s complement
      scheme using 4 bit binary bits [0000..1001 ].
 4. There exists special library routines to handle BCD data.
 ---------------------------------------------------------------------------------------------
   Points 1 to 4 = 3 Marks to be awarded proportionately. Minimum 1 Mark
 -----------------------------------------------------------------------------------------------
 5. The general method adopted to handle BCD operands are the following :
          i)       Handle group of 4 bits together (starting from right most position).
          ii)      Treat the most significant / leftmost group of 4 bits as the sign digit.
          iii)     Sign digit = 0000  +ve Sign , Sign digit = 1001 (9)  -ve sign.
          iv)      While processing any digit (group of 4 bits) if it exceeds 1001 then add
                   0110 to it (BCD adjustment) and ignore the Carry out
          v)       In order to keep consistency with the MSBit ( the sign bit) sign BCD
                   digit is handled in the following manner to represent –ve sign :
               Step 1. Complement the sign digit group (0000  1111) .
               Step 2. Add 1010 [ 2’s complement of 0110] to the sign digit it becomes
                      1001. [Decimal 9].
          This point = 3 Marks Minimum 1 Mark depending on progress
                                                                                               Contd. 12
            INDIAN INSTITUTE OF TECHNOLOGY, KHARAGPUR
                 End Autumn Semester Examination 2003
   Subject No. CS 43051             Subject Name : Comp. Org. & O.S.

                                 [ Question CUM Answer Booklet ]
                                                                                                 Page 12 of 35
----------------------------------------------------------------------------------------------------- -----------------
Q. 2 (b) Consider two (2) floating point numbers A & B both represented in IEEE
754 single precision format and stored in the physical memory of the CPU
specified in APPENDIX I using big - endian notation. These two operands A & B
are to be multiplied to generate the result C which is also to be stored in the
physical memory employing little - endian notation. Answer the following :

i. Elaborate the storage formats of A, B & C using appropriate schematic in
a byte organized memory starting from the location A200 4000.
                                                                                       [2 × 1 + 2 = 4]
----------------------------------------------------------------------------------------------------------
Ans. 2 (b) i. The IEEE 754 single precision format :
                | Sign bit | 8 bits Biased Exponent | 23 bits Mantissa
Assumed  The sign bit is stored as the leftmost bit of the Mantissa [ 1 Mark ]

Representation Scheme in big – endian notation for A & B :                             [ 1+ 1 = 2 Marks ]

                   Location Address                         Content

                A200 4000               Biased Exponent of A
-------------------------------------------------------------------------------------
                A200 4001             Most significant Byte of A’s Mantissa
                                          (including sign bit) .
---------------------------------------------------------------------------------------
                A200 4002               2nd Significand Byte of A’s Mantissa
-------------------------------------------------------------------------------------
                A200 4003             Least significant Byte of A’s Mantissa
---------------------------------------------------------------------------------------
                A200 4004               Biased Exponent of B
-------------------------------------------------------------------------------------
                A200 4005             Most significant Byte of B’s Mantissa
                                          (including sign bit) .
---------------------------------------------------------------------------------------
                A200 4006               2nd Significand Byte of B’s Mantissa
-------------------------------------------------------------------------------------
                A200 4007             Least significant Byte of B’s Mantissa
---------------------------------------------------------------------------------------
                                                                                                                  Contd. 13
            INDIAN INSTITUTE OF TECHNOLOGY, KHARAGPUR
                 End Autumn Semester Examination 2003
   Subject No. CS 43051             Subject Name : Comp. Org. & O.S.

                                 [ Question CUM Answer Booklet ]
                                                                                                 Page 13 of 35
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Ans. 2 (b) i. [Contd.]

 Assumed  The result C is also in IEEE 754 single precision format stored starting from
the very next Memory Location [ 1 Mark ]

Representation Scheme in little – endian notation for C :                        [ 1 Mark ]
                Location Address             Content

                A200 4008             Least significant Byte of C’s Mantissa
---------------------------------------------------------------------------------------
                A200 4009             2nd Significand Byte of C’s Mantissa
-------------------------------------------------------------------------------------
                A200 400A             Most significant Byte of C’s Mantissa
                                            (Including Sign Bit)
-----------------------------------------------------------------------------------------------------------
                A200 400B             Biased Exponent of C
-----------------------------------------------------------------------------------------------------------
Q. 2 (b) ii. Specify the assembly language routine along with elaborate comments
[at least 50% credit reserved for comments] using the instruction set of
the CPU specified in APPENDIX I to accomplish the aforesaid floating point
multiplication. Clearly highlight your assumptions [at least 20% credit
reserved for spelling out correct assumptions ].                                            [8]
--------------------------------------------------------------------------------------------------------
Ans. 2(b) The Assumptions : [ 2 Marks ]

     1. Both the inputs A & B contain valid Data values i.e. no data verification is needed
        before the actual computation.
     2. The bias value is already stored in the Memory Location Bias with proper
        padding.
     3. The CPU accesses A, B as well as C using a single instruction via the 32 bit Data
        Bus.
     4. The processing carried out is purely binary in nature, the distinctions are made
        only in the flag settings.

                                                                                                                 Contd. 14
            INDIAN INSTITUTE OF TECHNOLOGY, KHARAGPUR
                 End Autumn Semester Examination 2003
   Subject No. CS 43051             Subject Name : Comp. Org. & O.S.

                                 [ Question CUM Answer Booklet ]
                                                                                                 Page 14 of 35
----------------------------------------------------------------------------------------------------------------------
Ans. 2 (b) ii. [Contd.]

          The Algorithm / Comments [ 4 Marks ]

Step 1. CPU Register $r1  Operand A.
Step 2. CPU Register $r2  Operand B.
Step 3. CPU Register $r5  Bias.

Step 4. If ($r1) [ A ] equals 0 THEN $r14  All 0 go to Step
Step 5. If ($r2) [ B ] equals 0 THEN $r14  All 0 go to Step

  // Both A & B happens to be NON Zero . Extract Exponent of A
Step 6A. $r6  ($r1) AND 11111111| (8 bit 1) 000……000 (24 bit 0)
Step 6B. $r6  Right Shift ($r6) Logically 24 Times
// Now $r6 contains the Biased Exponent of A

 // Extract mantissa of A
Step 6C. $r7  ($r1) AND 00000000| (8 bit 0) 111……111 (24 bit 1)
Step 6D. $r7  Left Shift ($r7) Logically 8 Times
// Now $r7 contains the Mantissa of A in signed magnitude form.

   // Extract Exponent of B
Step 7A. $r8  ($r2) AND 11111111| (8 bit 1) 000……000 (24 bit 0)
Step 7B. $r8  Right Shift ($r8) Logically 24 Times
// Now $r8 contains the Biased Exponent of B

 // Extract mantissa of B
Step 7C. $r9  ($r2) AND 00000000| (8 bit 0) 111……111 (24 bit 1)
Step 7D. $r9  Left Shift ($r9) Logically 8 Times
// Now $r9 contains the Mantissa of B in signed magnitude form.

 // Extract Result Sign from the Signs of the two Operands A & B
Step 8A. $r10  ($r7) AND 1|000000..0000 (31 bit 0) [Sign of A]
Step 8B. $r11  ($r9) AND 1|000000..0000 (31 bit 0) [Sign of B]
Step 8C. $r12  ($r10) XOR ($r11) ($r12) holds 0 for equal sign, 1 for unequal sign
                                                                            Contd. 15
            INDIAN INSTITUTE OF TECHNOLOGY, KHARAGPUR
                 End Autumn Semester Examination 2003
   Subject No. CS 43051             Subject Name : Comp. Org. & O.S.

                                 [ Question CUM Answer Booklet ]
                                                                                                Page 15 of 35
----------------------------------------------------------------------------------------------------------------------
Ans. 2 (b) ii. [Contd.]

          The Algorithm / Comments (Contd.) [ 4 Marks ]

Step 9. CPU Register $r13  ($r6) PLUS ($r8) [ The exponents are added]
Step 10. $r13  ($r13) MINUS ($r5) [ The Stored Bias].
Step 11. If ($r13) > Maximum Exponent ( Exponent OVERFLOW)go to ERROR.
Step 12. If ($r13) < Minimum Exponent (Exponent UNDERFLOW) go to ERROR.

// Neither Overflow NOR Underflow

Step 13A. $r7  ($r7) AND 0|1111111111..111 ( 31 bit 1) Remove sign of A
Step 13B. $r9  ($r9) AND 0|1111111111..111 ( 31 bit 1) Remove sign of B

Step 14. $r14  ($r7) MULTIPLIED with ($r9) with TRUNCATION
Step 15. Normalize & Round Off Result by shifting ($r14) and adjusting the Exponent ($r13)
accordingly.
Step 16. $r14  ($r14) OR ($r12) [ Adjust Sign ].

// Adjust Result

Step 17 A . $r13  ($r13) RIGHT SHIFTED Logically 24 Bits.
Step 17 B. $r14  ($r14) OR ($r13) biased Exponent stored at the LSByte

Step 18. Memory Location C  ($r14)

Marking Policy : For total Absence of Code deduct max. 2 Marks.



                                                                                                                  Contd. 16
            INDIAN INSTITUTE OF TECHNOLOGY, KHARAGPUR
                 End Autumn Semester Examination 2003
   Subject No. CS 43051             Subject Name : Comp. Org. & O.S.

                                 [ Question CUM Answer Booklet ]
                                                                                                Page 16 of 35
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Q. 3. For the specified CPU specified in APPENDIX I elaborate
(a) All the supported addressing modes with proper illustrative instruction
examples.                                                                                  [4]
---------------------------------------------------------------------------------------------------
Ans. 3 (a) The supported addressing modes of the given CPU are the following :

 1)    Register Direct : e.g. MOV $ri, $rj.
 2)    Immediate : e.g. MVI U $ri, < 16 Bit Value >
 3)    Register Indirect : e.g. LOAD $ri, ($rj)
 4)    Based Indexed : e.g. LOAD $ri, $rj[$rk]
 5)    Restricted Direct : e.g. IN $ri, <16 Bit Input Peripheral                           Address >
 6)    CS Relative : e.g. JZ < 16 Bit Offset>

  Marking Policy : Mentioning each Mode 0.25 Mark , Example 0.25 Mark
 Overall Progress : 1 Mark
----------------------------------------------------------------------------------------------------
Q. 3 (b) A possible format for the bit level encoding of its instruction set along
with proper justification in a stepwise fashion.                                          [ 10 ]
-----------------------------------------------------------------------------------------------------
Ans. 3 (b). Bit Level Encoding of an Instruction :

      A. Op Codes [ 4 Marks ]

      a) 3 Classes of Op Codes i.e. 2 bits to encode Op Code Class { 1 Mark }

          Class Bits             Op Code Class
          ------------------------------------------
            00                   Data Movement
            01                   Data Processing
            10                   Control
            11                   Unused ( Expansion Area )

      b) Maximum Number of Op Codes in each class = 21 [ a)..u) ] hence one needs 5 bits to
      encode ALL Op Codes in a particular class. { 0. 5 Mark }
      c) One Mode bit is needed to signify one of the two modes [User / Supervisor ] {0. 5 Mark }

      Hence Op Code Encoding Pattern : <Mode Bit> [ 0  User, 1  Supervisor ] { 2 Marks }
                                       < Class Bits > [ As shown above ]
                                      < 5 Op Code Bits> / Class
                                                                                                                 Contd. 17
            INDIAN INSTITUTE OF TECHNOLOGY, KHARAGPUR
                 End Autumn Semester Examination 2003
   Subject No. CS 43051             Subject Name : Comp. Org. & O.S.

                                 [ Question CUM Answer Booklet ]
                                                                                                Page 17 of 35
----------------------------------------------------------------------------------------------------------------------
Ans. 3(b) [ Contd.] Bit Level Encoding of an Instruction :

     B. Operand Addresses [ 6 Marks ]

     1) 2 Operand Machine.
     2) Sometimes single Operand. (No. of Operand bit = 0  Single, 1  Two)
     3) 32 GPRs i.e. 5 bits to encode any Register Address.
     4) Maximum 3 Registers needs to be specified i.e. 3 X 5 = 15 bits will be needed.
     5) Worst case 1 Register ( 5 bits) and 16 bits Peripheral Address needs be specified.
        Assuming 8 bit Op Code that leaves us with 3 bits to encode addressing modes at the
        worst.
     6) 6 Possible Addressing Modes with some pairing restriction:

     Aforesaid Points : { 2 Marks }

                           Addressing Mode Pairing ( For 2 Operands) { 2 Marks }

Source Addressing Mode                        Destination Addressing                    Addressing Mode Code
                                                       Mode
              Register                                   Register                                         000
              Register                                  Immediate                                         001
              Register                               16 bit Peripheral                                    010
              Register                               Register Indirect                                    011
              Register                                Based Indexed                                       100
          Register Indirect                              Register                                         101
           Based Indexed                                 Register                                         110
          16 bit Peripheral                              Register                                         111



Single Operand Addresses :  Related to Control Group. { 1 Mark }

Hence addressing mode & Operand Address encoding : { 1 Mark }

< No. of Operands Bit > | < Addressing Mode (3 bits) | <Operand Addresses> [ < Max. 21 Bits >

                                                                                                                Contd. 18
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                                                                                                Page 18 of 35
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Q. 3 (c) Any possible enhancement in the existing instruction set without altering
the suggested bit level encoding of the instruction set.              [ 4]

------------------------------------------------------------------------------------------------------------
Ans. 3 (c) Suggested Enhancements in the Instruction Set

  1) New Class of Instructions like Flag Status Setting / Reading can be included.

  2) 5 bits Op Code Encoding permits 32 number of different Op Codes in each of the
     four (4) possible classes a few of which are illustrated below :

        Instruction Group                                        Possible New Instruction(s)
          Control Group                                           Conditional RETURN(s).

           Data Processing Group                           MULTIPLY , DIVIDE
                                                        [ Provided Control Unit can be
                                                          upgraded ]
        Marking Policy: 4 Marks to be awarded depending on Progress Made.
        --------------------------------------------------------------------------------------------------
                                                                                             Contd. 19
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----------------------------------------------------------------------------------------------------------------------

Q. 4. (a) Spell out the key differences between the following modes of altering
the flow of an assembly language program :
i. A conditional branch instruction.
ii. A software interrupt instruction.
iii. A conditional CALL instruction.
iv. A Device Interrupt.
v. An Exception.                                                           [2 × 5 = 10]
---------------------------------------------------------------------------------------------------------
Ans. 4(a)
  i. Conditional Branch Instruction: ( Distinctive Features) :
    ( 1) Depends on the status of the relevant conditional flag(s).
    (2) Uni Directional / Open / One way transfer of control i.e. does not come back to
        original code area by itself.
    (3) Requires little OR no book keeping.
    (4) Does not force the processor to switch mode (user to supervisor).
    (5) Does not invoke any new process / thread.

ii. A software Interrupt Instruction ( Distinctive features) :
  (1) Does not depend on the status of any conditional flags.
  (2) Two way transfer of control i.e. control comes back to original place after Interrupt
      had been serviced.
  (3) Automatically Stacks Return Address & System Status Flags, other status if any are
      to be stacked by the System Programmer i.e. requires significant book keeping.
  (4) Switches mode from user to supervisor and back.
  (5) Normally causes change of process state and sometimes brings in new process to
      execution/running state.

iii. A Conditional Call Instruction ( Distinctive features) :
  (1) Depends on the status of relevant conditional flags.
  (2) Two way transfer of control i.e. control comes back to original place after Returning
      from Called Routine..
  (3) Automatically Stacks Return Address, other status if any are to be stacked by the
      Programmer i.e. requires significant book keeping.
  (4) Does not switches mode from user to supervisor .
  (5) Normally creates a new Thread.


                                                                                                                 Contd. 20
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                                                                                                 Page 20 of 35
----------------------------------------------------------------------------------------------------- -----------------
Ans. 4 (a) [Contd.]
iv. A Device Interrupt ( Distinctive features) :
 (1) Is not an Instruction but initiated by some peripheral device i.e. a totally
     Asynchronous activity.
 (2) Is taken up for servicing after completing the execution of the current instruction is
     completed.
 (3) Does not depend on the status of any conditional flags, however depends on the
     Interrupt mask bits.
 (4) Two way transfer of control i.e. control comes back to original place after Interrupt
     had been serviced.
 (5) Automatically Stacks Return Address & System Status Flags, other status if any are
     to be stacked by the System Programmer i.e. requires significant book keeping.
 (6) Switches mode from supervisor to user sometimes.
 (7) Normally causes change of process state and sometimes brings in new process to
     execution/running state.

V. An Exception ( Distinctive features) :
 (1) Is a totally asynchronous activity caused by some unwanted happening during a
     program execution.
 (2) The offending instruction cannot be completed and often is rolled back instead.
 (3) May depends on the status of relevant conditional flags.
 (4) One way transfer of control and normally cause program termination.
 (5) May Stack the offending instruction hoping to resume later.
 (6) Switches mode from user to supervisor .
 (7) Normally terminates the process/ thread.

-----------------------------------------------------------------------------------------------------
Marking Policy : 2 Marks for each case , minimum 0.5 Marks depending on Progress
made.

                                                                                                            Contd. 21
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                                                                                 Page 21 of 35
---------------------------------------------------------------------------------------------------------
Q. 4 (b) For the CPU specified in APPENDIX I elaborate the register transfer
level(RTL) operations in their proper sequence for carrying out each of the
following:
Q. 4 (b) i. Executing the instruction that loads a CPU register(GPR) with the
contents of a Memory location accessed via based - indexed.                           [3]
---------------------------------------------------------------------------------------------------------
Ans. 4(b) i. LOAD $ri , $rj[$rk] (say)

   Step 1. ALU Operand # 1  ($rj)

   Step 2. ALU Operand # 2 Input  ($rk) ; ADD ; Inhibit Flags.

   Step 3. MAR  (DS) |(ALU Result Register)

   Step 4. MMU  (MAR)

   Step 5. Address Bus  (MMU) ; Memory Read.

   Step 6. MDR  Data Bus.

   Step 7. $ri  (MDR)
-----------------------------------------------------------------------------------------
 Marking Policy : Max. 3 Marks depending on Progress.

Q. 4 (b) ii. Fetching an instruction from the main memory.                            [2]
---------------------------------------------------------------------------------------------------------
Ans. 4(b) ii.
   Step 1. MAR  (CS) | (Program Counter)

   Step 2. Address Bus  (MMU) ; Memory Read.

   Step 3. MDR  Data Bus.

   Step 4. Instruction Register  (MDR)
-----------------------------------------------------------------------------------------
 Marking Policy : Max. 2 Marks depending on Progress.

                                                                                              Contd. 22
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---------------------------------------------------------------------------------------------------------
Q. 4 (b) iii. Executing an unconditional CALL instruction.                            [3]
---------------------------------------------------------------------------------------------------------
Ans. 4(b) iii.

   Step 1. MAR  (SS) | (SP+1)

   Step 2. MMU  (MAR)

   Step 3. Address Bus  (MMU)

   Step 4. MDR  (PC) ; Memory Write. [ PC Saved in Stack ]

 Step 5. PC  Instruction Register (Operand)
Marking Policy : Max. 3 Marks depending on Progress.

                                                                                              Contd. 23
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                                                                                 Page 23 of 35
---------------------------------------------------------------------------------------------------------

Q. 5. (a) Assume that you are to build the electronic memory system for the CPU
specified in APPENDIX I according to the following specifications :

• Cache Line size = 4 bytes.
• Program Cache Capacity = Data Cache Capacity = 512 Kbytes.
• CPU is connected to main memory via cache, i.e. a Look Through configuration
is used.
• Cache to Main Memory connectivity is maintained through a 32 bit DATA BUS
and the 32 bit ADDRESS BUS.
• Main Memory Size = 512 MByte which is expandable up to 4 GByte.
• System ROM Size = 2 MByte which is composed of 512 KByte sized EPROM
chips each of which are speed compatible with the CPU & CACHE.
The EPROM chips are properly organized in a EPROM bank to present a 32 Bit
data bus connectivity. This ROM space, however get copied OR mapped in the
System RAM space after system is booted up.
• System RAM is composed of 128 MBit Dynamic RAM chips which are first
organized to form a Byte Organized RAM bank. Subsequently these banks are
properly organized to form a 32 bit wide RAM Module.
• Each RAM chip happens to be 4 times slower than the CPU CACHE combine.
Hence proper Memory Interleaving technique is employed for the RAM modules.

Q. 5 (a) i. How many RAM and ROM chips are needed ? Clearly depict all the
calculation steps.                                                                              [3]
--------------------------------------------------------------------------------------------------------
Ans. 5 (a)
  A. Calculation of RAM chips :

System RAM Capacity = 512 Mbyte.
RAM Chip Size = 128 Mbit , Hence 8 such chips are needed to form a RAM Module of
128 Mbyte . Four (4) such modules are needed to fill up the 512 Mbyte RAM. { 1 + 1 }

Hence number of RAM Chips = 8 X 4 = 32 . [ 2 Marks ]

A. Calculation of ROM chips :

System ROM Capacity = 2 Mbyte.= 2048 Kbyte
EPROM Chip Size = 512 Kbyte , Hence 4 such chips are needed to fill up the 2048
Kbyte of ROM. [ 1 Mark]                                           Contd. 24
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---------------------------------------------------------------------------------------------------------

Q. 5 (a) ii. Show by neat schematic diagrams in each case, the interface details
between the CPU CACHE combine and the following.

A. The EPROM bank. [ 2 ]
-----------------------------------------------------------------------------------------------------------
Ans. 5(a) ii. A. ROM Size = 2 M Byte = 2048 K Bytes = 512 K X 32 bit Words.

             EPROM Chip size = 512 Kbyte . Four (4) such chips are put in parallel to
offer a 512 K, 32 bit wide ROM.

Each EPROM chip of 512 Kbyte size requires 19 Address Bits to access on chip
locations.

 Since our system has got 32 bit Address Bus hence lower 19 bits will go to select one 32
bit Word out of 512 K number 32 bit Words while the higher 13 bits will be used for
chip select.                       32 bit Data Bus



      a18.. a0 ADDR BUS
      ( 19 bits)                                                 8 bit DATA                   8 bit DATA             8 bit DATA
                                     8 bit DATA


                           512 Kbyte                 512 Kbyte                 512 Kbyte                    512 Kbyte
                          EPROM #3                  EPROM # 2                 EPROM # 1                    EPROM # 0
                          (d 31 .. d 24)             (d23 .. d16)               (d15 .. d8)                  (d7 .. d0)



                                                                     READ Control
                        Chip Select
                         Decoder
      a31.. a19
      ADDR
      BUS
      ( 13 bits)

                                                                                                Contd. 25
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---------------------------------------------------------------------------------------------------------

Q. 5(a) ii.B. A single 8 Bit wide RAM Bank along with individual RAM chips. [ 2 ]
-----------------------------------------------------------------------------------------------------------
Ans. 5(a). RAM Chip Size = 128Mbit i.e. requires 27 bit ADDRESS / Chip
                                        8 bit Data Bus



             1 Bit             1 Bit        1 Bit         1 Bit          1 Bit          1 Bit     1 Bit        1 Bit

         RAM             RAM           RAM          RAM                RAM         RAM          RAM       RAM
         Chip            Chip          Chip         Chip               Chip        Chip         Chip      Chip
          d7              d6            d5           d4                 d3          d2           d1        d0



                                            27 bit Address BUS


                                          Read (         ) / Write (      )   Control
                                          Bus

------------------------------------------------------------------------------------------------------------

Q. 5(a)ii.C. A single 32 Bit wide properly interleaved RAM module with all the
additional hardware (if any).                                           [3]
                                                            32 bit DATA BUS


 RD/WR
 CNTRL

                     32 bit In/Out          32 bit In/Out                32 bit In/Out            32 bit In/Out
                      Data Latch             Data Latch                   Data Latch               Data Latch



                     32 bit DRAM            32 bit DRAM                  32 bit DRAM              32 bit DRAM

                     Module # 1             Module # 2                   Module # 3               Module # 4




                 32 bit Input               32 bit Input                 32 bit Input             32 bit Input
                Address Latch              Address Latch                Address Latch            Address Latch




                                                                  32 bit ADDRESS BUS                      Contd. 26
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---------------------------------------------------------------------------------------------------------

Q. 5 (b) For the aforesaid CPU & memory hierarchy consider the following :
• The cache access time is l0 nsec.
• Main Memory access time is 200 nsec.
• Secondary memory access time is 2 msec which hosts the Virtual Memory.
• Cache employs Write through technique.
• Virtual Memory employs Write Back technique.
• 75% of memory references are read rest 25% are write.
• The Cache hit percentage is 90% for read access and 80% for write access.
• The Main Memory hit percentage is 80% for read access and 60% for write
access.
• In case of a MISS while accessing main memory about 30%of the time one
need to replace a frame.
• About 20% of the time the frame chosen for replacement is found to have
been modified.
You are to compute the following. In each case you must show ALL calculation
steps along with explanation [60% credit reserved for CALCULATION &
EXPLANATION].

Q. 5(b) i. The average access time of the Physical Memory. [ 3 ]
-----------------------------------------------------------------------------------------------------
Ans. 5(b) i.
         Read Access time assuming 90% Cache Hit [ 1 Mark ]
         = 0.9 x Cache Access time (10 ns) + 0.1 x Main Memory
            access time (200 ns)
         = (0.9 x 10 + 0.1 x 200) nsec
         = (9 + 20) ns = 29 ns.

         Write access time    [ 1 Mark ]
         (Assuming write through technique) & 80% Cache Hit
         = 0.8 x 10 + 200
         = 208 ns

         Average access time (75% read + 25% write) [ 1 Mark ]
         = 0.75 x 29 + 0.25 x 208
         = 21.75 + 52 = 73.75 ns

                                                                                              Contd. 27
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                                                                                 Page 27 of 35
---------------------------------------------------------------------------------------------------------

Q. 5(b) ii. The average access time of the Virtual Memory.                          [5]
---------------------------------------------------------------------------------------------------------
Ans. 5(b) ii.
         Read Access time assuming 80% Main Memory Hit [ 1.5 Marks ]
         = 0.8 x Main Memory Access time (200 ns) + 0.2 x Secondary Memory
            access time (2 msec)
         = (0.8 x 200 + 0.2 x 2000) nsec
         = (160 + 400) ns = 560 ns.

         Write access time     [ 2.5 Mark ] { Assumptions = 1.5 Mark }
         (Assuming write back technique) 60% Main Memory Hit ,
          30% of Time Replacement out of which 20 % of time WRITE Back
         = 0.6 x 200 + 0.4 x 0.7 x 2000 [ Secondary Memory Access (non replacement)]
             + 0.4 x 0.3 x 0.2 x ( 200 [Main Memory Write] + 2000 [Secondary Write])
         = 120+560+0.024 x 2200 = 680 + 52.8
         = 702.8 ns

         Average access time (75% read + 25% write) [ 1 Mark ]
         = 0.75 x 560 + 0.25 x 702.8
         = 420+175.7 = 595.7 ns
-------------------------------------------------------------------------------------------------------
Marking Policy :
                     Explanation = 2 Marks
                     Calculation = 2 Marks
                     Result = 1 Mark
                                                                                            Contd. 28
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                                                                                                 Page 28 of 35
                                                        Group C
-----------------------------------------------------------------------------------------------------------
Q. 6. (a) Consider a paging system in which the main memory has a capacity of four (4) pages.
The execution of a program Pr requires reference to seven (7) distinct pages P0, P1, P2, P3 P4,
P5 & P6. The page address stream formed by executing the program Pr happens to be
P2,P0,P2,P3,P6,P5,P4,P1,P4 , P6,P1,P3 . Depict the manner in which the pages are brought
into main memory using FIFO page replacement policy. Clearly indicate also the page selected
for replacement.                                                                               [ 5 + 5 = 10 ]
----------------------------------------------------------------------------------------------------------------------------- ----
Ans. 6(a)

  Time (T)            1         2          3 4              5         6         7         8           9 10 11 12
    Page              P2        P0         P2 P3            P6        P5        P4        P1          P4 P 6 P1 P3
  Address
generated by
the Program
     Pr

Memory                (P2)      P2         P2 P2            P2        (P5)      P5        P5          P5 P5 P5 (P5)
Frame #1              Page                                            Page                                                 Page
                      Fault                                           Fault                                                Fault
  Memory                        (P0)       P0 P0            P0        P0        (P4)      P4          P4 P 4 P4 P4
 Frame #2                       Page                                            Page
                                Fault                                           Fault
  Memory                                          (P3)      P3        P3        P3        (P1)        P1 P 1 P1 P1
 Frame #3                                         Page                                    Page
                                                  Fault                                   Fault
  Memory                                                    (P6)      P6        P6        P6          P6 P 6 P6 P3
 Frame #4                                                   Page
                                                            Fault

FIFO Page                       P2         P2 P2            P2        P0        P3        None P5 P5 P5
Selected for
Replacement
 Replaced                                                             P2        P0        P3                               P6
   Page


  Marks distribution :

  [ 8 Marks (for Page Sequence) + 2 Marks (Replaced Page) = 10 Marks ]

                                                                                                                 Contd. 29
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                                             Group C
Q. 6 (b) Consider the following specifications about the physical and virtual
spaces as existing in a computer system.

• Physical space = 64 K words out of which 16K is occupied by the resident
operating system. Remaining portion is available to accommodate user
processes.
• Physical space is divided into 2K word size frames.
• Virtual space for user 1 = 256K words.
• Virtual space for user 2 = 512K words.
• Both the users share a common 8K word library, which is required at all time
by both the users.
Specify the address layout of the following, clearly highlighting each field:
           (i)      Virtual address of user 1.
ii. Virtual address of user 2.
iii. Address of library.
iv. Physical Address.                                                                   [4 × 2 = 8]
 --------------------------------------------------------------------------------------------------------
Ans. 6(b) Atop each figure the Numbers within parenthesis depicts Marks
              Allocation for that part of the figure :

          (ii)    Virtual Address of User 1 – 256 K space divided into 128 No. of 2k
                  word pages.




(ii)     Virtual Address of Use r2 – 512K word space divided into 256 No. of 2K
         word pages.




                                                                                           Contd. 30
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                                                                                 Page 30 of 35
------------------------------------------------------------------------------------------------------------
Ans. 6 (b) [Contd.]

(iii)    Address of Library – 8K word space divided into 4 Numbers of 2K word pages




(iv) Physical Address - 64 K word space divided into 32 Nos of 2K frames each




Marking Policy : 2 Marks for each Topic as indicated by the numbers within
parenthesis in figure .

Q7.
         Consider a hypothetical computer system having the following CPU scheduling
         features.

        It has got 3 (three) priority levels 1, 2 & 3 with 1 being the highest and 3 being
         the lowest. It supports a multilevel preemptive scheduling policy having the
         features mentioned below :

                 Priority level         Allotted Time Quantum              % CPU time allotted
                                               (in Units)
                         1                         10                                  50%
                         2                         15                                  30%
                         3                         20                                  20%

        Context switching time among jobs/processes having same priority = 2 units.
        Context switching time from one priority level to another = 5 units.
        Dispatcher execution time = 5 units (fixed).
        Time Quantum allotted/job excludes the time taken by the dispatcher as well as
         the context switching time.                                          Contd. 31
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-------------------------------------------------------------------------------------------------------
Q. 7 [Contd.]
 Jobs/Processes are serviced in a Round Robin fashion.
 Before servicing the very first job, one need to execute the dispatcher and
     perform a context switch i.e., no job can possess a zero waiting time.
 If any job finishes well within its allotted time quantum the remaining part of
     that time quantum is not allotted to any other job rather a context switch
     takes place.
For the previously mentioned computer system having the aforesaid scheduling
policy, the following job mix / processes is required to be serviced.

        Process/Job          Service time         Priority       Arrival time
                              (in units)                          (in units)
              P0                  20                 2               0
              P1                  15                 1                5
              P2                  25                 2                8
              P3                  30                 3               10
              P4                  12                 1               15
              P5                  40                 3               20
              P6                  18                 2               22
              P7                  24                 1               30


(a) Specify the queue status at each priority level.                        [3]
(b) Specify the Gantt chart for the given job mix.                        [ 10 ]
(c) From the Gantt chart compute the turnaround time as well as waiting time for
    each process.                                                          [ 5]


                                                                                         Contd. 32
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                                                                               Page 32 of 35
   -------------------------------------------------------------------------------------------------------
Ans. 7 (a)




                                                                                          Contd. 33
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                                                                               Page 33 of 35
   -------------------------------------------------------------------------------------------------------
Ans. 7 (b)




                                                                                             Contd. 34
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                                                                               Page 34 of 35
   -------------------------------------------------------------------------------------------------------

Ans. 7(b) [Contd.] Numbers within ( ) indicates Marks Allocation for that part.




                                                                                             Contd. 35
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                                                                               Page 35 of 35
   -------------------------------------------------------------------------------------------------------

Ans. 7 ( c)

    Process              Waiting time                                 Turnaround time

     P0                           92                                            239

     P1                       7–5=2                                          69 – 5 = 64

     P2                    116 – 8 = 108                                    293 – 8 = 285

     P3                    143 – 10 = 133                                   327 – 10 = 317

     P4                     26 – 15 = 11                                     80 – 15 = 65

     P5                     251 – 10 = 241                                  356 – 20 = 336

     P6                     210 –22 = 188                                   305 – 22 = 283

     P7                      45 – 30 = 15                                    193 –30 = 168


Waiting time = Time interval between a process’s arrival in Ready Queue to
                       the instant it first grabs         processor.

Turnaround time = Time interval between a process’s arrival in Ready Queue
                         to the instant it comes out after completion..

Marking Policy: 5 Marks to be awarded proportionately

                               ********** THE END ********

								
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