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					Semiconductor Technology Challenges
- A Foundry Perspective



 Frank Wen, Ph.D.           International Technology
                            Conference, HK, 2002
 Executive Board Director   Date : 01. 14, 2003
 and President              地點 :
Agenda:

   UMC Technology Roadmap.

   300mm Fab.

   Technology Challenges.

   Summary.
Brief Outline:
In this presentation we start with UMC’s technology roadmap as an example to
elaborate the nano-meter semiconductor technology progresses in reference to
the ITRS technology roadmap. Then we cover the recent progress in the 300mm
Fab and technology at UMC. Some analysis on 300mm wafer advantages and its
implications are also presented.

Technology challenges for both FEOL and BEOL processes are discussed. It
encompasses photolithography advancement, device structures and interconnect
technologies like copper/low-K dielectric material. In addition, some specialty
devices and materials utilized in the advanced device applications, e.g. strained
silicon and SOI technologies, are also illustrated.

Finally a brief summary of technology challenges and future trend for joint
technology development with IDM’s outsourcing strategy are also discussed.
UMC Technology Roadmap
UMC Leads SIA Roadmap


        2000      2001        2002   2003      2004       2005    2006   2007




                  Low-k (k=2.7)
         0.15um      0.13um                 90nm                 65nm
LOGIC    Al,Cu           Cu                  Cu                   Cu




 ITRS                     0.13um                   90nm                  65nm

Box center represents pilot production start schedule.
 Box center marks the start of pilot production.
    Fundamental Challenges - Rising Fab Cost

        US$ millions                                                $3,600M
  3,500
                                                             $3,000M
  3,000
  2,500
                                                   $1,750M
  2,000
                                            $1,250M
  1,500
  1,000                             $700M
                         $400M
     500     $200M $300M

        0
             1983     1987   1990   1994    1997      1999   2001      2003
 wafer   4"/5" 5"/6"   6"  6"/8"    8"     8"    12"    12"
 process 1.2um 1.0um 0.8um 0.5um 0.35um 0.25um 0.13um 0.09um
* Source : Dataquest, UMC
Fab 12A: UMC’s 300mm Fab in Production




 Located in Tainan’s Science-based Industrial Park
 Budget: $3.0B, first wafer-out in Q2, 2001
 Currently producing customer products in volume
Gross Die Increases more than Area Ratio

   Die size: 12x12 mm2            Die size: 20x20 mm2

                         200 mm
 GDPW                     wafer                  GDPW
   180                                           57




                         300 mm
                          wafer
GDPW                                              GDPW
  432                                             148
Gross Die Increases More Than Area Ratio


An example:
                                                                           Die size:22*22 mm
 die size   200 m m   300 m m
                                Ratio                2.8
 (m m 2)    G DPW     G DPW
   5x5       1108      2602     2.35
                                                     2.6
   7x7        553      1313     2.37




                                        GDPW Ratio
 12x12        180       432     2.40                 2.4
  14x14       124       308     2.48
                                                     2.2               Die size:12*12 mm
  20x20       57        148     2.59

  22x22       45        121     2.69                  2
                                                           0   100    200     300    400       500
                                                                     Die size (mm sq.)
300mm Fab Implications
   Larger-Sized Die Will Benefit.

   Competitive Or Even Better Yield / D.D.

   Shorter Cycle Time For Prototypes Due To

    Single Wafer Processing Capability.

   Eventual Cost Advantage.

   A Game For Major Leaguers: Only Leaders In

    IDM, Foundry, DRAM Can Afford Building Fabs.
Technology Advancement Challenges

                      Advanced
                     lithography
  300mm                 High K          R&D cost and
           90-nm   SOI, Strained Si,   human resources
           65-nm    novel devices,
           45-nm          IPs
  Copper    IPs
   low-k
    IPs
    ITRS Lithography Roadmap

                                               DRAM half pitch
            250
                                               ASIC/MPU half pitch
                                               ASIC physical gate length
            200                                MPU physical gate length
CD (nm) .




                    248
            150
            100                   193

                                               157             EPL & EUV
            50
             0
             1999   2001   2003         2005   2007          2009
                                    Year
Lithography Challenges
   Mask
       Mask performance control and pellicle issue to 157nm
       Defect control
   Resist material
       Resist maturity and resist processing applications
   Exposure tool
       Lens performance, tool maturity and timing
       Alignment accuracy and overlay control
   Metrology
       Measurement accuracy and precision control
   Data engineering and data preparation
       OPC implementation and RET techniques
UMC 35nm Gate Patterning
                   35nm gate is patterned by
                    aggressive 193nm resist trim.



   Dense Line           TEOS




                               35nm

    Iso Line           NMOS Poly in Iso line
CMOS Device Structure Challenges
     90nm            65nm               45nm
 Bulk Transistor   Bulk Transistor   Bulk Transistor




     PD SOI            PD SOI            FD SOI




                       FD SOI          Strained Si




                                      Double Gate
UMC SOI Device Structure



          79 nm


          SOI



         BOX
UMC Strained-Silicon Device Structure




                      Poly Gate




       Strained-Si                         Co Silicide
        Channel
                                                         Material from
                     Relaxed Si 1-x Ge x                 AmberWave
                                                          Systems
                                UMC Strained Silicon NMOS Gm / Idsat Gain
                               300                                                                    1000                                                    100%
                                         NMOS                      Vd= 50mV                                      NMOS                        Vg=1.2 V         90%
                                                                                                             Strained-Si
Transconductance, Gm (uS/um)




                                         Strained-Si                                                   800                                                    80%

                                                                 41%                                                                                          70%




                                                                                                                                                                     Id enhancement
                                                                                      Idsat (uA/um)
                               200
                                                                                                       600       Bulk                                         60%

                                                                                                                                                              50%

                                                                                                       400                                                    40%
                               100
                                                                 Bulk                                                                                         30%

                                                                                                       200                                                    20%
                                                                                                                  Idlin > 35%              Idsat:23%          10%

                                0                                                                       0                                                     0%
                                     0      0.2   0.4    0.6      0.8   1       1.2                          0
                                                                                                             0    0.2 0.280.4     0.6
                                                                                                                                0.5675    0.8
                                                                                                                                            0.8551.0 1.1425
                                                                                                                                                        1.2
                                                        Vg (V)
                                                                                                                                 Vd (V)
                                                                            (W=0.3um, Poly CD ~70 nm)


                                     • Short Channel NMOS Gm_max increases 41% @ Vd=50 mV.
                                     • Idlin gain ( >30%) is greater than Idsat gain (23%) leading to better
                                     driving capability in circuit operation.
                                                                                                                        Substrate Material from AmberWave Systems
UMC Interconnect Technology Roadmap


Tecnology Node     0.13um    90nm           65nm
    k value          2.7       2.7            2.2

 Dielectric Tool    CVD       CVD      Porous CVD / SOD

    Al / Cu          Cu        Cu             Cu

   Cu Liner        PVD/CVD   PVD/CVD       CVD/ALD

   Cu Seed          PVD      PVD/CVD   PVD/ PVD + repair

     Cu Fill       Plating   Plating        Plating
UMC 0.13um Cu/Low-K Interconnect Technology
UMC Aggressive R&D Spending
   1997-2001 total R&D spending = $ 743 million
   Average R&D / Sales % = 8.6%

R&D $million                                     R&D / Sales %
     300                                                15%
                  R&D Spending                  13.3%
     250          R&D / Sales %
                                                        12%
                     10.4%                      245
     200                          8.9%
                                         170            9%
                                  153
     150   6.3%
                      111                               6%
     100                                 5.7%
             64
                                                        3%
      50

       0                                                0%
           1997      1998         1999   2000   2001
UMC Process Patent Leadership
Number of US Patents
  Granted per year
                                                           633
     700
                                                    560
     600
     500
     400                                     334
     300                              197
             153       172     155
     200
     100
       0
           1995    1996      1997    1998   1999   2000   2001


                UMC Ranks in the Top 10 for U.S.
             Semiconductor Process Technology Patents
Summary I : Technology Challenges

   300 mm Wafer: Fab Cost / Technology Challenge.

   Lithography Challenge: 90nm to 65nm to 45 nm.

   Interconnect Challenge: Low K Dielectric Material.

   Ultra Thin Gate: High K Gate Material.

   Device Structure: SOI, Strain Silicon Device,

                      Multi-Gate Device.
 Summary II : Global Trends
 1                  Fewer semiconductor companies
                    can afford building 300mm fabs and
                    developing nano-meter technologies
                    alone.

 2      Past                      Now                           Future

                                   +                    50%
                                                                 +     50%
        100%              80%           20%
       captive          captive     outsourcing       captive      outsourcing

Outsourcing is the general trend and is doing more for advanced technologies.

 3                  Business models may be modified to have
                    more inter-company JDP and JV partnership.

				
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