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CMOS_Fabricationv2

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CMOS_Fabricationv2 Powered By Docstoc
					By: Joaquin Gabriels
November 24th, 2008
   Overview of CMOS
   CMOS Fabrication Process Overview
   CMOS Fabrication Process
   Problems with Current CMOS Fabrication
   Future Changes in CMOS Fabrication
                        http://en.wikipedia.org/wiki/CMOS
   Complementary metal–oxide–semiconductor (CMOS)
   Has many different uses:
       Integrated Circuits
       Data converters
       Integrated transceivers
       Image sensors
       Logic circuits
NAND Circuit
http://lsmwww.epfl.ch/Education/former/2002-
2003/VLSIDesign/ch02/ch02.html
1.   Create a pattern.
2.   Oxidize small layer,
     about 1µm thick.
3.   Place photoresist on
     top of SiO2
4.   Place mask(pattern)
     above photoresist and
     expose it to UV light.
1.   Etch away SiO2
     using HF acid or
     plasma.
2.   Remove remaining
     photoresist with
     acids.
   To create a n well:
       Diffusion
         Heat wafer in Arsenic gas chamber until diffusion occurs.
       Ion Implantation
         Arsenic or phosphorous are implanted in window.


                                                                      SiO2


                                               n well
   A thin layer of oxide
    is deposited.
   A thin layer of
    polysilicon is
    deposited using
    Chemical Vapor
    Deposition (CVD) .



                      n well
        p substrate
http://en.wikipedia.org/wiki/Chemical_vapor_deposition
         Remove oxide layer
          using acid.
         Dope open area
          using Ion
          implantation or
          diffusion.

p+       n+       n+        p+            p+   n+
                                 n well
              p substrate
                                                Metal
                                                Thick field oxide
p+   n+       n+        p+            p+   n+

                             n well
          p substrate
   Optical lithography is limited by the light
    frequency.
   Material limitations
   Yield limitations
   Space limitations
   Material changes like using high-k materials.
   Design changes
       SOI(Silicon On Insulator)
       Double Gate (Finfet)
       Twin-Tub Process
http://www.fujitsu.com/downloads/MAG/vol39-1/paper02.pdf
   CMOS Digital Integrated Circuit Design - Analysis and Design by S.M.
    Kang and Y. Leblebici
   http://www.fujitsu.com/downloads/MAG/vol39-1/paper02.pdf
   “Introduction to VLSI Circuits and Systems,” John Wiley and Sons, 2002
   http://lsmwww.epfl.ch/Education/former/2002-
    2003/VLSIDesign/ch02/ch02.html
   http://en.wikipedia.org/wiki/Chemical_vapor_deposition
   users.ece.utexas.edu/~adnan/vlsi-05/lec0Fab.ppt
   http://en.wikipedia.org/wiki/CMOS
   www.usna.edu/EE/ee452/LectureNotes/02-
    _CMOS_Process_Steps/08_Simple_CMOS_Fab.ppt
   http://en.wikipedia.org/wiki/Silicon_on_insulator
   access.ee.ntu.edu.tw/course/VLSI_design_90second/data/Chapter%203%20Part
    2%2003-20-2002.doc

				
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