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					RES. , CAP. and BJT Layout Guide                      LG Semicon Co., Ltd.



       Resistor,Capacitor and BJT
               Layout Guide
                    for
           DRACULA Verification

      -. It is a layout guidance of resistor and capacitor.
         You can verify your design using DRACULA.
         LGS does`t provide the DRACULA rule file to customer in principle.
         If you need this files, contact to LGS marketing engineer.

      -. It applies to 0.8um, 0.6um, 0.5um and 0.35um design.
         The technology of 0.6um and 0.5um have a double poly process.




mailto:sonhh@lgsemicon.co.kr        1        ASIC LIBRARY TEAM/ 08-OCT-1998
RES. , CAP. and BJT Layout Guide                  LG Semicon Co., Ltd.




               - Table of Content -

                    1)     Analog Process Overview

                    2)     Layout Guide

                    3)     Double Poly Design Rules

                    4)     LVS   Check



mailto:sonhh@lgsemicon.co.kr        2     ASIC LIBRARY TEAM/ 08-OCT-1998
RES. , CAP. and BJT Layout Guide                   LG Semicon Co., Ltd.


        1. Analog Process Overview
             1) Kinds of R & C

                 - Resistor
                       Well Resistor
                       Diff. Resistor
                       Poly Resistor

                 - Capacitance
                       MOS Cap (using Gate Poly Layer)
                       Poly Cap (using Poly2 Layer)
                       Metal Cap




mailto:sonhh@lgsemicon.co.kr        3      ASIC LIBRARY TEAM/ 08-OCT-1998
 RES. , CAP. and BJT Layout Guide                            LG Semicon Co., Ltd.


2) Device Characteristics

  Items          Unit       Technology       Type                 Value            Remark
                                            WELL                   637.6
                                         DIFFUSION              0.63 / 0.41           N/P
                                0.8um    GATE POLY              4.22 / 5.76           N/P
                                          CAP POLY                   90
                                            WELL                   561.4
                                         DIFFUSION             65.3 / 98.2            N/P
              Sheet             0.6um    GATE POLY              5.55 / 5.79           N/P
               Resistance                 CAP POLY                   90
Resistor                                    WELL            314.5 / 338.9            5V / 3V
                                         DIFFUSION       84.4 / 134.3 80.7 / 132.4 N / P(5,3V)
               Ω




                 /SQ
                                0.5um    GATE POLY        11.2 / 10.9 12.5 / 12.6 N / P(5,3V)
                                          CAP POLY                   90
                                            WELL                   409.16
                                         DIFFUSION              3.36 / 3.32           N/P
                            0.35um       GATE POLY              3.79 / 4.05           N/P
                                          CAP POLY                   90



 mailto:sonhh@lgsemicon.co.kr            4          ASIC LIBRARY TEAM/ 08-OCT-1998
  RES. , CAP. and BJT Layout Guide                       LG Semicon Co., Ltd.




   Items            Unit         Technology    Type          Value               Remark
                                               MOS          1.96 / 1.97            N/P
                                               POLY
                                   0.8um                        1.55
                                               METAL        3.45E-2
                                                                                  N/P(3.3V)
                                               MOS     2.41 / 2.45 2.41/ 2.45     N/P( 5V)

                Unit               0.6um       POLY             1.55
                 Capacitance                   METAL     4.17E-2/4.17E-2         3.3V / 5V
Capacitance                                                                       N/P(3.3V)
                                               MOS     3.54 / 3.55 2.73 / 2.76    N/P( 5V)
                        ㎛




                  fF/   2
                                               POLY
                                   0.5um                        1.0
                                               METAL      2.89E-2/3.21E-2        3.3V / 5V
                                               MOS           4.79 / 4.53           N/P

                                  0.35um       POLY             1.55
                                               METAL        5.17E-2


  mailto:sonhh@lgsemicon.co.kr             5     ASIC LIBRARY TEAM/ 08-OCT-1998
 RES. , CAP. and BJT Layout Guide                                   LG Semicon Co., Ltd.


3) 0.6um Analog Process Summary
 -. Vertical Structure
                                    Gate Poly
                                    ONO
        Gate Poly                   C-Poly                         C-Poly
        Gate Oxide


                Active Transistor                    Capacitor               Resistor

                                                                                    Oxide

    Gate Poly             =           W                  ONO           =            Nitride
                                                                                    Oxide
                                      Poly

 -. Process Parameter

    •   Gate Poly Thickness                  :   Dopped Poly : 1500 [A] + W : 1500 [A]
    •   Gate Poly Rs                         :   6 - 8 [ohm/sq]
    •   Gate Oxide Electrical Thickness      :   145 [A], As Grown Thickness = 125 [A]
    •   C-Poly Thickness                     :   Implanted Poly : 1500 [A]
    •   C-Poly Rs                            :   90±15 [ohm/sq]
    •   ONO Dielectric Effective Thickness   :   220 [A]
    •   Cap.unit                             :   1.55±0.15 [fF/um2]

 mailto:sonhh@lgsemicon.co.kr                    6          ASIC LIBRARY TEAM/ 08-OCT-1998
 RES. , CAP. and BJT Layout Guide                                        LG Semicon Co., Ltd.


   2. Layout Guide
     1) Resistor
              WELL TYPE                                          DIFFUSION TYPE


                                 N-DIFF



            CONT       NWELL      CONT     METAL                  CONT    DIFFUSION    CONT   METAL




                       Dummy R Layer                                        Dummy R Layer

   Dummy Resistor Layer : #31 (CRE)                          Dummy Resistor Layer : #31

 Element Type : RES [NW]                                 Element Type : RES [ND] , RES [PD]

 In CDL :     R1 n1 n2 2.8k $[NW]                        In CDL : R1 n1 n2 2.8k $[ND]

*. In 0.35um, you should use SDI layer as same as dummy layer (CRE).

 mailto:sonhh@lgsemicon.co.kr                      7          ASIC LIBRARY TEAM/ 08-OCT-1998
RES. , CAP. and BJT Layout Guide                                      LG Semicon Co., Ltd.




                        POLY ( INCLUDING POLY2 ) TYPE




                         CONT            POLY1   OR   POLY2         CONT   METAL




                                   Dummy R Layer

                                Dummy Resistor Layer : #31
      Element Type : RES [PY] , RES [P2]

      In CDL : R1 n1 n2 2.2k $[PY]

   *. In 0.35um, you should use SDI layer as same as dummy layer (CRE).

mailto:sonhh@lgsemicon.co.kr                     8            ASIC LIBRARY TEAM/ 08-OCT-1998
RES. , CAP. and BJT Layout Guide                        LG Semicon Co., Ltd.



     2) Capacitance

                         MOS CAP (USING GATE POLY )

             DIFFUSION




                    CONT              METAL




                                         POLY




                    CONT




mailto:sonhh@lgsemicon.co.kr         9          ASIC LIBRARY TEAM/ 08-OCT-1998
  RES. , CAP. and BJT Layout Guide                                         LG Semicon Co., Ltd.


              POLY2 CAP                                              METAL CAP


                 CONT                  METAL                                                PORT LAYER




                 CONT                  METAL                                                PORT LAYER

           POLY1(TOP PLATE)                                      METAL1(TOP PLATE)

             POLY2 (BOTTOM PLATE)                                 METAL2 (BOTTOM PLATE)
                                                                                                 Dummy Cap
                                                                                                    Layer
Dummy Cap. Layer(#36) is not needed any more.             Dummy Cap Layer : #37 (MCAP)
                                                          METAL1, METAL2   :   DIFFERENT TYPE METAL

  Element Type : CAP [PY]                              Element Type : CAP [M2] or [M1],[M3],[M4]

  In CDL : C1 topnode botnode $[PY]                    In CDL : C1 m2node m1node $[M2]

*. CAP[PY] , [M1], [M2], [M3], [M4] is supported. And sandwitch capacitors are allowed.
*. Model type is referenced upper layer. You should not swap terminal order in CDL.

  mailto:sonhh@lgsemicon.co.kr                    10          ASIC LIBRARY TEAM/ 08-OCT-1998
RES. , CAP. and BJT Layout Guide                                LG Semicon Co., Ltd.



     3) BJT(Only vertical PNP BJT)

           PNP BJT
                                                          <In 0.35um>
                                                          Emitter Area : 1.1um x 1.1um
                                   P+   CONT
                                                          Base Area    : 5.9um x 5.9um
                                                          Emitter Space to Base   : 0.8um
                                   N+                     Base Space to Collector : 1.2um
                                                          Base N+ diffusion Width : 1.1um
                                                          Collect N+ diff. Width : 1.1um
                                                          NW overlap of Base N+ diff. : 0.6um
                               E                   C
                                                          <In 0.5um>
                                                          Emitter Area : 10um x 10um
                                   P+    B                Base Area    : 16.52um x 16.52um

                                   N+   NWELL
                                                          <In 0.6um>
                                   P+                     Emitter Area : 10um x 10um
                                               P-SUB      Base Area    : 5.9um x 5.9um

Element Type : BJT [SP]

In CDL : Q1 collector base emitter $[SP]

mailto:sonhh@lgsemicon.co.kr            11             ASIC LIBRARY TEAM/ 08-OCT-1998
RES. , CAP. and BJT Layout Guide                                      LG Semicon Co., Ltd.

  3. Double Poly Design Rule




                                                                                                ㎛
                                                                                    Dimension( )
                   Description                                0.6um        0.5um       0.35um
  1.  Capacitor Poly Space                                      2.0          2.0          2.0
  2.  Gate Poly Space                                           2.0          2.0          1.0
  3.  Capacitor Poly OL Gate Poly                               1.0          1.0          0.5
  4.  Capacitor Poly to Diff. Sapce                             2.0          2.0          1.0
  5.  Capacitor Poly contact to Gate Poly Space
      -. in case of Contact surrounded by Gate poly             1.2          1.2          1.0
      -. the other case                                         0.5          0.5          0.5
  6. Gate Poly on Capacitor Poly to TC Space                    1.0          1.0          1.0
       (TC on Gate Poly is not allowed)
  7. Capacitor Poly OL Capacitor Poly contact                   0.5          0.5          0.5
  8. Metal1 OL Capacitor contact on either                      0.3          0.3          0.2
       Capacitor Poly or Gate Poly
  9. Metal1 width on Capacitor Poly                             1.0          1.0          -
  10. Metal1 Space on Capacitor Poly                            1.0          1.0         1.0
  11. Metal2 Width on Capacitor Poly                            1.2          1.2          -
  12. Metal2 Space on Capacitor Poly                            1.2          1.2         1.2
  13. Capacitor Poly defined by Gate Poly                      10x10        10x10       10x10
  14. Capacitor Poly space to
     -. other unrelated layers                                  2.0          2.0          2.0
     -. other unrelated implant layers                          1.6          1.6          2.0
  15. Gate Poly to Metal1 Space                                 1.0          1.0          1.0
  16. Capacitor Poly width for resistor                                                   1.0
   *. Forbidden Rules
     -. Capacitor poly over diffusion region
     -. Gate poly across capacitor poly edge
     -. M3 over capacitor poly                                                           N/A


mailto:sonhh@lgsemicon.co.kr                          12   ASIC LIBRARY TEAM/ 08-OCT-1998
 RES. , CAP. and BJT Layout Guide                                        LG Semicon Co., Ltd.
Double Poly Design Rule
                                                          d7                     Layer Information
                   d1
                                                                                   Diffusion
                         d 11          d 13
                                                                                   Bottom Plate
                                                        d 15
                                                                                    (Poly2)
                         d 12

                                                                                   Top Plate
                                                                                   (Gate Poly)

                                                                                   Contact
                                                               d6
       d 14         d8                                                             Metal 1

                                                                    d4
                                                                                   Via_Contact
              d3                 d2
                                                                                   Metal 2
                                                               d5

                           d9   d 10
                                                                                   Other Layers
                                              d5


 mailto:sonhh@lgsemicon.co.kr                      13           ASIC LIBRARY TEAM/ 08-OCT-1998
RES. , CAP. and BJT Layout Guide                      LG Semicon Co., Ltd.


     4. LVS Check
     -To check LVS violation of design including Resistor or Capacitor,
        we use Dummy Layers ( CRE and MCAP).
        Layer #31, CRE is used for defining Resistor and Layer #37, (MCAP)
        for (metal) Capacitor.
        Layer #36 (CAP) which define cpoly-poly capacitor is not needed
        any more.

         As overlapping those dummy layers on layout and defining Resistor
         and Capacitance in rule file, we can verify the design including
         Resistor and Capacitance.

         But, we can check MOS type Capacitor, cpoly-poly Capacitor and
         BJT without adding dummy layer.

     - In 0.35um, you should use SDI layer over resistor region.


      * Contact LGS ASIC Design Dept. for more information.

mailto:sonhh@lgsemicon.co.kr         14       ASIC LIBRARY TEAM/ 08-OCT-1998

				
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