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					EE249 Project:
Partitioning Algorithms &
Modeling Methodologies
for HW/SW Partitioning
in Metropolis

   Mentor:
   John Moondanos,
   GSRC Visiting Fellow, UC Berkeley
   &
   Strategic CAD Labs Intel Corp.

                                       DUSD(Labs)
Problem Statement
 HW/SW partitioning deals with assigning parts of a system
  description to heterogeneous implementation units
      Key task in system level design due to the downstream cost & performance
       consequences of the initial partitioning choices

 Multi-faceted
      Processor & flash on the same die or not?
      Functionality Partitioning into chips
      Hardware vs. Software functionality Implementation
      Which functions to which type of silicon?

 Difficult to model & analyze with conventional RTL Tools

 Of course, the focus is on how it affects power consumption


                                                                                  2
Goal of the Project

Briefly Review the literature to capture the state of the art

Develop technologies and methodologies for solving the
  partitioning problem within the Metropolis environment
      Methodologies will focus more on the system modeling
       methodology that is better suited for the capabilities of Metropolis
      Technologies will focus more on the algorithms that must be used
       to accomplish the partitioning using the capabilities of the
       Metropolis environment.




                                                                          3
Suggestion for Design Driver for this Project

For the hardware: The PXA800F cell phone processor from
  Intel
     Some publicly available introductory material on the PXA800F is
      available in the “backup material section”
     Modeling of the Xscale can happen with the GnuPro simulator

For the Software: We have available Statistical Models for
  typical applications that run on the PXA800F




                                                                        4
Backup Material

Overview of the PXA800F cellular phone Processor

References




                                                    5
The Intel® PXA800F Cellular Processor

Full GSM/GPRS Class solution

 High-performance/Low-power Intel® XScale ™
 technology core, providing class-leading
 headroom for rich data applications
 Intel® Micro Signal Architecture

 Intel® On-Chip Flash Memory
     GSM/GPRS Communications Stack, RTOS and
      applications code for a single-chip mobile solution


                                                            6
The Intel® XScale ™ in the PXA800F
 High-performance, power-efficient processor supports data-intensive applications

    Processor core operates at an adjustable clock frequency from 104 to 312 MHz
   Instruction cache and Data cache memories
 4 MB integrated Intel On-Chip Flash memory

   512 KB integrated SRAM
   Memory controller supports synchronous Flash mode, page mode Flash, SRAM,
    DRAM, and variable latency
 DMA controller

 Clock units-GSM slow clocking, GSM frame timing, watchdog, RTC

   Supports a wide range of standard interfaces-SIM, UART, USB, I2C*, SPI, SSP,
    Digital Audio Interface, MultiMediaCard, Secure Digital Card, Sony Memory Stick,
    Dallas* 1-Wire* Interface, keypad, PWM D/A, JTAG
    Interfaces for Bluetooth, IrDA, GPS and digital camera peripherals
   LCD Controller for up to 120 x 240 display 16-bit color or gray scale


                                                                                       7
Intel Micro Signal Architecture in the PXA800F
 Performs GSM/GPRS baseband signal processing

    Modified Harvard architecture, dual-MAC, deep pipeline, 104 MHz
    execution clock
   Instruction cache and 64 KB dual-banked data SRAM
 512 KB integrated Intel On-Chip Flash for field-upgradable signal
    processing firmware
 Includes microprocessor instructions such as bit manipulation

 Includes cipher and Viterbi accelerators

    Multiple sleep modes and integrated power management minimize power
    consumption
   Interface support-digital I/Q, voice codec, auxiliary serial port for mixed-
    signal analog baseband, I2S audio codec interface, RF synthesizer serial
    control interface, JTAG

                                                                                   8
The Memory Subsystem

The Intel® XScale ™
     Instruction and Data Cache
     4MB of Flash & 512KB of SRAM always at 104MHz
     Memory Controller managing accesses to external SRAM

The MSA
     Integrated 64KB SRAM for microcontroller like instructions
      •   Special instructions for maximizing GSM/GPRS performance
     512KB of flash for program store




                                                                     9
 PXA800F Block Diagram         Smart Battery I/F
             UARTs for
             Bluetooth, IRDA


Synch Serial Port




          GSM Sim card I/F

External Power
Management I/F
                                                   10
 PXA800F Block Diagram            Pulse Width
            Memory Stick          Modulator for
                                  buzzer


Secure Card I/F




                   Programmable
                   Clock
                                                  Encrypt/Decrypt
  Timing Control Unit
                                                  GSM data offloading
  For basestation
                                                  MSA              11
  timing
  PXA800F Block Diagram
  DSP Synchronous
  Serial Ports
  interfacing with RF,
  speech




   High Speed Logger
   For debug
                          Viterbi error
Full Bandwidth (Hi-
                          decoding offloading
Fi) digital audio I/F
                          MSA              12
PXA800F Block Diagram




  Peripheral
    Bus 1
           Peripheral
             Bus 2
                        13
References

On the hardware-software partitioning problem: System
 modeling and partitioning techniques Marisa López-Vallejo,
 Juan Carlos López July 2003 ACM Transactions on Design
 Automation of Electronic Systems (TODAES), Volume 8
 Issue 3
A hardware/software partitioner using a dynamically
 determined granularity Jörg Henkel, Rolf Ernst June
 1997 Proceedings of the 34th annual conference on
 Design automation conference

                                                              14
References

Issues in partitioning & design space eploration for
  codesign: Dynamic hardware/software partitioning: a first
  approach Greg Stitt, Roman Lysecky, Frank Vahid June
  2003 Proceedings of the 40th conference on Design
  automation
Hardware/software partitioning of software binaries Greg
  Stitt, Frank Vahid November 2002 Proceedings of the 2002
  IEEE/ACM international conference on Computer-aided
  design

                                                              15

				
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