# final316-28-29-IIB

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```					                           Computer Engineering Department
College of Computer and Information Sciences
King Saud University

CEN316
Computer Architecture and Assembly Language
‫عمارة الحاسبات ولغات التجميع‬
Final Exam
Saturday 10/1/1429h
3 hours

Problem    P1      P2      P3       P4        P5      P6       P7      P8   Total

Max       10      10       10       10       10       10       10     10    80

:‫االسم‬

: ‫الرقم‬

Notes:
 Please be self-dependent, other means will not be tolerated.
 This is a closed book exam

‫"رة اشرح لي صدري و يسر لي أمري واحلل عقدة مه لسبوي يفقهىا‬
‫قىلي. بسم هللا الفتبح اللهم ال سهل إال مب جعلته سهال وأوت تجعل‬
"‫الحزن إذا شئت سهال يب أرحم الراحميه‬

1/11
Problem 1
Solve the following questions:

A)     If numbers in a floating-point processing unit are represented as follows:
8-bit normalized sign-magnitude mantissa
8-bit biased exponent

Find R1 = R2 + R3             where R2 = 0100100110101100 and
R3 = 0100100111101110

B)      After each of the following MIPS instructions, show the contents of the
destination register in decimal.
Ori     \$s1, \$zero, 20
Sll     \$s2, \$s1, 5
Slti    \$s3, \$s2,200
Subi    \$s4, \$s3, \$s2
Lui     \$s5, -7

2/11
Problem 2
Answer the following, using examples where possible,

A) Where does the Speedup of a pipeline come from? Is there any relation
between the speed up and the pipeline depth (number of stages)? Why not use
very deep pipeline? Please be specific and clear.

B) Compare Write through versus write back in cached memory system, mention
the ways to overcome write through processor stalls.

C) How do we form the jump address? Can we jump to any where in the memory
space? Explain clearly using examples.

D) One of the ways of reducing control hazards in pipelining processors is using
delayed branch; explain delayed branch, is there any relation between the
delayed branch solution and the cycle at which branch condition is known?

3/11
Problem 3

slti instruction is to be added to the single cycle Datapath, it translates:
slti \$s1,\$s2,x               # if (\$s2<x) then \$s1=1;
# else \$s1=0
# where x is an immediate value
1. Add any necessary modifications to the single cycle Datapath,
2. Fill in the control table with the missing values for the current and new
instructions.

Instruction Reg ALU Memto Reg Mem Mem Branch                                                                                                                     ALU                ALU
Dst Src Reg Write Read Write                                                                                                                         Op1                Op2
R-format                   1   0    0    0                                                                                                                        1                  0
LW                         1   1    0    0                                                                                                                        0                  0
SW                         0   0    1    0                                                                                                                        0                  0
BEQ                        0   0    0    1                                                                                                                        0                  1
slti

0
M
u
x
AL U
Ad d res u lt                 1

A dd                                                                                                                   S h if t                                         PC S rc
R eg D st                                   l e ft 2
4                                                                                         B ra nc h
In s tr u c ti o n [ 3 1 2 6 ]                    M e mt o Re g
Co n t ro l
A LU O p
M e mW r it e
A LU S rc
R e g W rite

I n s t ru c t i o n [ 2 5 2 1 ]                    Read
R ead                                                                                       r e g i st e r 1
a d dr es s
I n s t ru c t i o n [ 2 0 1 6 ]                                              d ata 1
r e g i st e r 2                                                  Z er o
I ns t ru c tio n                                      0                             Re g is te rs R e ad                         AL U
[31– 0]                                                                                                                              AL U
M                W rit e                   d ata 2           0                                 Ad d re ss              R e ad
r es ul t                                     1
I n st ru c ti on                                                           u               r e g i st e r                              M                                                         d a ta
u                                                                 M
m e mo ry                                                                x                                                                                                                               u
In s tr u c ti o n [ 1 5 1 1 ]                      W rit e                                      x
1                                                                                                               D a ta           x
d a ta                                      1                                                 me m or y        0
W ri te
da t a
16                32
In s tr u c ti o n [ 1 5 0 ]                                                  S ig n
e x te n d            A LU
co n tr ol

I ns t ru ct io n [ 5 0]

4/11
Problem 4

A) A computer has 16 general-purpose registers, which can be selected and used by
the user. It is desired to design an instruction format for this computer according
to the following specifications:

    Instruction size is 12-bit, fixed for all instructions
    Memory reference instructions: 8 instructions(no registers, only direct addressing)
    Register reference instructions that use two registers: 7 instructions
    Register reference instructions that use one register: 16 instructions

      2_registers Instruction

      1_Register Instruction

      Memory Instruction

What is the maximum memory size? Can you suggest a way to increase it?

B) A company is to improve its computer. The applications that users typically run
on this computer have the following instruction distribution and average CPI’s:

Instruction        Percentage     Average CPI
Integer ALU           20%             1.0
FP Multiply           20%             4.0
Branch                20%             1.5

instruction that multiplies two operands together and adds the result to a third
operand. They have determined that this feature can be used to combine half of the
FP add instructions and the corresponding FP multiply in the original code.
Assuming the clock cycle time of the machine is not affected and the CPI of the
1. the ratios of the instruction counts,
2. the overall machine CPIs, and
3. the execution time of the original versus the new machine.

5/11
Problem 5
A new instruction called dec_s is to be added to the multicycle
implementation, the instruction behaves like regular store (sw) except that it
decrement the address register before accessing memory.

1. suggest the instruction format
Instruction: dec_s        ………………

Format:

2. Complete the RTL description of this instruction (instruction Steps) based on

Step name               Action
IR=Memory[PC];
Instruction Fetch    PC = PC + 4;
Instruction Decode    A=Reg[IR[25-21]];B=Reg[IR[20-16]];
and register fetch   ALUOut = PC + (sign-extend(IR[15-0]) << 2);

3. Add any necessary changes to the circuit diagram
4. Modify the state diagram to incorporate the new instruction, original
instructions should not be changed

6/11
P C W rite C ond                 P C S our ce
P C W rit e
A LU O p
IorD         Outputs
AL U S rc B
A LU S rcA
M emW r ite          Control
R e gW rite
M e mtoR eg

IR W rite
Op         R e gD st
[5– 0]
write                                                                                      0
control
M
Jum p                1 u
26               28
I ns tr uc tio n [ 2 5 – 0 ]                                                                                                                        ad dre ss [3 1-0 ]     x
S h ift
2
left 2
I n s tr uc tio n
[3 1 - 2 6 ]
PC              0                                                                                                                                                                                                P C [ 31 - 2 8 ]
0
M                                                 I n s tr u c t i o n                                           Re a d
M
u    A d d re s s                                      [2 5 – 2 1 ]                                              re g i s t e r 1
u
x                                                                                                                                                                            x
I n s tr u c t i o n                                           Re a d                                                                                    Z e ro
1              M e m or y
[2 0 – 1 6 ]                                              re g i st e r 2 da ta 1                                     1
A LU         AL U    AL U O u t
M e m D a ta                                                               0                        R e gi st e rs
I n str u c t ion                                M             W rite                                                                                   r es ult
[1 5 – 0 ]                                 u             re g i s t e r                                          0
In st ruc tio n                                       da ta 2
W r ite                                                                 [1 5 – 1 1 ]          x
I ns tr u ctio n                                                   W rite                                         4        1 M
d a ta                                                                                     1                                                                          u
re g is te r                                                     da ta                                                   2 x
I n s t ru c t io n                             0                                                                    3
[1 5 – 0 ]                                 M
u
x
M e m o ry                                         1
d a ta                                                 16                       32
S if t                                   ALU
S ign
r e g is te r
e x te n d             le f t 2                                control

I n s t r u c tio n [5 – 0 ]

write
write                                                                                                  control
control

Instruction decode/
Instruction fetch                                                            register fetch
0
ALUSrcA = 0
IorD = 0                                                                                            ALUSrcA = 0
Start                                         IRWrite                                                                                           ALUSrcB = 11
ALUSrcB = 01                                                                                           ALUOp = 00
ALUOp = 00
PCWrite
PCSource = 00
e)
')

-t y p
EQ

(Op = 'J')

=R
'B

(Op
=

p

= 'S                                                                Branch
(O

Jump
computation
or   (Op                         Execution                                       completion
W ')                                                                                                                                                       completion
= 'L
2                                               (Op                                 6                                                      8                                               9
ALUSrcA = 1
ALUSrcA = 1                                                                             ALUSrcA =1                                        ALUSrcB = 00
ALUSrcB = 10                                                                                                                                                                                PCWrite
ALUSrcB = 00                                        ALUOp = 01
ALUOp = 00                                                                                                                                                                               PCSource = 10
ALUOp = 10                                         PCWriteCond
PCSource = 01
(O
(Op = 'LW')

p
=
'S
W
')

Memory                                 Memory
access                                 access                                                 R-type completion
3                                      5                                            7

RegDst = 1
IorD = 1                                     IorD = 1                                 MemtoReg = 0

Write-back step
4

RegDst = 0
RegWrite
MemtoReg = 1

7/11
Problem 6

Suppose a MIPS processor uses the following simple 6-stage pipeline:

IF: Instruction Fetch
ID: Instruction decode
EX : Execute
MEM: Access Memory
WB: Write results to registers

1. Identify all the data dependencies in the following code.

lw     \$s5, 100(\$s2)

Sw     \$s3, 100(\$s5)

2. Fill in the instruction timing schedule assuming NO forwarding mechanism is
available.

Instruction          1    2    3   4   5    6   7   8   9   10 11 12 13 14 15 16 17 18 19 20
Add           IF   ID   REG EX MEM WB

8/11
Problem 7

A) Consider the following cache design:
 There is a single off chip cache (512 Kb)
 A hit on the cache takes 1 clock cycle
 It takes (Blocksize/4) cycles to service a miss including delivering data to
processor.
 The clock rate for this design is 100 MHz.

Assumptions
Assume that the read and write miss penalties are the same and ignore other
write stalls.
Considering block sizes of 16 and 128 bytes and
Direct mapping and 2-way set associative as options.
Assume the following miss rates for the 4 possible designs:
Block size (in bytes)
Cache size       Mapping option
16              128
Direct Mapped             0.04             0.01
128KB         2-way set
0.02           0.0095
associative

Find the design, which minimizes average memory access time (AMAT)
for the single-level external cache.

B) Given the following two implementations of a machine, one with cache (MC) and
one with out (MNC):

Instruction type   Inst Freq. mix   MC cycles   MNC cycles
ALU                     30%            2           3
Store                   20%            3           5
branch                  25%            1           2

Assume cache miss rate of 2% for instructions and 5% for data where cache
miss penalty is 40 cycles. What is the CPI for each machine, taking into
consideration the cache effect?

9/11
Problem 8

A 2-way set associative cache which uses blocks of 8 bytes is interfaced to the MIPS
machine. The cache size is 64 bytes. The replacement algorithm used is LRU.
Knowing that, solve the following

Consider the following sequence of memory accesses, given as byte addresses:

24 50 52      56 32 18 40 48 50 80              58    60 100

Label each reference in the list as a hit or a miss; show your work clearly,
cache is NOT empty initially, as seen below.

Add    24   50    52   56    32   18       40   48    50   80    58 60 100
H/M

D V            Tag           Data               D    V        Tag           Data
0 0 0                         X                 1    1   1                M[100000]
1 1 1                      M[101000]            0    0   0                   X
1 1 1                      M[110000]            0    0   2                   X
1 0 3                         X                 0    1   4               M[10011000]

10/11
‫مسودة‬

‫11/11‬

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