Chis status report
Next submission
• Due date 16 february 2010
http://www.mosis.com/ibm/ibm_schedule.html
• Process 0.13um IBM (8RF-DM)
Specs
• 4 Channels / 2 Token readouts / 1 DLL
• 256 cells/channels
• Max power = 100mW/channels
• Conversion time = 2us
• Readout time = 1us/channels
Improvements
• New IBM design kit 1.6.2.4 (Redraw layouts)
• Trigger at the input (New Comparators)
• Increased range (New buffer)
• Faster and better AtoD conversion
• Faster read-out (New D-Flipflop)
• Two-edges DLL (To do)
• Removal of the DC current in the IO pads
Trigger schematic
Internal Trigger
trigger output-
control write switch
latency 2-3 ns
threshold levels
simulated pulse (stalactite)
reset trigger –
restart writing
process
Internal Trigger
trigger output
latency 1-2 ns
simulated pulse (stalagmite)
threshold levels
reset trigger –
restart writing
process
-Works for both + and – pulses
-Acceptable latency (each sampling capacitor is rewritten every ~ 25 ns)
-Keep external trigger option in addition
A to D conversion Logic setup:
q12 compOUT Clear Reset dff
0 0 0 1
0 1 0 0
1 0 0 1
1 1 0 1
when Reset = 1, mux
sends gnd to Clock input
on register, stopping
count
simulation -> rollover protection
2.5 GHz clock
comparator output in red (stays high)
counting stops when 13th bit goes high
(400ps*4096=1.64us)
New input structure
Sampling capacitance
with read and write
switches
Rail to rail voltage
follower used as a
buffer for the stored
value.
Buffer
1V of linear input
dynamic
Sampling
Sampling
Buffered
value
Capacitance
value
Phase detector
The output1 fires when input1 comes first and vice versa. The pulse
width depends on the delay between the two input pulse.