Understanding Signal Integrity Solutions to Chapter Exercise Problems
Solutions for Chapter 5
5.1) In Chapter 8 we learn that high resistance is a factor in creating high conductor loss. Since
the board is „completed‟ it would be very expensive to re-route it with wider traces (even
though doing so would reduce conductor losses). A review of Tables 5.5 and 5.6 shows an
alternative: resistance (especially at high-frequencies) can be significantly reduced by
switching from the ED foil used in nearly all FR4 type laminate systems to rolled
copper. This reduces the trace resistivity and surface roughness without requiring a change
the circuit board artwork (although the stackup thickness may change if the traces were not
half-ounce to begin with).
5.2) From Table 5.4 we see that half-ounce copper is nominally 0.67 mils thick, but that the IPC
spec requires the inner layers to be no thinner than 0.47mils and outer layers no thinner than 1.3 mils.
By assuming all half-ounce traces are 0.65 mils thick the circuit model is valid for the „nominal
case‟, but not for „worst case‟ analysis. In fact, the model under-estimates the resistance of
the stripline layers and over estimates the resistance of microstrip traces. As we‟ll see in
Chapter 8, resistance is a strong factor in determining conductor losses, so the nominal model
will not properly predict losses in the worst case.
5.3) As we've seen, the boards produced by the two shops are very unlikely to have the same construction,
even if the same laminate system is employed. The following signal integrity problems could occur:
Timing may differ. Of special concern are those traces that have been experimentally tuned based
on the electrical characteristics of the boards manufactured by the high-end shop to obtain a
particular timing relationship
Microstrip characteristics are likely to be different between the two shops, because the plating and
solder mask processes will not be the same. This can affect trace impedance, and signal loss.
Stripline trace impedance may differ because of the use of different prepreg mats, resulting in a
different glass-to-resin ratio. Stripline trace shapes are not likely to be the same, which can also
change the impedance.
If the trace is controlled impedance the tolerance from nominal for either microstrip or stripline
may not be as tightly controlled.
The signal integrity engineer may have requested that non-functional pads (see section 5.2.1) be
removed by the prototype shop on high-speed nets. This technique can improve performance but is
not always done by high-volume shops.
The via aspect ratio should be checked to insure that the diameter of the smallest via used falls
within the capability of the volume production shop for a board of this thickness. Although more
of a reliability than a signal integrity concern, the volume production shop is unlikely to have as
aggressive via aspect rules as the prototype shop.
5.4) The signal integrity engineer should perform the following tests to uncover the potential
problems identified in problem 5.3:
Test equipment (such as a TDR) should be used to measure the impedance (single ended and
differential) of critical nets.
Timing (especially set-up and hold of data with respect to a clock) should be verified with an
oscilloscope or communications analyzer.
Signal quality should be checked with a high-bandwidth oscilloscope or communications analyzer
by examining the wave shape and amplitude of critical signals (especially important for high-
Page 1 of 30
Signal integrity should be verified with a high-bandwidth oscilloscope or communications
analyzer to examine representatives of all net classes for reflections and overshooting.
If possible, obtain a cross section of the board and compare the shapes of the traces with the
prototype. Grossly different shapes or dimensions may mean the impedance, loss or coupling will
5.5) From section 5.2.2 we see that presently, via aspect ratios in standard production fall
in the 6 to 8 range. Rearranging equation (5.1) and solving for via OD, we find that
(rounding to the smallest value) the via will be between 11 and 15 mils (0.28 to 0.38mm) in
Page 2 of 30
Solutions for Chapter 6
6.1) From section 6.5 and equation (6.3), we know the lines impedance limits the current
launched down a transmission line. In fact, the driver impedance and the transmission line impedance
form a series circuit which limits the current that is initially launched.
From Ohms law, the current is I 27 .5mA
R g Z o 30 50
This is the current the driver pulls from the ASIC power supply to drive the transmission line, but it is
only an estimate of the total current. This value does not include the current required to operate the
logic internal to the pad driver (which is usually low), or the „overlap‟ current (which may be high) that
appears when the driver switches.
6.2) From equation (6.4) we know the launched voltage is found by applying the voltage
Vi Vcc 2 .2 1.375V
Zo Z g 30 50
6.3) Using the voltage divider principle shown in example 6.2, the launched voltages are:
Vcc Rg Vi
3.3 30 2.06
3.3 50 1.65
3.3 75 1.32
2.2 30 1.38
2.2 50 1.10
2.2 75 0.88
From these results we see that either a 50 or 75 driver connected to the 3.3V supply, or a 30
driver connected to the 2.2V supply, meets the stated requirements.
6.4) The worst case current draw of 750mA occurs when all 32 drivers switch
simultaneously. The maximum current per driver is therefore 23.4mA .
The design task then becomes finding the combination of driver impedance and transmission line
impedance that launches no more than 23.4mA when the supply voltage is 3.3V.
The following table is created using the technique illustrated in Example 6.1:
Zg Zo i
50 50 33mA
75 75 22
50 75 26.4
75 50 26.4
From this we see that the combination of a 75 driver and 75 trace causes 22mA to be launched,
which just satisfies the requirement. Incidentally, although it‟s an important consideration, total power
supply current is usually only one of the factors a signal integrity engineer uses to select the driver and
Page 3 of 30
6.5) From elementary circuit theory we know the “I square R” heating is the resistance of the driver
multiplied by the square of the current it launches. We‟ll use this to estimate the driver power
dissipation with the understanding that we are ignoring the power dissipated by the driver logic
The 2.2V/30 combination launches 27.5mA down the 50 transmission line,
dissipating Pd 27 .5mA 30 22 .7 mW . The other two choices (75 and
50 drivers connected to the 3.3V supply) each dissipate more than twice that
power. Therefore, the 30 driver connected to the 2.2V supply will heat the
ASIC the least.
This example assumes that the power when pulling the line low is the same as the power when driving
the line high. Often this is not the case, but the same approach used in this example can be used to
determine the pull down power. To calculate the actual die temperature we would need to know the
thermal impedance of the ASIC and its heat sink, and an estimate for how often the driver is driving
high and driving low.
6.6) The impedance is found from equation (6.1) to be Z o 50 .
C 118 pF
The propagation delay is found from equation (6.2) and then scaled to account for the lines actual
length: tpd LC 280nH 118 pF 5.75nS / meter .
Because the line is half a meter long, the total delay is 5.75nS/meter x 0.5 meter = 2.87nS.
6.7) The propagation delay as given by (6.2) is tpd LC 50nH 20 pF 1nS .
Rearranging equation (6.5) and using 0.5 as the limit, tr > 2 LC . That is, a signal won‟t
experience significant transmission line effects if its rise time is twice as long as the delay of the
interconnect. This is the same as saying that reflections won't occur if the rise time is greater than the
round trip time of the signal, and this is the origin of that rule of thumb. In this example, a 2ns signal
rise time or smaller will experience transmission line behavior.
Using the more conservative 0.125 limit, a signal rise time as slow as 8nS would be expected to
experience transmission line behavior.
6.8) From (6.1) for the 1 meter long case:
L 280nH / meter 1m 280nH
Zo = 50.5
C 110 pF / meter 1m 110 pF
From (6.2), tpd LC 280nH / meter 1m 110 pF / meter 1m 5.55nS per
When calculating the delay for the 5cm long line case, the length units in the numerator and
denominator cancel, but the units do not cancel when computing the impedance:
Page 4 of 30
L 280nH / meter 5cm 280nH
Zo = 50.5
C 110 pF / meter 5cm 110 pF
tpd LC 280nH / meter 5cm 110 pF / meter 5cm 278 pS per 5cm.
6.9) Equations (6.1) and (6.2) relate the capacitance and inductance to the impedance and
delay. In this problem we have two equations and two unknowns; this lets us find
L and C in terms of Zo and tpd by simultaneously solving (6.1) and (6.2). Doing so
td 174 ps 2
Zo 50 2
L t d Z o 174 ps 2 50 2 8.7nH
6.10) Equation (6.5) can be used to determine if the stub is long electrically, and so
should be modeled as a transmission line or as a lumped circuit. From section 6.7 we‟ll select the
most conservative rule: LC ≥ 0.125tr , where tr is the signal rise time. Although we don‟t know L
or C, we do know tpd which is equal to LC : it‟s 166ps/inch x 0.5 inches = 83ps. Therefore, from
equation (6.5), the stub is considered electrically long if 83ps is greater than 0.125tr . Computing, we
find that this is the case: 0.125 t r 0.125 350 ps 44 ps . Since the stub is electrically long, it
must be modeled with a transmission line.
6.11) From section 6.6 we know the decoupling capacitors must have an impedance very much
lower than the parallel combination of the ten 50 traces. The parallel combination of the ten
transmission lines has an impedance of 5; if we assume one tenth of that is „very much lower‟ the
capacitors must have an impedance of 0.5 or less.
From Chapter 1, we know the 3dB bandwidth of a signal having a 1ns rise time is 350MHz. From
elementary circuit theory we know the reactance of a 10nF capacitance at 350MHz is:
X C 46 m , and the reactance of the inductance is:
6.28 f C
X L 6.28 f L 1.5 .
Therefore, at 350MHz the parasitic inductance dominates and for all practical purposes the capacitor
has an impedance of 1.5.
The impedance will be reduced by placing multiple capacitors in parallel, and in fact no less than 3 of
the specified capacitors must be used to obtain a net impedance at 350MHz of 0.5. However, a
fewer number of capacitors would be needed if the parasitic inductance was less than the 700pH
assumed in this example. For instance, since the body style and mounting determine the series
inductance, switching to a low inductance capacitor, or using larger diameter vias to connect the
capacitors to the power and ground planes will require fewer capacitors.
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This approach yields a good engineering estimate, but a CAD analysis of the power system is
necessary to demonstrate that the impedance is low enough for all of the frequencies contained in the
signal, not only the highest frequency ones.
6.12) We can see from Figure 6.8 that the return current passes through the decoupling capacitors
associated with both power supplies. This means that as far as creating an AC short is concerned, the
two sets of capacitors are in series. If three capacitors were used for each power supply (as in the
previous example), the series capacitance would be 1, twice as high as the 0.5 minimum.
Therefore, a minimum of 6 on each supply would be necessary to reduce the impedance to below
Page 6 of 30
Solutions for Chapter 7
7.1) We can find the impedance from Equation (7.3) by assuming t = 0.65 mils and r =
4.2 as follows:
94 b w 94 16 5
Zo ln = ln 60 .2
r w t 4.2 5 0.65
This is in reasonable agreement with the more precise Figure 7.8, which shows h = 18.8 mils
to obtain 60.
7.2) We can find the impedance from equation set (7.4) by assuming t = 0.65 and r = 4.2
r 1 r 1 w 4.2 1 4.2 1 8
r _ eff = 3.18
2 2 w 10h 2 2 8 52
60 7.5h 60 39
Zo ln = ln 50
r _ eff w 1.25t 3.18 8 0.813
This is in reasonable agreement with the more accurate Figure 7.8, which shows h = 4.7 mils
to obtain 50. It‟s also worth noting that, as expected, the effective dielectric constant is
lower than the dielectric constant of the laminate material.
7.3) Figure 7.8 shows the plane separation for half-ounce stripline on FR4. From that
graph we see the distance increases from 13.3 mils when the trace is 5 mils wide to 19.5 mils
when its 8 mils wide. Each stripline layer will therefore be 6.2 mils thicker if the trace width
changes from 5 to 8 mils.
7.4) Recalling that Dk and εr are synonymous, equation (7.5) is used to find the delay.
tpd 84.7 r 84.7 4.2 173.6 pS per inch (68.7ps/cm). Since the line is 12” (30.5cm)
long, the signal will require 2.1nS to travel from the generator to the load. Because the trace
is stripline, the trace geometry or impedance are not factors in determining the delay.
7.5) Because the board thickness is fixed at an upper limit, to maximize the number of
routing layers each layer must be as thin as possible. From Figure 7.8 we can see that in
general, narrow, low impedance traces require thinner dielectrics than wide, high-impedance
ones. Therefore, for this design a narrow, low impedance trace is suggested.
However, as we‟ve seen, low impedance traces cause more current to be drawn from the
ASIC I/O supply, possibly increasing that part of the design.
7.6) From sections 7.7 and 7.8 we can see that lowering the dielectric constant raises the
impedance and lowers the transmission line delay by the square root of the ratio of the
Therefore, the impedance increases and the delay decrease by a factor
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of 1.058 . This makes the impedance on the new laminate equal
to 50 1.058 53 .
If we assume the delay time for FR4 is 174 ps/inch (68.6 ps/cm) as shown in problem 7.4, the
174 ps / inch
delay on the new laminate becomes 164.5 ps/inch (64.7 ps/cm).
7.7) Since the striplines have been formed on the same layer, we‟ll assume Dk is the same for
both traces. This makes the delay time identical. Neither the trace impedance nor the width
affects the delay, tpd. As we‟ve seen, this is a fundamental characteristic of stripline
7.8) Since the trace is stripline, changing the distance between planes (b in figure 7.1) has
no effect on the delay. However, from Figure 7.8 we see that in general, reducing
the distance between the return planes lowers trace impedance. Therefore, the striplines on the
thinner board will have a lower impedance but the delay time will not change.
7.9) The propagation delay time tpd is 171.4 pS/inch (or 67.5 pS/cm). From
equation (7.5) the delay time is tpd 84.7 r ps/inch (or tpd 33.5 r ps/cm).
Rearranging and solving for εr, we have: r
84.7 ps / inch 33.5 ps / cm .
Solving, εr is found to be 4.1. This technique can be used to determine r from TDR (Time Domain
Reflectometry) measurements), but it requires that tpd be measured with great precision. Doing so can
be difficult, especially if the line is long or has high losses.
7.10) Once Rac is known for a given frequency we can use equation (7.2) to find the AC resistance at some
Rac _ f 2 Rac _ f 1 7 7 / meter 3.16 22.1 / meter . This assumes
the frequency is not so high that the effects of surface roughness comes into play.
7.11) This is a direct application of equation (7.1), and the problem statement provides all the
required information except for the trace capacitance. That can be obtained from Figure 7.4
where we see that on FR4 stripline capacitance for a 50 trace of any width is about
Applying equation (7.1) we find at 100MHz:
G 6.28 C f LT 6.28 3.5 pF / inch 100 MHz 0.02 44 x10 6 Semens/inch.
Page 8 of 30
Similarly for part (b), G = 440x10-6 Semens/inch at 1GHz.
These values are used directly in a SPICE lossy transmission line model (such as the “O” and
“W” elements discussed in Chapter 3), but their significance is not obvious. To put
them in perspective, we recall that conductance is the reciprocal of resistance. The
conductance at 100MHz is equivalent to a 23K resistor to ground; the resistance falls to
2.3K at 1GHz. These values are much higher than the 50 trace impedance but nonetheless
they are surprisingly low. For instance, at 1GHz 2.3mA is shunted to ground for every volt launched
by the driver.
7.12) The W line model requires 6 parameters:
- Lo (the trace inductance)
- Co (the trace capacitance)
- Ro (the trace DC resistance)
- Go (the dielectric loss at DC)
- Rs (the trace AC resistance, called Rac throughout this book)
- Gd (the dielectric AC loss).
The capacitance and inductance (and sometimes the conductance and AC resistance) are
known if a 2-D field solver is available. The task then is to appropriately format these values
for the W line model. However, in this problem we‟ll assume a 2-D solver is not available and
so all of the parameters will be estimated by hand.
Referring to Figure 7.2, the DC resistance for a 5 mil wide, half-ounce 50 stripline is 0.2;
from Figure 7.4 C is 3.5pF/inch on FR4; from Figure 7.5 L is 8.7nH/inch, and from Figure 7.6
Rac is 0.7/inch at 350MHz. For our purposes in this book the capacitance and inductance will
not change with frequency. However, frequency does alter the AC resistance and conductance,
and because of this the W line circuit model requires that the values be scaled in terms of
To find G we use the same method as in the previous problem:
G 6.28 C f LT 6.28 3.5 pF / inch 350 MHz 0.02 154 x10 6
Because the laminates used in modern circuit boards have very low DC loss, Go is generally
taken to be zero. A higher value can be used if the applied voltage is very high, or for those
laminates susceptible to moisture uptake if the operating humidity is high.
Since conductance increases directly with frequency, for the W line model Gd is scaled by
dividing G by the frequency at which it was measured:
G 154 S
Gd 440 x10 15 semens/inch per Hz.
f 350 MHz
Since the skin effect causes Rac to increase as the square root of the frequency, Rs is scaled for
the model by dividing Rac by the square root of its measured frequency:
Rs 37 .4 x10 6 per square root Hz.
f 350 MHz
The model then becomes:
Page 9 of 30
Page 10 of 30
Solutions for Chapter 8
8.1) Equation (8.1) can calculate this exactly, but we can use Figure 8.3 to come up with an estimate.
Receiving 175mV from an 800mV signal means the signal swing has been reduced to 22% of the
original. From Figure 8.3 we see the „Received‟ curve crosses the 22% mark on the „Signal Swing‟
axis when the loss is 13.2dB. To meet specification, the channel must not have loss higher than this.
Chapter 17 shows how to find the signal swing when only the loss in dB is known.
8.2) Since in this problem loss is the only factor, Figure 8.6 provides all the information necessary to
answer this question. We see in the figure that wide, high-impedance traces have the lowest losses. For
instance, a 10 mil wide 70 stripline or microstrip has less loss than a 5 mil wide 50 stripline or
microstrip. Therefore, considering only loss and considering only the values in the graph, the design
should use a 10 mil wide, 70 trace. In practice, other factors such as crosstalk, board thickness and
test equipment compatibility all play rolls in deciding the trace impedance.
8.3) From equation (8.3) we know that the conductor loss depends on the value of the loop resistance, Rac.
Referring back to Figure 7.6 we see that on FR4, Rac for an 8 mil wide, half-ounce stripline is
0.49/inch at 350MHz. We saw in problem 7.10 how to use equation (7.2) to find Rac at any frequency
once it is known at some other frequency. Repeating that process here, we find that at 1.25GHz, Rac is
1.9 times larger than it is at 350MHz. Therefore, at 1.25GHz Rac is 0.93/inch, or 14.7 for 15.75
inches. Applying equation (8.3) to determine the conductor loss in dB, we find:
4.3 Rac 4.3 14.7
c = 1.3dB .
From Figure 8.3 we see that a loss of 1.3dB means nearly 14% of the signal is dissipated before it
reaches the load. The total loss will be higher than this because the dielectric loss must also be included
when figuring the total loss.
8.4) The signal integrity engineer is correct: moving to a low Dk material will improve
both the dielectric and conductor losses, but only because the traces are controlled impedance, and
then only providing the board thickness remains the same. The laminate data appearing in Table 5.1
shows why both of these assertions are true: We notice that a low Dk laminate generally corresponds
to a low LT value. Assuming this is true for the laminate chosen in this application, this accounts for
the lower dielectric loss, but it has no bearing on lowering the conductor loss. In this situation a low
Dk also results in lower conductor loss because with the lower Dk the conductor traces must become
wider to keep the impedance at a specific value (50 in this instance), while at the same time keeping
the distance between the trace and the return planes the same. This is necessary to keep the overall
board thickness the same.
The end result is that for the same board thickness and impedance, moving the design to the low Dk
laminate causes the traces to become wider and to have lower dielectric and conductor losses. Of
course, the significant side effect is that the traces are wider than in the original design, which may
require the board artwork to be redone.
8.5) The faster rise time signals mean transmission line effects are likely to be more
severe, including crosstalk (see Chapter 10) and reflections (Chapter 11). Also, circuit board traces
that were short enough to be reflection free (or nearly so) at 1nS may well appear long enough to
experience transmission line effects at 700pS. A more subtle effect involves signal attenuation. The
faster rise time means the signals launched from the new version of the gate array will contain higher
frequency harmonics than the slower signal. From Figure 8.5 we can see how these higher frequencies
cause higher loss than signals launched from the original gate array. As we‟ve seen, loss reduces the
signal amplitude and can cause distortion. If the trace is long enough, the extra setup time advantage
touted by the manufacture could be outweighed by the adverse signal integrity impact. Only
Page 11 of 30
simulation or lab measurement can determine if the new part will work in the existing design.
8.6) Because the trace is stripline, changing the impedance has no effect on dielectric loss. To
calculate the loss at 1GHz, we notice from equation (8.4) that dielectric loss changes directly
with frequency. Therefore, reducing the frequency by a factor of 2 results in the dielectric loss being
cut in half to 1.5 dB.
8.7) From Table 5.1 we see that for IS410 at 1GHz, Dk = 3.9 and the LT = 0.019. From
Chapter 1 we know that the 3dB bandwidth of the signal can be estimated by:
BW 500 MHz 0.5GHz . For simplicity we‟ll assume most of
tr 700 pS
the signal energy is at this frequency or lower. We now have all that is necessary to find
the dielectric loss with equation (8.4). Since the trace length is given in cm, 0.91 is chosen for
d K f r LT = 0.91 0.5 3.9 0.019 0.017 dB / cm 40 cm 0.68 dB .
8.8) From Chapter 1 we can determine that the fundamental frequency of the 4 ns pulse
is 250MHz, and each harmonic will be 250MHz higher in succession.
From this chapter we know the total loss is the sum of the conductor and dielectric losses,
and we know that each increase with frequency.
To find the conductor loss we must first find Rac; to find the dielectric loss we‟ll assume that
r = 4.2 and the LT = 0.02. For simplicity in this problem we‟ll assume these are the same at
all frequencies, but in fact the dielectric constant and loss tangent change with frequency.
As we can see in equation (8.4), the dielectric loss increases linearly with frequency. For
instance, the dielectric loss at the fundamental frequency (250MHz, or 0.25GHz) is:
d K f r LT 2.32 0.25 4.2 0.02 0.024dB / inch .
From Figure 7.6 we find that Rac = 0.7/inch at 350MHz. As we showed in problem set 7.10,
we can find Rac at any frequency by applying equation (7.2). For instance, Rac at the
fundamental frequency is:
Rac _ f 2 Rac _ f 1 0.7 0.59 / inch .
We can now find the conductor loss from equation (8.3):
4.3 Rac 4.3 0.59 / inch
c 0.051 dB / inch
The total loss is the sum of the dielectric and conductor losses, and at 250MHz is:
t 0.024 dB / inch 0.051 dB / inch 0.075 dB / inch .
Page 12 of 30
The following table shows the results for the fundamental and first 5 harmonics, where the
frequency is in MHz and the losses are in dB/inch:
Freq d c t
250 0.024 0.051 0.075
500 0.047 0.072 0.119
750 0.071 0.088 0.159
1000 0.094 0.102 0.196
1250 0.118 0.114 0.232
1500 0.141 0.125 0.266
From this example we can clearly see how each of the pulses harmonics are attenuated more
than the previous ones, which causes pulse distortion.
8.9) From section 8.4.1 we know that surface roughness begins to significantly increase trace resistance
when the roughness is about equal to the skin depth, but we have not shown how to calculate skin
It can be shown (see  in the text) that for copper at room temperature, the skin depth
(delta) in meters is:
4.5 10 9
, when f the frequency in MHz.
By solving the equation for f and then setting the skin depth equal to the average roughness of
the copper foil we can find the frequency where the effects of surface roughness becomes
apparent. Assuming = 1μm (the moderate value used for Ra in this chapter) we find f =
4.5GHz. This falls to 1.1GHz when Ra increases to 2μm (the more aggressive value).
Page 13 of 30
Solutions for Chapter 9
9.1) From Table 9.1 we see that the odd mode impedance is lower than then even mode impedance, and the
characteristic impedance lies between the two. We can take this general observation as a rule without
proof and state that this will always be the case. Therefore, Zoo = 36, Zo = 60, and Zoe = 97.
9.2) Using an argument similar to that in Problem 9.1, we can state that that as a rule the odd
mode delay is less than the even mode delay for either stripline or microstrip traces. The
odd mode delay is therefore 142pS/inch and the even mode is 154pS/inch.
9.3) Using the description of the inductance and capacitance matrix appearing in section 9.2.1,
the self inductance (Ls) and self capacitance (Cs) of trace 3 is L33 and C33.
From the inductance matrix we see that the inductance and capacitance are given
for a length of line 1 meter long, making L33 286.1nH/m, and from the capacitance matrix
C33 is 118.0pF/m.
We find the total mutual inductance (Lm) and capacitance (Cm) by summing the trace 3 mutuals.
For the inductance the mutual terms are 35.3nH/m between trace 3 and 2 (and again, between trace 3
and 4), and 9.705nH/m between trace 3 and 1 (and between trace 3 to 5). The total mutual inductance
is then Lm = 2(35.3nH/m) + 2(9.705nH/m) = 90.0nH/m.
In a similar way, Cm is found to be -11.69pF/m (but it would be used as a positive value in simulations
9.4) We know from Table 9.1 that two cases bound the change in impedance: the largest occurs when
the aggressors switch in phase, and the lowest is when they switch out of phase with the victim.
For a two trace system this corresponds to the even and odd mode impedances discussed in section
Even though in this case more than two traces are involved, we can find the bounds by summing the
mutual terms and using the equations for the even and odd mode impedances [equations (9.4) and
The mutual inductance and capacitance was found in Problem 9.3 to be 90nH/m, and -11.69pF/m. The
self inductance and capacitance was determined to be 286.1nH/m and 118pF/m.
The even and odd mode impedances are then:
Ls Lm 286.1nH 90nH 376nH
Z oe 59.5
C s Cm 118 pF 11.69 pF 106.3 pF
Ls Lm 286.1nH 90nH 196.1nH
Z oo 38.9
Cs Cm 118 pF 11.69 pF 129.7 pF
Notice that (as discussed in section 9.2.2) even though the capacitance matrix reports the mutual
capacitance as negative, it‟s used as positive in the equations.
9.5) Using the same reasoning and strategy from Problem 9.4, we can find the worst case times by
summing the mutual terms for the 5 trace system and using them in the two trace even and odd mode
propagation time equations [equations (9.5) and (9.7)].
Page 14 of 30
Doing so we find:
tpdeven ( Ls Lm )(Cs Cm ) 376nH 106.3 pF 6.3nS
tpdodd ( Ls Lm )(Cs Cm ) 196.1nH 129.7 pF 5.0nS
As we did in problem 9.4, we take the mutual capacitance as positive, even though it‟s negative in the
capacitance matrix. Also, because the matrices are per meter, the even and odd propagation times are
for traces 1 meter in length.
9.6) We know from sections 9.4 and 9.5 that the even and odd modes have the same delay for stripline
traces, but not for microstrips. Since the results of problem 9.5 show the delays to be different, the
matrices represent a microstrip.
9.7) From sections 9.4 and 9.5 we know the odd and even mode delays will be the same if the
trace is stripline, but they will have different values if the traces are microstrip.
Using equations (9.5) and (9.7) to find the even and odd mode propagation time we find:
tpdeven ( Ls Lm )(Cs Cm ) 10.52nH 2.04nH 2.835 pF 0.549 pF 169.4 pS
tpdodd ( Ls Lm )(Cs Cm ) 10.52nH 2.04nH 2.835 pF 0.549 pF 169.4 pS
As we have in the previous problems, we take the mutual capacitance as positive, even though it‟s
negative in the capacitance matrix. Also, because the matrices are per inch, the even and odd
propagation times are for traces 1 inch in length.
Since the even and odd delays are identical, the matrix must represent a stripline.
9.8) From Chapter 7 [equation (7.5)] we know the delay of a stripline is
tpd 84.7 r ps/inch.
Since in this case r is 4.0, this gives a delay of tpd 84 .7 4 169 .4 ps/inch, which matches the
delay found for the stripline in problem 9.7.
This shows that, as described in section 9.5, in stripline the delay is determined by the dielectric
constant, and that the results match the even and odd mode delays found by equations (9.5) and (9.7).
9.9) The first column in the inductance and capacitance matrices show how the coupling from trace 1 to its
neighbors progressively declines as the distance increases. For instance, the inductance matrix shows
the coupling from trace 1 to 2 (L12) is 35.57nH, and it falls to 9.705nH two traces away from trace 1.
The coupling continues to fall as the distance increases, so that by a distance equal to 4 traces away it
has been reduced to 2.416nH (the value for L15).
Page 15 of 30
The same results are obtained when the coupling is measured from trace 5: the coupling from
trace 5 to 4 (L54) is 35.57nH, and it‟s 9.705 nH two traces away. The coupling from trace 5
to 1 (L51) is 2.416nH, the same as L15. Since these values are identical to the values using trace 1 as a
reference, the traces are symmetrically positioned.
9.10) From Chapter 6 and section 9.6 we know that voltage divider action between the driver
impedance and the trace impedance determines the launched voltage. From section 9.5 we
also know that the transmission line impedance is the lowest under odd mode conditions,
and it‟s the highest in the even mode. These two cases set the bounds for the trace
impedance, and so, for the launched voltage.
Using equation (9.6) we find the odd mode impedance to be:
Ls Lm 10.52nH 2.04nH
Z oo 49.3
C s Cm 2.835 pF 0.549 pF
The even mode impedance is found with (6.4):
Ls Lm 10.52nH 2.04nH
Z oe 73.3
C s Cm 2.835 pF 0.549 pF
The voltage divider principal is described with equation (6.4):
Zo Z g
Where Zo is either 49.3 or 73.3, Vcc is 2.5V and Zg (the ASIC I/O impedance) is either 25 or
Solving for Vi when Zg is 25 we find that under odd mode conditions the launched voltage is
1.66V. It climbs to 1.86V under even mode switching.
When Zg is 10 the launched voltage ranges from 2.1V to 2.2V.
We see from this that (confirming what we saw in section 9.6) the launched voltage changes
depending on the switching mode. We also see the effect of lowering the driver impedance:
the launched voltage is higher in both the even and odd mode cases, and the difference
between the even and odd mode voltages is less.
9.11) The even and odd mode delays were found in problem 9.7 to be 169.4ps. Repeating those
calculations but keeping the mutual capacitance negative yields:
tpdeven ( Ls Lm )(Cs Cm ) 10.52nH 2.04nH 2.835 pF (0.549 pF ) 204 pS
tpdodd ( Ls Lm )(Cs Cm ) 10.52nH 2.04nH 2.835 pF (0.549 pF ) 137 pS
We can see that these results are incorrect for two reasons: First, we know that the matrices in
problem 9.7 represents a stripline, and we know the delays therefore must be identical. Second, the
delays do not match those found by using the dielectric constant (as shown in problem 9.8).
Page 16 of 30
Solutions for Chapter 10
10.1) Equation (10.2a) is used to find the near end coupling factor (NEXT). We know
that far end crosstalk (FEXT) is zero for low loss striplines, but we‟ll compute it to show a typical
result that equation (10.1a) produces under these conditions.
To use these equations we must identify the self and mutual capacitances and inductances, and
determine the impedance. From Chapter 9 we know that for this problem Ls = 4.447E-7; Lm = 8.28E-
8; Cs = 1.088E-10; Cm = -2.025E-11.
From equation (6.1) in Chapter 6 we know that the impedance is Z o ; here
Zo 63.9 .
Cs 108.8 pF
We can now use equation (10.1a) to determine Kf:
Kf 0.5 m Z o Cm 0.5
Z 63.9 20.25 pF
-249 x 10-15 s/m, and equation (10.2a) to determine Kb:
4 444.7nH 108.8 pF 63.9 63.9 20.25 pF
m Z o Cm
4 Ls Cs o
0.093. Notice that, as discussed in Chapter 9, the mutual capacitance is taken as
positive in the calculations, even though the field solver properly reports it as a negative
number. We also see that since the field solver reported its results in terms of meters, Kf
has units of seconds/meter. As expected, Kb is unit less.
We further note that although Kf is very small, in this problem it is not zero even though the traces
are stripline. As a practical matter Kf is so small as to be virtually zero, especially when it‟s
compared to the values calculated for microstrip (see problem 10.2).
Nonetheless, because the result is not zero, it‟s apparent that the field solver did not precisely
calculate Lm and Cm. The end result is that a SPICE simulation using these data would show some
(albeit extremely small, as shown in Problem 10.3) forward crosstalk.
10.2) We solve this problem in a manner similar to problem (10.1). Doing so we find that
Zo is 63.9, Kf is -231.4 x 10-12 s/m, and Kb is 0.052. Since the data in this problem
describes microstrip, we would expect Kf to be non-zero. The fact that it is
negative shows that must be greater than Z o Cm , and this is the case:
8.3 10 10 , while Z o Cm 3.6 10 10 .
Compared to the results in the previous problem, we see that these results for Kf are three orders of
10.3) We use equation (10.1b) to find FEXT, noting that length is 0.3m, dv is (1.8V –
Page 17 of 30
0.8V = 1V) and dt is 250ps.
For the stripline FEXT Kf length 249 10 15 0.4 399 V
dt 250 ps
For the microstrip it‟s -370mV since Kf is -231.4E-12 s/m. We see that although FEXT should be
zero, its calculated value is very small, and (as far as digital signaling is concerned) is zero in
10.4) To find NEXT we use either equations (10.2b) or (10.2c), depending if the line is long. To determine
this we must first use equation (10.2d) to find the electrical delay of the coupled region. For the
tpd length Ls Cs 0.4 367nH 90.0 pF 2.3nS . Since twice this is larger
than the rise time, the line is electrically long and equation (10.2c) is used to find NEXT:
NEXT Kb dV 0.0931 93mV .
In a similar way, we find the microstrip tpd to be 2.3ns, and [again using equation (10.2c)] we find
NEXT is 51.8mV.
10.5) Central to this rule of thumb is the premise that the vias must not be separated by more than
a quarter wavelength at the highest frequency present in the signal. We‟ll assume the 3dB
bandwidth described in Chapter 1 is that frequency. Once the highest frequency has been
determined, the physical distance in meters that it represents can be found by calculating
the wavelength as described in Chapter 17.
From Chapter 1 we know that the 3dB bandwidth of a signal can be estimated by
BW . Scaling this to MHz and ns, BW .
From Chapter17 the wavelength in meters when the frequency is in MHz is
. By assuming r = 4.2 for FR4, and that the bandwidth is the highest
frequency present, we can substitute bandwidth for frequency and find the wavelength in terms of the
signal rise time in ns to be about:
0.4 tr .
The rule of thumb requires the distance between vias to be less than a quarter wavelength, so by
dividing this result by 4 we have a maximum distance of: d 0.1tr , which matches the results in
Our approach assumes that only frequencies up to the 3dB frequency is important, and we justify this
gross simplification by noting that the lower frequency harmonics present in the signal will have
longer wavelengths than the 3dB wavelength, and that any frequencies higher than the 3dB frequency
Page 18 of 30
will have such low energy that they can be ignored. These simplifications are reasonable since we are
developing a rule of thumb, but the results should be verified by simulation or measurement for a
10.6) We‟ll first use equation (10.1) to find FEXT , and then NEXT from (10.2).
As we did in problem 10.1, we begin by finding the impedance:
Zo 62.42 .
Cs 102.9 pF
We can now find Kf, and because the matrices are in terms of meters, the results are in
seconds per meter:
L 9.662 108 11
62.42 62.42 2.23310
Kf 0.5 m Z o Cm 0.5
Therefore, the FEXT voltage, noting that dv is 1.68V and dt is 0.1ns, is found to be:
FEXT Kf length 77.03 1012 0.3 388.2mV
We now turn our attention to finding the reverse crosstalk voltage. We note that the transmission
line has a delay of tpd Ls Cs = 6.4ns/meter. Since twice this is much longer than the signal
rise time, we‟ll use equation (10.2c) to find the actual crosstalk voltage once Kb has been determined.
Using equation (10.2):
4 Ls Cs Zo
9.662 10 8
62.42 2.223 10 11 0.1143
4 400.9nH 102.9 pF
Since dv is 1.68V, NEXT Kb dV 0.11431.68V 192mV
10.7) The graph represents trace separation in terms of trace widths, but in this problem we have
the separation in mils. Converting, we recognize that the distance of 10 mils is equivalent
to a separation of 2 on the graph. From the solid, 50 curve we find that Kb is 0.023 for that
10.8) The setup is similar to that shown in the bottom of Figure 10.8 with the center trace the
victim, but for this problem the two outer traces are driven as aggressors. We‟ll
approach this in the same way as Problem 10.1, but here we‟ll combine the mutuals from traces 1 and
3 to find Lm and Cm.
Page 19 of 30
We first find the impedance to be Zo 59.2 . Noting that since the 2ed
Cs 123.3 pF
trace is the victim, for Ls and Cs we use L22 and C22.
Before we can use equation (10.a) to find Kf, we must first determine Lm and Cm. Since there are
multiple aggressors, the mutuals are summed to find the total. Focusing for a moment on just the
inductance, in this particular case, Lm L12 L32 . Since the outer traces are the same distance from
the center trace, the mutuals are identical and are the same as L12. Therefore,
Lm L12 L12 2L12 . In a similar way Cm 2C12 .
From the model for this problem, L12 = 1.124E-7 and C12 = -2.935E-11, making
Lm 2.248 E 7 and Cm 58 .7 E 12 .
We can now use equation (10.1a) to determine Kf for this three trace system (once again noting that
Cm is taken as positive):
m Zo Cm 59.2 58.7 pF 0.249
4 Ls C s Zo 4 432.7nH 123.3 pF 59.2
To find the actual coupled voltage NEXT, we must first determine if the coupled region is electrically
long. As in the previous problems, we find:
tpd length Ls Cs 0.3 432.7nH 123.3 pF 2.2nS . Since this is larger than
twice the rise time, the line is electrically long and equation (10.2c) is used to find NEXT, noting that
dv is 1.65V:
NEXT Kb dV 0.2491.65 411mV .
Page 20 of 30
Solutions for Chapter 11
11.1) The voltage reflection coefficient at the load is found from equation (11.3) to be:
Rl Z o 100 75
Rl Z o 100 75
11.2) Using equation (11.3), the reflection coefficient at the generator is:
Rg Z o 10 75
Rg Z o 10 75
11.3) We begin by arbitrarily assuming Vne is 1.5V. This value yields a convenient
magnitude for the current pulse.
From Ohms law [equation (11.1)] the value of the current pulse traveling with the voltage pulse is:
Ii 20mA .
These two pulses are no longer in the proper proportion when they reach the 100 load resistance.
For instance, the 1.5V incident voltage dropped across a 100 load requires a current of
Il 15mA rather than the 20mA that was launched.
From the solution of Problem 11.1 we know that l is +0.143, and by applying equation (11.2) we
find that the reflected voltage is:
Vr Vi l 1.5 (0.143 ) 0.21V .
From equation (11.4), and assuming the initial load voltage is zero, the total voltage is:
Vt Vi Vr V p 1.5V 0.21V 0 1.71V .
The value of the reflected current is I r I i 20 mA (0.143 ) 2.86 mA (noting that
the reflection coefficient for the current is (-) compared to the voltage, as described in section
11.3.1). Once again assuming the load current is initially zero, the total current through the load is:
It Ii Ir Ip 20mA 2.86mA 0 17.1mA.
The magnitudes of these voltage and current pulses satisfies Ohms law, because
Rl 100 .
I t 17 .2mA
Taking this one step further, we can verify that the reflected voltage and current waves have a ratio
equal to the transmission line impedance:
Page 21 of 30
Zo 75 .
I t 2.86 mA
The negative value associated with the current indicates that the current pulse is
traveling from the load to the generator and does not indicate that the transmission
line impedance should be negative. Since the impedance must be positive, the
magnitude for the current is used.
11.4) To determine the magnitude of the reflections, the values of the incident waves must first be
From voltage divider principle (see Chapter 6), we find that a 1.4V pulse is launched. To satisfy
Ohms law [see equation (11.1)], this pulse is accompanied by a 23.5mA current pulse.
From Table 11.1, the voltage reflection coefficient for an open circuit is +1. The current reflection
coefficient is -1 (see section 11.3.1). This means the entire voltage and current waves will reflect
from the open circuit, making the reflected voltage wave 1.4V and the reflected current -23.5mA.
11.5) The same methods used in the previous problems to find the launched voltage and the load and
generator reflection coefficients are used to solve this problem.
The launched voltage (Vi) is found by the voltage divider principle to be:
Vi 1V 0.50V .
Rl Z o 100 50
The reflection coefficient at the load is: l 0.333 , and the
Rl Z o 100 50
reflection coefficient at the generator is:
Rg Zo 50 50
Rg Zo 50 50
Since the load reflection coefficient has a value greater than zero, the incident wave will create a
positive polarity reflection that causes the total voltage to be greater than the launched voltage.
And, since the reflection coefficient at the generator end is zero, the energy reflected from the load
will not re-reflect from the generator. Therefore, to solve this problem we only need to find the
total voltage at the load from the incident wave:
Vt (0.333 0.5V ) 0.5V 0.667 V .
11.6) As w did in the previous problem, we begin by using the voltage divider principle to find the
launched voltage and then find the load and generator reflection coefficients.
The launched voltage (Vi) is found to be:
Vi 1V 0.667V .
The reflection coefficient at the load is:
Page 22 of 30
Rl Z o 100 50
l 0.333 .
Rl Z o 100 50
The reflection coefficient at the generator is:
Rg Z o 25 50
Rg Z o 25 50
With these parameters established we are now ready to create a reflection chart similar to Figure
11.7, and we‟ll use that same numbering scheme here to identify the steps.
Step 1: Vi = 0.667V
2: Vne = 0
3: Vr 0.333 0.667 V 0.222 V ; At the load
Vt 0.667 V 0.222 V 0.889 V
4: Vr 0.333 0.222 V 73 .9mV ; At the generator
Vt 0.222V 73 .9mV 184 mV
5: Vr 0.333 73 .9mV 24 .4mV ; At the load
Vt (73 .9mV ) (24 .4mV ) 98 .2mV
6: Vr 0.333 24 .4mV 8.1mV ; At the generator
Vt 24 .4mV 8.1mV 16 .3mV
11.7) Proceeding as in the previous problem, we find that the launched pulse has an amplitude of 0.25V,
and that g and l are both equal to 1.
When the 0.25V incident pulse arrives at the load, the reflected voltage becomes:
Vi l 0.25V 1 0.25V . Assuming the voltage across the load is initially zero, this makes
the total load voltage Vt Vi Vr V p 0.25V 0.25V 0 0.5V .
The +0.25V reflection travels back up the line, toward the generator. When it arrives at the
generator, the reflected voltage becomes Vi g 0.25V 1 0.25V . Because the width of
the launched pulse was much narrower than the length of the line, the voltage at the generator is
zero volts when the reflection arrives. This makes the total generator voltage:
Vt Vi Vr V p 0.25V 0.25V 0 0.5V .
The +0.25V reflection travels back down the line, toward the load. By the time this reflection
arrives the previous reflection has vanished, so the total load voltage is, once again,
Vt Vi Vr V p 0.25V 0.25V 0 0.5V . This process repeats itself when the
reflection arrives at the generator.
Page 23 of 30
Since the line is lossless, the 0.25V pulse travels up and down the line indefinitely, causing 0.5V,
200ps wide pulses to appear every 4ns at each end of the line. In practical systems losses in the
transmission line consume some of the energy from the reflected pulse, making the pulse smaller
on each round trip. Instead of a steady, continuous stream of 0.5V pulses, the response is a series
of progressively smaller pulses that eventually vanish.
Page 24 of 30
Solutions for Chapter 12
12.1) We know that for the best impedance matching the termination resistance should equal the
transmission line impedance. Therefore if we determine the termination resistance these two
resistors represent we will know the optimum value (and, presumably, the expected value) of the
transmission line impedance.
Resistor Rterm is found from equation (12.1):
R1 R2 120 120
Rterm 60 .
R1 R2 120 120
Therefore, the trace impedance is probably close to 60.
12.2) The reflection coefficient (presented in the previous chapter) is a good way to gauge the severity
of the mismatch occurring between the transmission line impedance and Rterm.
We begin by noting that the worst case value for Rterm will occur when R1 and R2 are
simultaneously at the extremes of their values. Therefore, to find the highest value for Rterm we‟ll
set R1 and R2 to (120 + 5%) = 126. The lowest value will occur when R1 and R2 are
simultaneously (120 - 5%) = 114.
Using these values in equation (12.1) in the same way we did in the previous problem, the highest
value of Rterm is found to be 63 and the lowest is 57. In the previous problem we determined
that Zo is probably 60. Assuming that to be true, Chapter 11‟s equation (11.3) is used to find the
Rm ax Z o 63 60
m ax 0.024 , and
Rm ax Z o 63 60
Rm in Z o 57 60
m in 0.026
Rm in Z o 57 60
This degree of mismatch represents a small error and will only be consequential in high
12.3) As we found in the previous problem, here we see that Rterm can take on values between (60
+5%) and (60 -5%), that is, between 63 and 57. Since these are the same values used
previously, we see that max and min are identical to the values found with the two resistor parallel
termination case. This means the impedance of the Thevenin termination has the same sensitivity
to resistor tolerance as the two resistor parallel termination circuit. However, the degree to which
the termination voltage changes is not the same.
12.4) Since the optimum value for Rterm is equal to the characteristic impedance of the coax, the value
for resistor R1 is found from equation (12.3a) to be:
Vdd Rterm 5V 75
R1 375 .
Resistor R2 is found from equation (12.3b) to be:
Page 25 of 30
R1 Vterm 375 1V
R2 93 .8 .
Vdd Vterm 5V 1V
Using stock values for R1 and R2 gives R1 = 360 and R2 = 91. Using equation (12.2) we find
that Vterm is unaffected by this selection:
Vterm Vdd 5V 1V .
R1 R2 360 91
However, equation (12.1) shows that Rterm is slightly less than the optimum value of 75:
R1 R 2 360 91
Rterm 73 . By using the reflection coefficient
R1 R2 360 91
(introduced in the previous chapter), we find that L is -0.014, which shows that this degree of
mismatch is insignificant.
12.5) From equation (12.3a),
Vdd Rterm 5V 130
R1 Vterm 217 3V
Vdd Vterm 5V 3V
Standard values are 220 and 330. These values were commonly used to parallel terminate
bipolar TTL logic and are still available as integrated resistor networks. The 130 termination
impedance is high for modern circuit board traces, but it‟s a good match for wire-wrapped and
hand wired interconnect, and for circuit boards without a nearby ground plane.
12.6) Two resistor parallel termination is shown in the top of Figure 12.3, and that circuit will be
analyzed first. From there we can see that when driver TX holds the bus low, current flows from
Vdd through R1. Since Rds_on is 12, from Ohms law this current is:
I 29 .5mA .
Rtotal 100 12
The driver dissipates P I R 29.5mA 12 10.4mW , and R1
dissipates 29.5mA 100 87mW . The total system power is the sum of these, or 97.4mW.
For the Thevenin equivalent shown at the bottom of the figure, we‟ll set Vterm to
1.65V and Rterm = 50, since this is the Thevenin equivalent of the two
resistor termination circuit we just analyzed.
In this case, the current from the Vterm supply sunk by driver TX is:
Page 26 of 30
I 26 .6mA .
Rtotal 50 12
The driver dissipates 8.5mW and resistor Rterm dissipates 35.4mW. These sum to give the total
system power of 43.9mW.
The power savings of the Thevenin termination is evident. In this example the driver dissipates
about 18% less power and Rterm dissipates about 60% less power than in the two resistor
termination. Additionally, nearly 10% less current is drawn from the Vterm supply than is drawn
from Vdd. This represents a savings of more than 50% in power.
12.7) This is a direct application of equation (12.4):
Cterm 1.4nF .
f Zo 33 10 6 65
12.8) Solving equation (12.4) for frequency f, we have:
f 128 MHz . Because a capacitor‟s
Cterm Z o 470 10 12 50
reactance decreases as frequency increases, frequencies higher than 128MHz are likely to be better
terminated than lower ones. However, the parasitic inductance of the component will ultimately
limit the high-frequency response. For this reason circuit simulation should be used to verify this
estimate and the suitability of the network for a specific application.
12.9) Because the signal rise time is so much smaller than the electrical length of the transmission line,
the load capacitors appear as a discontinuity at the end of the line and do not add to the lines
distributed capacitance. For proper termination the series resistance should match the transmission
line impedance. This makes RS1 50 and RS2 and RS3 each 65.
12.10) If we assume driver TX has the same strength pulling up as it does pulling down, placing Vterm at
the receivers switch point voltage will give the best results. Therefore, Vterm is
12.11) The resistance should match the transmission line impedance, making Rterm1 50, and Rterm2 and
Rterm3 each 65.
12.12) Since the impedance of the trace has changed but not the length, from the text we know that the
12” (30.5cm) transmission line has an unloaded delay of 2.1ns, and has 3.5pF loads placed every 6
From equation (12.8) the loaded capacitance is:
tpd 2 2.1ns 2
Co 52.5 pF ; since the loads are placed every 6”
tpd Z o
2.1ns 2 40 2
Page 27 of 30
(15.2cm) the loaded capacitance is half this, or 26.25pF. Using equation (12.6), we find the loaded
impedance to be:
ZL 37.6 .
CL 3.5 pF
Co 26.25 pF
This is a 6% reduction in the unloaded impedance, and is less than the 9% reduction that occurs
when the trace impedance is 65. This shows that lower impedance trace is less affected by
distributed loads than higher impedance traces.
12.13) From Figure 12.17 we know that good signal quality will not be obtained on this
net with series termination. Therefore, RS should be set to 0. Proper termination will be achieved
by parallel termination using Rterm1 – Rterm3.
The proper value for the resistors is determined by the impedance of transmission lines T4-T5.
Since T3 and T5 are 50 lines, 50 resistors should be used for Rterm3 and Rterm2. To match the
impedance of T4, a 65 resistor should be used for Rterm1.
As described in the text, to prevent reflections, transmission line T1 should have a value equal to
the parallel combination of T2 and T4, which in this case is 28.
As a practical matter, a circuit board fabrication shop probably does not have experience in
deliberately producing traces of this value, so they are unlikely to be willing to guarantee this
impedance in volume production at a reasonable cost. A better solution is to isolate T2 and T4 and
extend T4 directly to the driver in a fashion similar to that shown in Figure 12.9. Alternatively, it
may be more economical to isolate T2 and T4 and drive T4 from a driver separate from T2.
12.14) We know from problem 12.6 that in normal operation the Thevenin termination dissipates less
power than the two resistor scheme shown at the top portion of Figure 12.3. However, in this
problem we are asked to analyze the power savings when the bus is placed in the high-impedance
When none of the drivers are pulling the bus high or low the drivers appear to be disconnected
from the bus and, resistors R1 and R2 in Figure 12.3 appear as simple load resistors connected
from Vdd to ground.
Assuming R1 and R2 are 100, the total power dissipated in Vdd for the terminator pair is:
V 3.3V 2
P dd 54.5mW .
Rtotal 100 100
In contrast, by using a Thevenin termination the power is zero when the drivers
are all placed in the high-impedance state. The total system power should also account for the
small amount of power dissipated in the voltage regulator used to create Vterm, but this simplified
analysis shows that in three-state applications Thevenin termination can use significantly less
power than a two resistor termination scheme.
Page 28 of 30
Solutions for Chapter 13
13.1) We find the termination resistor values with equations (13.4) and (13.5), but to use
these equations we must first find the even and odd mode impedances. Chapter 9 describes
how to do this, and as shown in Exercise problem 9.10 for this pair of traces, Zoo = 49.3
and Zoe = 73.3.
Therefore, from equation (13.4): R1 Z oe 73 .3 , and from (13.5):
2 Z oe Z oo 2 73 .3 49 .3
R2 301 .1
Z oe Z oo 73 .3 49 .3
13.2) From equation (13.1) we know that the differential impedance is twice the odd mode
impedance. Using the techniques described in Chapter 9 we find that in this case
Zoo = 50.0 and Zoe = 63.3.
Therefore, from equation (13.1) Z diff 2 Z oo 2 50 100 .
13.3) As stated, the problem does not contain enough information to confidently answer
this question. As section 13.4 describes, the length matching and driver characteristics
significantly influence if mode conversion will occur, and if so, its severity. The signaling
rate and receiver input characteristics are also important factors. However, limiting our
scope to only considering the diff-pair routing, the relatively large difference between the
even and odd mode impedances suggests that this trace pair may benefit from the three
resistor termination scheme showed in Figure 13.11. A circuit simulation which includes the
differences in trace lengths and all discontinuities (such as vias) is necessary to decide on the
13.4) From Figure 13.10 and section 13.4 we know that for proper termination
the resistor value is made equal to the differential impedance of the diff-pair. In problem
13.2 we found Zdiff to be 100. Therefore, a single 100 resistor placed across the diff-pair
is the proper termination.
13.5) As described in section 13.4, a single resistor from each trace to ground is sometimes used
to terminate a diff-pair. If this technique is chosen, the resistor value is made equal to the
odd model impedance of the diff-pair. From problem 13.2 we know Zoo = 50, so for
proper termination a 50 resistor is placed to ground from each trace.
13.6) As done previously, we first calculate the even and odd mode impedances and then use
equations (13.4) and (13.5) to find the values for R1 and R2.
In this case, the odd mode impedance is calculated to be 50.0 and the even mode
impedance 51.8. This small difference supports the assertion that the diff-pair is loosely coupled. In
fact, the model represents a pair of 4 mil wide microstrips separated by 16 mils.
The resistors are found to be R1 Z oe 51 .8 , and
2 Z oe Z oo 2 51 .8 50 .0
R2 2.9 K
Z oe Z oo 51 .8 50 .0
These resistance values make intuitive sense given that the diff-pair is loosely coupled:
because the even mode impedance is so close to the odd mode impedance we would expect
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this diff-pair to behave as two isolated traces. For this reason R1 should be equal in value to the
transmission line impedance, and R2 should be inconsequential. We see this is so: R1 is
essentially equal to Zo and R2 is so much greater that as a practical matter it can be ignored.
13.7) The bottom portion of Figure 13.11 shoes how to do this. As we showed in Problem
13.1, resistors R1 and R2 are found from the diff-pair even and odd mode impedances. As
we see in the figure, series capacitors prevent DC from the Vtt supply to flow down the diff-
pair back to the oscillator. This allows Vtt to rebias the signal at the receiver without
interference from the transmitter. By making Vtt equal to 1.65V the ASIC receiver will swing 1V
peak to peak and be centered at 1.65V.
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