The Complete Pentium Instruction Set Table (32 Bit Addressing Mode Only) by Sang Cho ********************************************** Explanation of the Notation used in this Table ********************************************** /digit -- A digit between 0 and 7 indicates that the ModR/M byte of the instruction uses only the r/m (register or memory) operand. The reg field contains the digit that provides an extension to the instruction's opcode. /r -- Indicates that the ModR/M byte of the instruction contains both a register operand and an r/m operand. cb -- A relative byte offset from the next instruction for JMP, CALL etc. cw -- A relative word offset from the next instruciton for JMP, CALL etc. cd -- A relative doubleword offset from the next instruction for JMP, CALL etc. cp -- An absolute far pointer for JMP, CALL etc. ib, iw, id -- 1-byte (ib), 2-byte (iw), or 4-byte (id) immediate operand +rb, +rw, +rd -- register code, from 0 through 7, added to an opcode byte. rb rw rd ---------------------AL = 0 AX = 0 EAX = 0 CL = 1 CX = 1 ECX = 1 DL = 2 DX = 2 EDX = 2 BL = 3 BX = 3 EBX = 3 AH = 4 SP = 4 ESP = 4 CH = 5 BP = 5 EBP = 5 DH = 6 SI = 6 ESI = 6 BH = 7 DI = 7 EDI = 7 +i -- A number used in floating-point instructions when one of the operands is ST(i) from the FPU register stack. rel8 -- A relative address in the range from -128 to 127 bytes from the end of the instruction. rel16 and rel32 -- A relative address within the same code segment as the instruction assembled. ptr16:16 and ptr16:32 -- A far pointer, typically in a code segment different from that of the instruction. r8 -- One of the byte general-purpose registers. r16 -- One of the word general-purpose registers. r32 -- One of the doubleword general-purpose registers.
imm8 -- An immediate byte value. imm16 -- An immediate word value. imm32 -- An immediate doubleword value. r/m8 -- A byte general-purpose register, or a byte from memory. r/m16 -- A word general-purpose register, or a word memory operand. r/m32 -- A doubleword general-purpose register, or a doubleword memory operand. m -- A 16- or 32-bit operand in memory. m8 -- A byte operand in memory, pointed to by the DS:(E)SI or ES:(E)DI registers. Used with the string instructions and the XLAT instruction. m16 -- A word operand in memory, pointed to by the DS:(E)SI or ES:(E)DI registers. Used only with the string instructions. m32 -- A doubleword operand in memory, pointed to by the DS:(E)SI or ES:(E)DI registers. Used only with the string instructions. m64 -- A memory quadword operand in memory. Used only with the CMPXCHG8B instruction. m16:16, m16:32 -- A memory operand containing a far pointer composed of two numbers. The number to the left of the colon corresponds to the pointer's segment selector. The number to the right corresponds to its offset. m16&32, m16&16, m32&32 -- A memory operand consisting of data item pairs whose sizes are indicated on the left and the right side of the ampersand. All memory addressing modes are allowed. The m16&16 and m32&32 operands are used by the BOUND instruction to provide an operand containing an upper and lower bounds for array indices. The m16&32 operand is used by LIDT and LGDT to provide a word with which to load the limit field, and a doubleword with which to load the base field of the corresponding GDTR and IDTR registers. moffs8, moffs16, moffs32 -- A simple memory variable (memory offset) of type byte, word, or doubleword used by some variants of the MOV instruction. The actual address is given by a simple offset relative to the segment base. No ModR/M byte is used in the instruction. The number shown with moffs indicates its size, which is determined by the address-size attribute of the instruction. Sreg -- A segment register. The segment register bit assignments are ES=0, CS=1, SS=2, DS=3, FS=4, and GS=5. m32real, m64real, m80real
-- A single-, double-, and extended-real floating-point operand in memory. m16int, m32int, m64int -- A word-, short-, and long-integer floating-point operand in memory. ST or ST(0) -- The top element of the FPU register stack. ST(i) -- The i th element from the top of the FPU register stack. (i = 0 through 7) mm -- An MMX register. The 64-bit MMX registers are: MM0 through MM7. mm/m32 -- The low order 32 bits of an MMX register or a 32-bit memory operand. mm/m64 -- An MMX register or a 64-bit memory operand.
Alphabetical Listing ========================================================================= ====== Opcode,Data Instruction Explanation -----------------------------------------------------------------------------37 AAA ASCII adjust AL after addition D5 0A AAD ASCII adjust AX before division D4 0A AAM ASCII adjust AX after multiplication 3F AAS ASCII adjust AL after subtraction 14 ib ADC AL,imm8 Add with carry 15 id ADC EAX,imm32 Add with carry 80 /2 ib ADC r/m8,imm8 Add with carry 81 /2 id ADC r/m32,imm32 Add with carry 83 /2 ib ADC r/m32,imm8 Add with carry 10 /r ADC r/m8,r8 Add with carry 11 /r ADC r/m32,r32 Add with carry 12 /r ADC r8,r/m8 Add with carry 13 /r ADC r32,r/m32 Add with carry 04 ib ADD AL,imm8 Add 05 id ADD EAX,imm32 Add 80 /0 ib ADD r/m8,imm8 Add 81 /0 id ADD r/m32,imm32 Add 83 /0 ib ADD r/m32,imm8 Add 00 /r ADD r/m8,r8 ADD 01 /r ADD r/m32,r32 ADD 02 /r ADD r8,r/m8 ADD 03 /r ADD r32,r/m32 ADD 24 ib AND AL,imm8 AND 25 id AND EAX,imm32 AND 80 /4 ib AND r/m8,imm8 AND 81 /4 id AND r/m32,imm32 AND 83 /4 ib AND r/m32,imm8 AND 20 /r AND r/m8,r8 AND 21 /r AND r/m32,r32 AND 22 /r AND r8,r/m8 AND
23 /r 63 /r Sel. 62 /r 0F BC /r 0F BD /r 0F C8+rd 0F A3 /r 0F BA /4 ib 0F BB /r 0F BA /7 ib 0F B3 /r 0F BA /6 ib 0F AB /r 0F BA /5 ib E8 cd FF /2 r/m32 9A cp FF /3 m16:32 98 99 99 F8 FC FA 0F 06 Reg. Zero F5 0F 47 /r 0F 43 /r 0F 42 /r 0F 46 /r 0F 42 /r 0F 44 /r 0F 4F /r 0F 4D /r 0F 4C /r 0F 4E /r 0F 46 /r 0F 42 /r 0F 43 /r 0F 47 /r 0F 43 /r 0F 45 /r 0F 4E /r 0F 4C /r 0F 4D /r 0F 4F /r 0F 41 /r 0F 4B /r 0F 49 /r 0F 45 /r
AND r32,r/m32 ARPL r/m16,r16 BOUND r32,m32&32 BSF r32,r/m32 BSR r32,r/m32 BSWAP r32 BT r/m32,r32 BT r/m32,imm8 BTC r/m32,r32 BTC r/m32,imm8 BTR r/m32,r32 BTR r/m32,imm8 BTS r/m32,r32 BTS r/m32,imm8 CALL rel32 CALL r/m32 CALL ptr16:32 CALL m16:32 CBW CWD CDQ CLC CLD CLI CLTS CMC CMOVA r32,r/m32 CMOVAE r32,r/m32 CMOVB r32,r/m32 CMOVBE r32,r/m32 CMOVC r32,r/m32 CMOVE r32,r/m32 CMOVG r32,r/m32 CMOVGE r32,r/m32 CMOVL r32,r/m32 CMOVLE r32,r/m32 CMOVNA r32,r/m32 CMOVNAE r32,r/m32 CMOVNB r32,r/m32 CMOVNBE r32,r/m32 CMOVNC r32,r/m32 CMOVNE r32,r/m32 CMOVNG r32,r/m32 CMOVNGE r32,r/m32 CMOVNL r32,r/m32 CMOVNLE r32,r/m32 CMOVNO r32,r/m32 CMOVNP r32,r/m32 CMOVNS r32,r/m32 CMOVNZ r32,r/m32
AND Adjust Request Privilege Level of Check Array Index Against Bounds Bit scan forward on r/m32 Bit scan reverse on r/m32 Reverses the byte order of a r32 Bit Test Bit Test Bit Test and Complement Bit Test and Complement Bit Test and Clear Bit Test and Clear Bit Test and Set Bit Test and Set Call near, rel to n.inst Call near, abs.ind.add. given in Call far, abs.add. given in operand Call far, abs.ind.add. given in Convert Byte to Word Convert Word to Doubleword Convert Doubleword to Quadword Clear CF flag Clear DF flag Clear interrupt flag Clear Task-Switched Flag in Control Complement CF flag Move if above Move if above or equal Move if below Move if below or equal Move if carry Move if equal Move if greater Move if greater or equal Move if less Move if less or equal Move if not above Move if not above or equal Move if not below Move if not below or equal Move if not carry Move if not equal Move if not greater Move if not greater or equal Move if not less Move if not less or equal Move if not overflow Move if not parity Move if not sign Move if not zero
0F 40 /r 0F 4A /r 0F 4A /r 0F 4B /r 0F 48 /r 0F 44 /r 3C ib 3D id 80 /7 ib 81 /7 id 83 /7 ib 38 /r 39 /r 3A /r 3B /r A6 ES:(E)DI A7 ES:(E)DI 0F B0 /r 0F B1 /r 0F C7 /1 m64 0F A2 27 2F FE /1 FF /1 48+rd F6 /6 F7 /6 F7 /6 0F 77 C8 iw 00 C8 iw 01 proc. C8 iw ib proc. D9 F0 D9 E1 value D8 /0 ST(0) DC /0 ST(0) D8 C0+i DC C0+i DE C0+i r.stack DE C1 r.stack DA /0 DE /0 DF /4 DF /6
CMOVO r32,r/m32 CMOVP r32,r/m32 CMOVPE r32,r/m32 CMOVPO r32,r/m32 CMOVS r32,r/m32 CMOVZ r32,r/m32 CMP AL,imm8 CMP EAX,imm32 CMP r/m8,imm8 CMP r/m32,imm32 CMP r/m32,imm8 CMP r/m8,r8 CMP r/m32,r32 CMP r8,r/m8 CMP r32,r/m32 CMPSB CMPSD CMPXCHG r/m8,r8 CMPXCHG r/m32,r32 CMPXCHG8B m64 CPUID DAA DAS DEC r/m8 DEC r/m32 DEC r32 DIV r/m8 DIV r/m16 DIV r/m32 EMMS ENTER imm16,0 ENTER imm16,1 ENTER imm16,imm8 F2XM1 FABS FADD m32real FADD m64real FADD ST(0),ST(i) FADD ST(i),ST(0) FADDP ST(i),ST(0) FADDP FIADD m32int FIADD m16int FBLD m80bcd FBSTP m80bcd
Move if Move if Move if Move if Move if Move if Compare Compare Compare Compare Compare Compare Compare Compare Compare Compare
overflow parity parity even parity odd sign zero
byte at DS:(E)SI with at DS:(E)SI with
Compare dw
Compare and Exchange Compare and Exchange Compare and Exchange EAX := Processor id.info. Decimal adjust AL after addition Decimal adjust AL after subtraction Decrement r/m8 by 1 Decrement r/m32 by 1 Decrement r32 by 1 Unsigned divide AX by r/m8 Unsigned divide DX:AX by r/m16 Unsigned divide EDX:EAX by r/m32 Set the FP tag word to empty Create a stack frame for a procedure Create a nested stack frame for a Create a nested stack frame for a Replace ST(0) with 2**ST(0) - 1 Replace ST(0) with its absolute Add m32real to ST(0) and s.r. in Add m64real to ST(0) and s.r.in Add ST(0) to ST(i) and s.r.in ST(0) Add ST(i) to ST(0) and s.r. in ST(i) Add ST(0) to ST(i), s.r.in ST(i),pop Add ST(0) to ST(1), s.r.in ST(1),pop Add m32int to ST(0) and s.r.in ST(0) Add m16int to ST(0) and s.r.in ST(0) Convert m80BCD to real and push Store ST(0) in m80bcd and pop ST(0)
D9 E0 9B DB E2 DB E2 DA C0+i DA C8+i DA D0+i DA D8+i DB C0+i DB C8+i DB D0+i DB D8+i D8 /2 DC /2 D8 D0+i D8 D1 D8 /3 r.stack. DC /3 r.stack. D8 D8+i D8 D9 DE D9 DB F0+i flags DF F0+i ,pop DB E8+i o.v.set s.f. DF E8+i ovssf pop D9 FF D9 F6 word. D8 /6 ST(0) DC /6 ST(0) D8 F0+i ST(0) DC F8+i ST(i) DE F8+i pop DE F9 pop DA /6 ST(0) DE /6 ST(0) D8 /7 ST(0) DC /7 ST(0)
FCHS FCLEX FNCLEX FCMOVB ST(0),ST(i) FCMOVE ST(0),ST(i) FCMOVBE ST(0),ST(i) FCMOVU ST(0),ST(i) FCMOVNB ST(0),ST(i) FCMOVNE ST(0),ST(i) FCMOVNBE ST(0),ST(i) FCMOVNU ST(0),ST(i) FCOM m32real FCOM m64real FCOM ST(i) FCOM FCOMP m32real FCOMP m64real FCOMP ST(i) FCOMP FCOMPP FCOMI ST,ST(i) FCOMIP ST,ST(i) FUCOMI ST,ST(i) FUCOMIP ST,ST(i) FCOS FDECSTP FDIV m32real FDIV m64real FDIV ST(0),ST(i) FDIV ST(i),ST(0) FDIVP ST(i),ST(0) FDIVP FIDIV m32int FIDIV m16int FDIVR m32real FDIVR m64real
Complements sign of ST(0) Clear f.e.f. after checking for .. Clear f.e.f. without checking for .. Move if below Move if equal Move if below or equal Move if unordered Move if not below Move if not equal Move if not below or equal Move if not unordered Compare ST(0) with m32real. Compare ST(0) with m64real. Compare ST(0) with ST(i). Compare ST(0) with ST(1). Compare ST(0) with m32real,pop Compare ST(0) with m64real,pop Compare Compare Compare Compare ST(0) ST(0) ST(0) ST(0) with with with with ST(i), ST(1), ST(1), ST(i), pop pop pop pop set status
Compare ST(0) with ST(i), set s.f. Compare ST(0) with ST(i), check Compare ST(0) with ST(i), check Replace ST(0) with its cosine Decrement TOP field in FPU status Divide ST(0) by m32real and s.r.in Divide ST(0) by m64real and s.r.in Divide ST(0) by ST(i) and s.r.in Divide ST(i) by ST(0) and s.r.in Divide ST(i) by ST(0), s.r.in ST(i) Divide ST(1) by ST(0), s.r.in ST(1) Divide ST(0) by m32int and s.r.in Divide ST(0) by m64int and s.r.in Divide m32real by ST(0) and s.r.in Divide m64real by ST(0) and s.r.in
D8 F8+i ST(0) DC F0+i ST(i) DE F0+i pop DE F1 pop DA /7 ST(0) DE /7 ST(0) DD C0+i DE /2 DA /2 DE /3 DA /3 DF /0 DB /0 DF /5 D9 F7 r. 9B DB E3 DB E3 DF /2 DB /2 DF /3 DB /3 DF /7 D9 /0 DD /0 DB /5 D9 C0+i D9 E8 D9 E9 D9 EA D9 EB D9 EC D9 ED D9 EE D9 /5 D9 /4 D8 /1 ST(0) DC /1 ST(0) D8 C8+i ST(0) DC C8+i ST(i) DE C8+i ST(i) pop DE C9 ST(1) pop
FDIVR ST(0),ST(i) FDIVR ST(i),ST(0) FDIVRP ST(i),ST(0) FDIVRP FIDIVR m32int FIDIVR m16int FFREE ST(i) FICOM m16int FICOM m32int FICOMP m16int FICOMP m32int FILD m16int FILD m32int FILD m64int FINCSTP FINIT FNINIT FIST m16int FIST m32int FISTP m16int FISTP m32int FISTP m64int FLD m32real FLD m64real FLD m80real FLD ST(i) FLD1 FLDL2T FLDL2E FLDPI FLDLG2 FLDLN2 FLDZ FLDCW m2byte FLDENV m14/28byte FMUL m32real FMUL m64real FMUL ST(0),ST(i) FMUL ST(i),ST(0) FMULP ST(i),ST(0) FMULP
Divide ST(i) by ST(0) and s.r.in Divide ST(0) by ST(i) and s.r.in Divide ST(0) by ST(i), s.r.in ST(i) Divide ST(0) by ST(1), s.r.in ST(1) Divide m32int by ST(0) and s.r.in Divide m64int by ST(0) and s.r.in Sets tag for ST(i) to empty Compare ST(0) with m16int Compare ST(0) with m32int Compare ST(0) with m16int and pop Compare ST(0) with m32int and pop Push m16int Push m32int Push m64int Increment the TOP field FPU status Initialize FPU after ... Initialize FPU without ... Store ST(0) in m16int Store ST(0) in m32int Store ST(0) in m16int and pop Store ST(0) in m32int and pop Store ST(0) in m64int and pop Push m32real Push m64real Push m80real Push ST(i) Push +1.0 Push log2 10 Push log2 e Push pi Push log10 2 Push loge 2 Push +0.0 Load FPU control word from m2byte Load FPU environment from m14/m28 Multiply ST(0) by m32real and s.r.in Multiply ST(0) by m64real and s.r.in Multiply ST(0) by ST(i) and s.r.in Multiply ST(i) by ST(0) and s.r.in Multiply ST(i) by ST(0), s.r.in Multiply ST(1) by ST(0), s.r.in
DA /1 FIMUL m32int ST(0) DE /1 FIMUL m16int ST(0) D9 D0 FNOP D9 F3 FPATAN arctan(ST(1)/ST(0)) pop D9 F8 FPREM (ST(0)/ST(1)) D9 F5 FPREM1 rem(ST(0)/ST(1)) D9 F2 FPTAN 1.0 D9 FC FRNDINT DD /4 FRSTOR m94/108byte byte 9B DD /6 FSAVE m94/108byte DD /6 FNSAVE m94/108byte D9 FD FSCALE D9 FE FSIN D9 FB FSINCOS push c D9 FA FSQRT D9 /2 FST m32real DD /2 FST m64real DD D0+i FST ST(i) D9 /3 FSTP m32real DD /3 FSTP m64real DB /7 FSTP m80real DD D8+i FSTP ST(i) 9B D9 /7 FSTCW m2byte D9 /7 FNSTCW m2byte 9B D9 /6 FSTENV m14/28byte D9 /6 FNSTENV m14/28byte 9B DD /7 FSTSW m2byte after 9B DF E0 FSTSW AX DD /7 FNSTSW m2byte without DF E0 FNSTSW AX D8 /4 FSUB m32real ST(0) DC /4 FSUB m64real ST(0) D8 E0+i FSUB ST(0),ST(i) ST(0) DC E8+i FSUB ST(i),ST(0) ST(i) DE E8+i FSUBP ST(i),ST(0) pop DE E9 FSUBP pop DA /4 FISUB m32int ST(0)
Multiply ST(0) by m32int and s.r.in Multiply ST(0) by m16int and s.r.in No operation is performed Repalces ST(1) with Replaces ST(0) with rem Replaces ST(0) with IEEE Replaces ST(0) with its tangent push Round ST(0) to an integer Load FPU status from m94 or m108 Store FPU status to m94 or m108 Store FPU environment to m94 or m108 Scale ST(0) by ST(1) Replace ST(0) with its sine Compute sine and consine of ST(0) s square root of ST(0) Copy ST(0) to m32real Copy ST(0) to m64real Copy ST(0) to ST(i) Copy ST(0) to m32real and pop Copy ST(0) to m64real and pop Copy ST(0) to m80real and pop Copy ST(0) to ST(i) and pop Store FPU control word Store FPU control word without Store FPU environment Store FPU env without Store FPU status word at m2byte Store FPU status word in AX after Store FPU status word at m2byte Store FPU status word in AX without Sub m32real from ST(0) and s.r.in Sub m64real from ST(0) and s.r.in Sub ST(i) from ST(0) and s.r.in Sub ST(0) from ST(i) and s.r.in Sub ST(0) from ST(i), s.r.in ST(i) Sub ST(0) from ST(1), s.r.in ST(1) Sub m32int from ST(0) and s.r.in
DE /4 FISUB m16int ST(0) D8 /5 FSUBR m32real ST(0) DC /5 FSUBR m64real ST(0) D8 E8+i FSUBR ST(0),ST(i) ST(0) DC E0+i FSUBR ST(i),ST(0) ST(i) DE E0+i FSUBRP ST(i),ST(0) pop DE E1 FSUBRP pop DA /5 FISUBR m32int ST(0) DE /5 FISUBR m16int ST(0) D9 E4 FTST DD E0+i FUCOM ST(i) DD E1 FUCOM DD E8+i FUCOMP ST(i) DD E9 FUCOMP DA E9 FUCOMPP D9 E5 FXAM D9 C8+i FXCH ST(i) D9 C9 FXCH D9 F4 FXTRACT sig. D9 F1 FYL2X and pop D9 F9 FYL2XP1 ST(1)*log2(ST(0)+1) pop F4 HLT F6 /7 IDIV r/m8 F7 /7 IDIV r/m32 F6 /5 IMUL r/m8 F7 /5 IMUL r/m32 0F AF /r IMUL r32,r/m32 6B /r ib IMUL r32,r/m32,imm8 6B /r ib IMUL r32,imm8 69 /r id IMUL r32,r/m32,imm32 69 /r id IMUL r32,imm32 E4 ib IN AL,imm8 address into AL E5 ib IN EAX,imm8 address into EAX EC IN AL,DX AL ED IN EAX,DX into EAX FE /0 INC r/m8 FF /0 INC r/m32 40+rd INC r32
Sub m16int from ST(0) and s.r.in Sub ST(0) from m32real and s.r.in Sub ST(0) from m64real and s.r.in Sub ST(0) from ST(i) and s.r.in Sub ST(i) from ST(0) and s.r.in Sub ST(i) from ST(0), s.r. in ST(i) Sub ST(1) from ST(0), s.r.in ST(1) Sub ST(0) from m32int and s.r.in Sub ST(0) from m16int and s.r.in Compare ST(0) with 0.0 Compare ST(0) with ST(i) Compare ST(0) with ST(1) Compare ST(0) with ST(i) and pop Compare ST(0) with ST(1) and pop Compare ST(0) with ST(1) and pop pop Classify value or number in ST(0) Exchange ST(0) and ST(i) Exchange ST(0) and ST(1) Seperate value in ST(0) exp. and Replace ST(1) with ST(1)*log2ST(0) Replace ST(1) with Halt Divide Divide Multiply Multiply Multiply Multiply Multiply Multiply Multiply Input byte from imm8 I/O port Input byte from imm8 I/O port Input byte from I/O port in DX into Input doubleword from I/O port in DX Increment 1 Increment 1 Increment register by 1
6C ES:(E)DI 6D CC CD CE 0F 08 0F 01 /7 CF 77 73 76 72 E3 74 7F 7D 7C 7E 75 71 79 70 7A 7B 78 0F 87 0F 83 0F 82 0F 86 0F 84 0F 8F 0F 8D 0F 8C 0F 8E 0F 85 0F 81 0F 89 0F 80 0F 8A 0F 8B 0F 88 EB E9 FF /4 EA FF /r 9F 0F 02 /r C5 /r 8D /r C9 C4 /r 0F B4 /r
INS m8 INS m32 INT 3 INT imm8 INTO INVD INVLPG m IRETD JA rel8 JAE rel8 JBE rel8 JC rel8 JECXZ rel8 JE rel8 JG rel8 JGE rel8 JL rel8 JLE rel8 JNE rel8 JNO rel8 JNS rel8 JO rel8 JPE rel8 JPO rel8 JS rel8 JA rel32 JAE rel32 JB rel32 JBE rel32 JE rel32 JG rel32 JGE rel32 JL rel32 JLE rel32 JNE rel32 JNO rel32 JNS rel32 JO rel32 JPE rel32 JPO rel32 JS rel32 JMP rel8 JMP rel32 JMP r/m32 JMP ptr16:32 JMP m16:32 LAHF LAR r32,r/m32 LDS r32,m16:32 LEA r32,m LEAVE LES r32,m16:32 LFS r32,m16:32
Input byte from I/O(DX) into Input dw from I/O(DX) into ES:(E)DI Interrupt 3--trap to debugger Interrupt vector number (imm8) Interrupt 4--if overflow flag is 1 Flush internal caches Invalidate TLB Entry for page (m) Interrupt return(32) Jump short if above Jump short if above or equal Jump short if below or equal Jump short if carry Jump short if ECX register is 0 Jump short if equal Jump short if greater Jump short if greater or equal Jump short if less Jump short if less or equal Jump short if not equal Jump short if not overflow Jump short if not sign Jump short if overflow Jump short if parity even Jump short if parity odd Jump short if sign Jump near if above Jump near if above or equal Jump near if below Jump near if below or equal Jump near if equal Jump near if greater Jump near if greater or equal Jump near if less Jump near if less or equal Jump near if not equal Jump near if not overflow Jump near if not sign Jump near if overflow Jump near if parity even Jump near if parity odd Jump near if sign Jump short, relative, Jump near, relative, Jump near, abs.ind.in r/m32 Jump far, abs.add given in operand Jump far, abs.ind.in m16:32 Load Status Flags into AH Load Access Rights Byte Load DS:r32 with far ptr Load effective address Set ESP to EBP, then pop EBP Load ES:r32 with far ptr Load FS:r32 with far ptr
ib
cb cb cb cb cb cb cb cb cb cb cb cb cb cb cb cb cb cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cb cd cp
0F B5 0F 01 0F 01 0F 00 LDTR 0F 01 CR0 F0 AC AL AD EAX E2 E1 E1 E0 E0 0F 03 0F 03 0F B2 0F 00 88 89 8A 8B 8C 8E A0 A1 A1 A2 A3 A3 B0+rb B8+rd C6 C7 0F 22 0F 22 0F 22 0F 22 0F 20 0F 20 0F 20 0F 20 0F 21 0F 23 0F 6E 0F 7E 0F 6F 0F 7F A4 A5
/r /2 /3 /2 /6
LGS r32,m16:32 LGDT m16&32 LIDT m16&32 LLDT r/m16 LMSW r/m16 LOCK LODS m8 LODS m32 cb cb cb cb cb LOOP rel8 LOOPE rel8 LOOPZ rel8 LOOPNE rel8 LOOPNZ rel8 LSL r16,r/m16 LSL r32,r/m32 LSS r32,m16:32 LTR r/m16 MOV r/m8,r8 MOV r/m32,r32 MOV r8,r/m8 MOV r32,r/m32 MOV r/m16,Sreg** MOV Sreg,r/m16** MOV AL, moffs8* MOV AX, moffs16* MOV EAX, moffs32* MOV moffs8*,AL MOV moffs16*,AX MOV moffs32*,EAX MOV r8,imm8 MOV r32,imm32 MOV r/m8,imm8 MOV r/m32,imm32 MOV CR0, r32 MOV CR2, r32 MOV CR3, r32 MOV CR4, r32 MOV r32,CR0 MOV r32,CR2 MOV r32,CR3 MOV r32,CR4 MOV r32,DR0-DR7 MOV DR0-DR7,r32 MOVD mm,r/m32 MOVD r/m32,mm MOVQ mm,mm/m64 MOVQ mm/m64,mm MOVS m8,m8 MOVS m32,m32
Load Load Load Load
GS:r32 with far ptr m into GDTR m into IDTR segment selector r/m16 into
Load r/m16 in machine status word of Asserts LOCK signal for duration .. Load byte at address DS:(E)SI into Load dword at address DS:(E)SI into Dec count;jump if count # 0 Dec count;jump if count # 0 and ZF=1 Dec count;jump if count # 0 and ZF=1 Dec count;jump if count # 0 and ZF=0 Dec count;jump if count # 0 and ZF=0 Load Segment Limit Load Segment Limit Load SS:r32 with far ptr Load Task Register Move Move Move Move Move segment register to r/m16 Move r/m16 to segment register Move byte at ( seg:offset) to AL Move word at ( seg:offset) to AX Move dword at ( seg:offset) to EAX Move AL to ( seg:offset) Move AX to ( seg:offset) Move EAX to ( seg:offset) Move imm8 to r8 Move imm32 to r32 Move imm8 to r/m8 Move imm32 to r/m32 Move r32 to CR0 Move r32 to CR2 Move r32 to CR3 Move r32 to CR4 Move CR0 to r32 Move CR2 to r32 Move CR3 to r32 Move CR4 to r32 Move debug register to r32 Move r32 to debug register Move doubleword from r/m32 to mm Move doubleword from mm to r/m32 Move quadword from mm/m64 to mm Move quadword from mm to mm/m64 Move byte at DS:(E)SI to ES:(E)DI Move dword at DS:(E)SI to ES:(E)DI
/r /r /r /3 /r /r /r /r /r /r
/0 ib /0 id /r /r /r /r /r /r /r /r /r /r /r /r /r /r
0F BE /r extension 0F BF /r extension 0F B6 /r extension 0F B7 /r extension F6 /4 F7 /4 F6 /3 F7 /3 90 F6 /2 F7 /2 0C ib 0D id 80 /1 ib 81 /1 id 83 /1 ib 08 /r 09 /r 0A /r 0B /r E6 ib E7 ib EE EF 6E 6F (DX) 0F 63 /r 0F 6B /r 0F 67 /r 0F FC /r 0F FD /r 0F FE /r 0F EC /r 0F ED /r 0F DC /r 0F DD /r 0F DB /r 0F DF /r 0F 74 /r 0F 75 /r 0F 76 /r 0F 64 /r 0F 65 /r 0F 66 /r 0F F5 /r 0F E5 /r 0F D5 /r 8F /0 58+rd
MOVSX r32,r/m8 MOVSX r32,r/m16 MOVZX r32,r/m8 MOVZX r32,r/m16 MUL r/m8 MUL r/m32 NEG r/m8 NEG r/m32 NOP NOT r/m8 NOT r/m32 OR AL,imm8 OR EAX,imm32 OR r/m8,imm8 OR r/m32,imm32 OR r/m32,imm8 OR r/m8,r8 OR r/m32,r32 OR r8,r/m8 OR r32,r/m32 OUT imm8,AL OUT imm8,EAX OUT DX,AL OUT DX,EAX OUTS DX,m8 OUTS DX,m32 PACKSSWB mm,mm/m64 PACKSSDW mm,mm/m64 PACKUSWB mm,mm/m64 PADDB mm,mm/m64 PADDW mm,mm/m64 PADDD mm,mm/m64 PADDSB mm,mm/m64 PADDSW mm,mm/m64 PADDUSB mm,mm/m64 PADDUSW mm,mm/m64 PAND mm,mm/m64 PANDN mm,mm/m64 PCMPEQB mm,mm/m64 PCMPEQW mm,mm/m64 PCMPEQD mm,mm/m64 PCMPGTB mm,mm/m64 PCMPGTW mm,mm/m64 PCMPGTD mm,mm/m64 PMADDWD mm,mm/m64 PMULHW mm,mm/m64 PMULLW mm,mm/m64 POP m32 POP r32
Move byte to doubleword, signMove word to doubleword, signMove byte to doubleword, zeroMove word to doubleword, zeroUnsigned multiply Unsigned multiply Two's complement negate r/m8 Two's complement negate r/m32 No operation Reverse each bit of r/m8 Reverse each bit of r/m32 OR OR OR OR OR OR OR OR OR Output byte in AL to I/O(imm8) Output dword in EAX to I/O(imm8) Output byte in AL to I/O(DX) Output dword in EAX to I/O(DX) Output byte from DS:(E)SI to I/O(DX) Output dword from DS:(E)SI to I/O Pack with Signed Saturation Pack with Signed Saturation Pack with Unsigned Saturation Add packed bytes Add packed words Add packed dwords Add signed packed bytes Add signed packed words Add unsigned pkd bytes Add unsigned pkd words AND quadword from .. to .. And qword from .. to NOT qw in mm Packed Compare for Equal Packed Compare for Equal Packed Compare for Equal Packed Compare for GT Packed Compare for GT Packed Compare for GT Packed Multiply and Add Packed Multiply High Packed Multiply Low Pop m32 Pop r32
1F 07 17 0F A1 0F A9 61 9D 0F EB 0F F1 0F 71 0F F2 0F 72 0F F3 0F 73 0F E1 0F 71 0F E2 0F 72 0F D1 0F 71 0F D2 0F 72 0F D3 0F 73 0F F8 0F F9 0F FA 0F E8 0F E9 0F D8 0F D9 0F 68 0F 69 0F 6A 0F 60 0F 61 0F 62 FF 50+rd 6A 68 0E 16 1E 06 0F A0 0F A8 60 9C 0F EF D0 D2 C0 D1
/r /r /6 /r /6 /r /6 /r /4 /r /4 /r /2 /r /2 /r /2 /r /r /r /r /r /r /r /r /r /r /r /r /r /6
ib ib ib ib ib ib ib ib
ib id
/r /2 /2 /2 ib /2
POP DS POP ES POP SS POP FS POP GS POPAD POPFD POR mm,mm/m64 PSLLW mm,mm/m64 PSLLW mm,imm8 PSLLD mm,mm/m64 PSLLD mm,imm8 PSLLQ mm,mm/m64 PSLLQ mm,imm8 PSRAW mm,mm/m64 PSRAW mm,imm8 PSRAD mm,mm/m64 PSRAD mm,imm8 PSRLW mm,mm/m64 PSRLW mm,imm8 PSRLD mm,mm/m64 PSRLD mm,imm8 PSRLQ mm,mm/m64 PSRLQ mm,imm8 PSUBB mm,mm/m64 PSUBW mm,mm/m64 PSUBD mm,mm/m64 PSUBSB mm,mm/m64 PSUBSW mm,mm/m64 PSUBUSB mm,mm/m64 PSUBUSW mm,mm/m64 PUNPCKHBW mm,mm/m64 PUNPCKHWD mm,mm/m64 PUNPCKHDQ mm,mm/m64 PUNPCKLBW mm,mm/m32 PUNPCKLWD mm,mm/m32 PUNPCKLDQ mm,mm/m32 PUSH r/m32 PUSH r32 PUSH imm8 PUSH imm32 PUSH CS PUSH SS PUSH DS PUSH ES PUSH FS PUSH GS PUSHAD PUSHFD PXOR mm,mm/m64 RCL r/m8,1 RCL r/m8,CL RCL r/m8,imm8 RCL r/m32,1
Pop DS Pop ES Pop SS Pop FS Pop GS Pop EDI,... and EAX Pop Stack into EFLAGS Register OR qword from .. to mm Packed Shift Left Logical Packed Shift Left Logical Packed Shift Left Logical Packed Shift Left Logical Packed Shift Left Logical Packed Shift Left Logical Packed Shift Right Arithmetic Packed Shift Right Arithmetic Packed Shift Right Arithmetic Packed Shift Right Arithmetic Packed Shift Right Logical Packed Shift Right Logical Packed Shift Right Logical Packed Shift Right Logical Packed Shift Right Logical Packed Shift Right Logical Packed Subtract Packed Subtract Packed Subtract Packed Subtract with Saturation Packed Subtract with Saturation Packed Subtract Unsigned with S. Packed Subtract Unsigned with S. Unpack High Packed Data Unpack High Packed Data Unpack High Packed Data Unpack Low Packed Data Unpack Low Packed Data Unpack Low Packed Data Push r/m32 Push r32 Push imm8 Push imm32 Push CS Push SS Push DS Push ES Push FS Push GS Push All g-regs Push EFLAGS XOR qword Rotate 9 bits left once Rotate 9 bits left CL times Rotate 9 bits left imm8 times Rotate 33 bits left once
D3 /2 C1 /2 ib D0 /3 D2 /3 C0 /3 ib D1 /3 D3 /3 C1 /3 ib D0 /0 D2 /0 C0 /0 ib D1 /0 D3 /0 C1 /0 ib D0 /1 D2 /1 C0 /1 ib D1 /1 D3 /1 C1 /1 ib times 0F 32 0F 33 0F 31 F3 6C ES:[(E)DI] F3 6D ES:[(E)DI] F3 A4 ES:[(E)DI] F3 A5 ES:[(E)DI] F3 6E port DX F3 6F port DX F3 AC F3 AD EAX F3 AA F3 AB EAX F3 A6 F3 A7 F3 AE F3 AF F2 A6 F2 A7 F2 AE F2 AF C3 CB C2 iw stack
RCL RCL RCR RCR RCR RCR RCR RCR ROL ROL ROL ROL ROL ROL ROR ROR ROR ROR ROR ROR
r/m32,CL r/m32,imm8 r/m8,1 r/m8,CL r/m8,imm8 r/m32,1 r/m32,CL r/m32,imm8 r/m8,1 r/m8,CL r/m8,imm8 r/m32,1 r/m32,CL r/m32,imm8 r/m8,1 r/m8,CL r/m8,imm8 r/m32,1 r/m32,CL r/m32,imm8
Rotate Rotate Rotate Rotate Rotate Rotate Rotate Rotate Rotate Rotate Rotate Rotate Rotate Rotate Rotate Rotate Rotate Rotate Rotate Rotate
33 bits left CL times 33 bits left imm8 times 9 bits right once 9 bits right CL times 9 bits right imm8 times 33 bits right once 33 bits right CL times 33 bits right imm8 times 8 bits r/m8 left once 8 bits r/m8 left CL times 8 bits r/m8 left imm8 times 32 bits r/m32 left once 32 bits r/m32 left CL times 32 bits r/m32 left imm8 times 8 bits r/m8 right once 8 bits r/m8 right CL times 8 bits r/m16 right imm8 times 32 bits r/m32 right once 32 bits r/m32 right CL times 32 bits r/m32 right imm8
RDMSR RDPMC RDTSC REP INS m8,DX REP INS m32,DX REP MOVS m8,m8 REP MOVS m32,m32 REP OUTS DX,m8 REP OUTS DX,m32 REP LODS AL REP LODS EAX REP STOS m8 REP STOS m32 REPE CMPS m8,m8 REPE CMPS m32,m32 REPE SCAS m8 REPE SCAS m32 REPNE CMPS m8,m8 REPNE CMPS m32,m32 REPNE SCAS m8 REPNE SCAS m32 RET RET RET imm16
Read from Model Specific Register Read Performance-Monitoring counters Read Time-Stamp Counter Input ECX bytes from port DX into Input ECX dwords from port DX into Move ECX bytes from DS:[(E)SI] to Move ECX dwords from DS:[(E)SI] to Output ECX bytes from DS:[(E)SI] to Output ECX dwords from DS:[(E)SI] to Load ECX bytes from DS:[(E)SI] to AL Load ECX dwords from DS:[(E)SI] to Fill ECX bytes at ES:[(E)DI] with AL Fill ECX dwords at ES:[(E)DI] with Find nonmatching bytes in m and m Find nonmatching dwords in m and m Find non-AL byte starting at Find non-EAX dword starting at Find matching bytes in m and m Find matching dwords in m and m Find AL, starting at ES:[(E)DI] Find EAX, starting at ES:[(E)DI] Near return Far return Near return, pop imm16 bytes from
CA stack 0F AA 9E D0 D2 C0 D1 D3 C1 D0 D2 C0 D1 D3 C1 D0 D2 C0 D1 D3 C1 D0 D2 C0 D1 D3 C1 1C 1D 80 81 83 18 19 1A 1B AE AF 0F 97 0F 93 0F 92 0F 96 0F 94 0F 9F 0F 9D 0F 9C 0F 9E 0F 95 0F 91 0F 99 0F 90 0F 9A 0F 9B
iw
RET imm16 RSM SAHF SAL r/m8,1 SAL r/m8,CL SAL r/m8,imm8 SAL r/m32,1 SAL r/m32,CL SAL r/m32,imm8 SAR r/m8,1 SAR r/m8,CL SAR r/m8,imm8 SAR r/m32,1 SAR r/m32,CL SAR r/m32,imm8 SHL r/m8,1 SHL r/m8,CL SHL r/m8,imm8 SHL r/m32,1 SHL r/m32,CL SHL r/m32,imm8 SHR r/m8,1 SHR r/m8,CL SHR r/m8,imm8 SHR r/m32,1 SHR r/m32,CL SHR r/m32,imm8 SBB AL,imm8 SBB EAX,imm32 SBB r/m8,imm8 SBB r/m32,imm32 SBB r/m32,imm8 SBB r/m8,r8 SBB r/m32,r32 SBB r8,r/m8 SBB r32,r/m32 SCAS m8 SCAS m32 SETA r/m8 SETAE r/m8 SETB r/m8 SETBE r/m8 SETE r/m8 SETG r/m8 SETGE r/m8 SETL r/m8 SETLE r/m8 SETNE r/m8 SETNO r/m8 SETNS r/m8 SETO r/m8 SETPE r/m8 SETPO r/m8
Far return, pop imm16 bytes from Resume from System Management Store AH into Flags Shift Arithmetic Left Shift Arithmetic Left Shift Arithmetic Left Shift Arithmetic Left Shift Arithmetic Left Shift Arithmetic Left Shift Arithmetic Right Shift Arithmetic Right Shift Arithmetic Right Shift Arithmetic Right Shift Arithmetic Right Shift Arithmetic Right Shift Logical Left Shift Logical Left Shift Logical Left Shift Logical Left Shift Logical Left Shift Logical Left Shift Logical Right Shift Logical Right Shift Logical Right Shift Logical Right Shift Logical Right Shift Logical Right Subtract with borrow Subtract with borrow Subtract with borrow Subtract with borrow Subtract with borrow Subtract with borrow Subtract with borrow Subtract with borrow Subtract with borrow Scan String Scan String Set byte if above Set byte if above or equal Set byte if below Set byte if below or equal Set byte if equal Set byte if greater Set byte if greater or equal Set byte if less Set byte if less or equal Set byte if not equal Set byte if not overflow Set byte if not sign Set byte if overflow Set byte if parity even Set byte if parity odd
/4 /4 /4 /4 /4 /4 /7 /7 /7 /7 /7 /7 /4 /4 /4 /4 /4 /4 /5 /5 /5 /5 /5 /5
ib ib ib ib ib ib ib
ib ib id /3 ib /3 id /3 ib /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r
0F 98 /r 0F 01 /0 0F 01 /1 0F A4 /r 0F A5 /r 0F AC /r 0F AD /r 0F 00 /0 Register 0F 01 /4 F9 FD FB AA AB 0F 00 /1 2C 2D 80 /5 81 /5 83 /5 28 /r 29 /r 2A /r 2B /r A8 A9 F6 /0 F7 /0 84 /r 85 /r 85 /r 0F 0B 0F 00 /4 0F 00 /5 9B 9B 0F 09 0F 30 0F C0 /r 0F C1 /r 0F C1 /r 90+rd 90+rd 86 /r 86 /r 87 /r 87 /r D7 34 35 80 /6 81 /6 83 /6
ib ib
SETS SGDT SIDT SHLD SHLD SHRD SHRD SLDT
r/m8 m m r/m32,r32,imm8 r/m32,r32,CL r/m32,r32,imm8 r/m32,r32,CL r/m32
Set byte if sign Store GDTR to m Store IDTR to m Double Precision Shift Double Precision Shift Double Precision Shift Double Precision Shift Store Local Descriptor
Left Left Right Right Table
ib id ib id ib
ib id ib id
ib id ib id ib
SMSW r/m32 STC STD STI STOS m8 STOS m32 STR r/m16 SUB AL,imm8 SUB EAX,imm32 SUB r/m8,imm8 SUB r/m32,imm32 SUB r/m32,imm8 SUB r/m8,r8 SUB r/m32,r32 SUB r8,r/m8 SUB r32,r/m32 TEST AL,imm8 TEST EAX,imm32 TEST r/m8,imm8 TEST r/m32,imm32 TEST r/m8,r8 TEST r/m16,r16 TEST r/m32,r32 UD2 VERR r/m16 VERW r/m16 WAIT FWAIT WBINVD WRMSR XADD r/m8,r8 XADD r/m16,r16 XADD r/m32,r32 XCHG EAX,r32 XCHG r32,EAX XCHG r/m8,r8 XCHG r8,r/m8 XCHG r/m32,r32 XCHG r32,r/m32 XLAT m8 XOR AL,imm8 XOR EAX,imm32 XOR r/m8,imm8 XOR r/m32,imm32 XOR r/m32,imm8
Store Machine Status Word Set Carry Flag Set Direction Flag Set Interrup Flag Store String Store String Store Task Register Subtract Subtract Subtract Subtract Subtract Subtract Subtract Subtract Subtract Logical Compare Logical Compare Logical Compare Logical Compare Logical Compare Logical Compare Logical Compare Undifined Instruction Verify a Segment for Reading Verify a Segment for Writing Wait Wait Write Back and Invalidate Cache Write to Model Specific Register Exchange and Add Exchange and Add Exchange and Add Exchange r32 with EAX Exchange EAX with r32 Exchange byte Exchange byte Exchange doubleword Exchange doubleword Table Look-up Translation Logical Exclusive OR Logical Exclusive OR Logical Exclusive OR Logical Exclusive OR Logical Exclusive OR
30 31 32 33
/r /r /r /r
XOR XOR XOR XOR
r/m8,r8 r/m32,r32 r8,r/m8 r32,r/m32
Logical Logical Logical Logical
Exclusive Exclusive Exclusive Exclusive
OR OR OR OR
Opcode ordered Listing ========================================================================= ====== Opcode,Data Instruction Explanation -----------------------------------------------------------------------------00 /r ADD r/m8,r8 ADD 01 /r ADD r/m32,r32 ADD 02 /r ADD r8,r/m8 ADD 03 /r ADD r32,r/m32 ADD 04 ib ADD AL,imm8 Add 05 id ADD EAX,imm32 Add 06 PUSH ES Push ES 07 POP ES Pop ES 08 /r OR r/m8,r8 OR 09 /r OR r/m32,r32 OR 0A /r OR r8,r/m8 OR 0B /r OR r32,r/m32 OR 0C ib OR AL,imm8 OR 0D id OR EAX,imm32 OR 0E PUSH CS Push CS 0F 00 /0 SLDT r/m32 Store Local Descriptor Table Register 0F 00 /1 STR r/m16 Store Task Register 0F 00 /2 LLDT r/m16 Load segment selector r/m16 into LDTR 0F 00 /3 LTR r/m16 Load Task Register 0F 00 /4 VERR r/m16 Verify a Segment for Reading 0F 00 /5 VERW r/m16 Verify a Segment for Writing 0F 01 /0 SGDT m Store GDTR to m 0F 01 /1 SIDT m Store IDTR to m 0F 01 /2 LGDT m16&32 Load m into GDTR 0F 01 /3 LIDT m16&32 Load m into IDTR 0F 01 /4 SMSW r32/m16 Store Machine Status Word 0F 01 /6 LMSW r/m16 Load r/m16 in machine status word of CR0 0F 01 /7 INVLPG m Invalidate TLB Entry for page (m) 0F 02 /r LAR r32,r/m32 Load Access Rights Byte 0F 03 /r LSL r16,r/m16 Load Segment Limit 0F 03 /r LSL r32,r/m32 Load Segment Limit 0F 05 LOADALL undocumented load all // 1998.11.05 0F 06 CLTS Clear Task-Switched Flag in Control Reg. Zero 0F 08 INVD Flush internal caches 0F 09 WBINVD Write Back and Invalidate Cache 0F 0B UD2 Undefined Instruction -----------------------------------------------0F 0D PREFETCH 3DNOW (K6)
0F 0E FEMMS 3DNOW (K6) 0F 0F /r BF PAVGUSB mm,mm/m64 3DNOW (K6) 0F 0F /r 9E PFADD mm,mm/m64 3DNOW (k6) 0F 0F /r 9A PFSUB mm,mm/m64 3DNOW (k6) 0F 0F /r AA PFSUBR mm,mm/m64 3DNOW (K6) 0F 0F /r AE PFACC mm,mm/m64 3DNOW (k6) 0F 0F /r 90 PFCMPGE mm,mm/m64 3DNOW (k6) 0F 0F /r A0 PFCMPGT mm,mm/m64 3DNOW (k6) 0F 0F /r B0 PFCMPEQ mm,mm/m64 3DNOW (k6) 0F 0F /r 94 PFMIN mm,mm/m64 3DNOW (k6) 0F 0F /r A4 PFMAX mm,mm/m64 3DNOW (k6) 0F 0F /r 0D PI2FD mm,mm/m64 3DNOW (k6) 0F 0F /r 1D PF2ID mm,mm/m64 3DNOW (k6) 0F 0F /r 96 PFRCP mm,mm/m64 3DNOW (k6) 0F 0F /r 97 PFRSQRT mm,mm/m64 3DNOW (k6) 0F 0F /r B4 PFMUL mm,mm/m64 3DNOW (k6) 0F 0F /r A6 PFRCPIT1 mm,mm/m64 3DNOW (k6) 0F 0F /r A7 PFRSQIT1 mm,mm/m64 3DNOW (k6) 0F 0F /r B6 PFRCPIT2 mm,mm/m64 3DNOW (k6) 0F 0F /r B7 PMULHRW mm,mm/m64 3DNOW (k6) -----------------------------------------------0F 20 /r MOV r32,CR0 Move CR0 to r32 0F 20 /r MOV r32,CR2 Move CR2 to r32 0F 20 /r MOV r32,CR3 Move CR3 to r32 0F 20 /r MOV r32,CR4 Move CR4 to r32 0F 21 /r MOV r32,DR0-DR7 Move debug register to r32 0F 22 /r MOV CR0, r32 Move r32 to CR0 0F 22 /r MOV CR2, r32 Move r32 to CR2 0F 22 /r MOV CR3, r32 Move r32 to CR3 0F 22 /r MOV CR4, r32 Move r32 to CR4 0F 23 /r MOV DR0-DR7,r32 Move r32 to debug register 0F 24 /r MOV 0F 26 /r MOV 0F 30 WRMSR Write to Model Specific Register 0F 31 RDTSC Read Time-Stamp Counter 0F 32 RDMSR Read from Model Specific Register 0F 33 RDPMC Read Performance-Monitoring counters 0F 34 SYSENTER 0F 35 SYSEXIT 0F 40 /r CMOVO r32,r/m32 Move if overflow 0F 41 /r CMOVNO r32,r/m32 Move if not overflow 0F 42 /r CMOVB r32,r/m32 Move if below 0F 42 /r CMOVC r32,r/m32 Move if carry 0F 42 /r CMOVNAE r32,r/m32 Move if not above or equal 0F 43 /r CMOVAE r32,r/m32 Move if above or equal 0F 43 /r CMOVNB r32,r/m32 Move if not below 0F 43 /r CMOVNC r32,r/m32 Move if not carry 0F 44 /r CMOVE r32,r/m32 Move if equal 0F 44 /r CMOVZ r32,r/m32 Move if zero 0F 45 /r CMOVNE r32,r/m32 Move if not equal 0F 45 /r CMOVNZ r32,r/m32 Move if not zero 0F 46 /r CMOVBE r32,r/m32 Move if below or equal 0F 46 /r CMOVNA r32,r/m32 Move if not above 0F 47 /r CMOVA r32,r/m32 Move if above
0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F
47 48 49 4A 4A 4B 4B 4C 4C 4D 4D 4E 4E 4F 4F 60 61 62 63 64 65 66 67 68 69 6A 6B 6E 6F 71 71 71 72 72 72 73 73 74 75 76 77 7E 7F 80 81 82 83 84 85 86 87 88 89 8A
/r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /r /2 /4 /6 /2 /4 /6 /2 /6 /r /r /r /r /r
ib ib ib ib ib ib ib ib
cd cd cd cd cd cd cd cd cd cd cd
CMOVNBE r32,r/m32 CMOVS r32,r/m32 CMOVNS r32,r/m32 CMOVP r32,r/m32 CMOVPE r32,r/m32 CMOVNP r32,r/m32 CMOVPO r32,r/m32 CMOVL r32,r/m32 CMOVNGE r32,r/m32 CMOVGE r32,r/m32 CMOVNL r32,r/m32 CMOVLE r32,r/m32 CMOVNG r32,r/m32 CMOVG r32,r/m32 CMOVNLE r32,r/m32 PUNPCKLBW mm,mm/m32 PUNPCKLWD mm,mm/m32 PUNPCKLDQ mm,mm/m32 PACKSSWB mm,mm/m64 PCMPGTB mm,mm/m64 PCMPGTW mm,mm/m64 PCMPGTD mm,mm/m64 PACKUSWB mm,mm/m64 PUNPCKHBW mm,mm/m64 PUNPCKHWD mm,mm/m64 PUNPCKHDQ mm,mm/m64 PACKSSDW mm,mm/m64 MOVD mm,r/m32 MOVQ mm,mm/m64 PSRLW mm,imm8 PSRAW mm,imm8 PSLLW mm,imm8 PSRLD mm,imm8 PSRAD mm,imm8 PSLLD mm,imm8 PSRLQ mm,imm8 PSLLQ mm,imm8 PCMPEQB mm,mm/m64 PCMPEQW mm,mm/m64 PCMPEQD mm,mm/m64 EMMS MOVD r/m32,mm MOVQ mm/m64,mm JO rel32 JNO rel32 JB rel32 JAE rel32 JE rel32 JNE rel32 JBE rel32 JA rel32 JS rel32 JNS rel32 JPE rel32
Move if not below or equal Move if sign Move if not sign Move if parity Move if parity even Move if not parity Move if parity odd Move if less Move if not greater or equal Move if greater or equal Move if not less Move if less or equal Move if not greater Move if greater Move if not less or equal Unpack Low Packed Data Unpack Low Packed Data Unpack Low Packed Data Pack with Signed Saturation Packed Compare for GT Packed Compare for GT Packed Compare for GT Pack with Unsigned Saturation Unpack High Packed Data Unpack High Packed Data Unpack High Packed Data Pack with Signed Saturation Move doubleword from r/m32 to mm Move quadword from mm/m64 to mm Packed Shift Right Logical Packed Shift Right Arithmetic Packed Shift Left Logical Packed Shift Right Logical Packed Shift Right Arithmetic Packed Shift Left Logical Packed Shift Right Logical Packed Shift Left Logical Packed Compare for Equal Packed Compare for Equal Packed Compare for Equal Set the FP tag word to empty Move doubleword from mm to r/m32 Move quadword from mm to mm/m64 Jump near if overflow Jump near if not overflow Jump near if below Jump near if above or equal Jump near if equal Jump near if not equal Jump near if below or equal Jump near if above Jump near if sign Jump near if not sign Jump near if parity even
0F 8B cd 0F 8C cd 0F 8D cd 0F 8E cd 0F 8F cd 0F 90 /r 0F 91 /r 0F 92 /r 0F 93 /r 0F 94 /r 0F 95 /r 0F 96 /r 0F 97 /r 0F 98 /r 0F 99 /r 0F 9A /r 0F 9B /r 0F 9C /r 0F 9D /r 0F 9E /r 0F 9F /r 0F A0 0F A1 0F A2 0F A3 /r 0F A4 /r ib 0F A5 /r 0F A8 0F A9 0F AA 0F AB /r 0F AC /r ib 0F AD /r 0F AE /0 0F AE /1 0F AE /2 0F AE /3 0F AE /7 0F AF /r 0F B0 /r 0F B1 /r 0F B2 /r 0F B3 /r 0F B4 /r 0F B5 /r 0F B6 /r extension 0F B7 /r extension 0F BA /4 ib 0F BA /5 ib 0F BA /6 ib 0F BA /7 ib 0F BB /r
JPO rel32 JL rel32 JGE rel32 JLE rel32 JG rel32 SETO r/m8 SETNO r/m8 SETB r/m8 SETAE r/m8 SETE r/m8 SETNE r/m8 SETBE r/m8 SETA r/m8 SETS r/m8 SETNS r/m8 SETPE r/m8 SETPO r/m8 SETL r/m8 SETGE r/m8 SETLE r/m8 SETG r/m8 PUSH FS POP FS CPUID BT r/m32,r32 SHLD r/m32,r32,imm8 SHLD r/m32,r32,CL PUSH GS POP GS RSM BTS r/m32,r32 SHRD r/m32,r32,imm8 SHRD r/m32,r32,CL FXSAVE m512 FXRSTOR m512 LDMXCSR m STMXCSR m SFENCE IMUL r32,r/m32 CMPXCHG r/m8,r8 CMPXCHG r/m32,r32 LSS r32,m16:32 BTR r/m32,r32 LFS r32,m16:32 LGS r32,m16:32 MOVZX r32,r/m8 MOVZX r32,r/m16 BT r/m32,imm8 BTS r/m32,imm8 BTR r/m32,imm8 BTC r/m32,imm8 BTC r/m32,r32
Jump near if parity odd Jump near if less Jump near if greater or equal Jump near if less or equal Jump near if greater Set byte if overflow Set byte if not overflow Set byte if below Set byte if above or equal Set byte if equal Set byte if not equal Set byte if below or equal Set byte if above Set byte if sign Set byte if not sign Set byte if parity even Set byte if parity odd Set byte if less Set byte if greater or equal Set byte if less or equal Set byte if greater Push FS Pop FS EAX := Processor id.info. Bit Test Double Precision Shift Left Double Precision Shift Left Push GS Pop GS Resume from System Management Bit Test and Set Double Precision Shift Right Double Precision Shift Right ?? ?? ?? ?? ?? Multiply Compare and Exchange Compare and Exchange Load SS:r32 with far ptr Bit Test and Clear Load FS:r32 with far ptr Load GS:r32 with far ptr Move byte to doubleword, zeroMove word to doubleword, zeroBit Bit Bit Bit Bit Test Test Test Test Test and and and and Set Clear Complement Complement
0F BC /r 0F BD /r 0F BE /r extension 0F BF /r extension 0F C0 /r 0F C1 /r 0F C1 /r 0F C7 /1 m64 0F C8+rd 0F D1 /r 0F D2 /r 0F D3 /r 0F D5 /r 0F D8 /r 0F D9 /r 0F DB /r 0F DC /r 0F DD /r 0F DF /r 0F E1 /r 0F E2 /r 0F E5 /r 0F E8 /r 0F E9 /r 0F EB /r 0F EC /r 0F ED /r 0F EF /r 0F F1 /r 0F F2 /r 0F F3 /r 0F F5 /r 0F F8 /r 0F F9 /r 0F FA /r 0F FC /r 0F FD /r 0F FE /r 10 /r 11 /r 12 /r 13 /r 14 ib 15 id 16 17 18 /r 19 /r 1A /r 1B /r 1C ib 1D id
BSF r32,r/m32 BSR r32,r/m32 MOVSX r32,r/m8 MOVSX r32,r/m16 XADD r/m8,r8 XADD r/m16,r16 XADD r/m32,r32 CMPXCHG8B m64 BSWAP r32 PSRLW mm,mm/m64 PSRLD mm,mm/m64 PSRLQ mm,mm/m64 PMULLW mm,mm/m64 PSUBUSB mm,mm/m64 PSUBUSW mm,mm/m64 PAND mm,mm/m64 PADDUSB mm,mm/m64 PADDUSW mm,mm/m64 PANDN mm,mm/m64 PSRAW mm,mm/m64 PSRAD mm,mm/m64 PMULHW mm,mm/m64 PSUBSB mm,mm/m64 PSUBSW mm,mm/m64 POR mm,mm/m64 PADDSB mm,mm/m64 PADDSW mm,mm/m64 PXOR mm,mm/m64 PSLLW mm,mm/m64 PSLLD mm,mm/m64 PSLLQ mm,mm/m64 PMADDWD mm,mm/m64 PSUBB mm,mm/m64 PSUBW mm,mm/m64 PSUBD mm,mm/m64 PADDB mm,mm/m64 PADDW mm,mm/m64 PADDD mm,mm/m64 ADC r/m8,r8 ADC r/m32,r32 ADC r8,r/m8 ADC r32,r/m32 ADC AL,imm8 ADC EAX,imm32 PUSH SS POP SS SBB r/m8,r8 SBB r/m32,r32 SBB r8,r/m8 SBB r32,r/m32 SBB AL,imm8 SBB EAX,imm32
Bit scan forward on r/m32 Bit scan reverse on r/m32 Move byte to doubleword, signMove word to doubleword, signExchange and Add Exchange and Add Exchange and Add Compare and Exchange Reverses the byte order of a r32 Packed Shift Right Logical Packed Shift Right Logical Packed Shift Right Logical Packed Multiply Low Packed Subtract Unsigned with S. Packed Subtract Unsigned with S. AND quadword from .. to .. Add unsigned pkd bytes Add unsigned pkd words And qword from .. to NOT qw in mm Packed Shift Right Arithmetic Packed Shift Right Arithmetic Packed Multiply High Packed Subtract with Saturation Packed Subtract with Saturation OR qword from .. to mm Add signed packed bytes Add signed packed words XOR qword Packed Shift Left Logical Packed Shift Left Logical Packed Shift Left Logical Packed Multiply and Add Packed Subtract Packed Subtract Packed Subtract Add packed bytes Add packed words Add packed dwords Add with carry Add with carry Add with carry Add with carry Add with carry Add with carry Push SS Pop SS Subtract with borrow Subtract with borrow Subtract with borrow Subtract with borrow Subtract with borrow Subtract with borrow
1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40+rd 48+rd 50+rd 58+rd 60 61 62 63 Sel. 64 65 66 67 68 69 69 6A 6B 6B
/r /r /r /r ib id /r /r /r /r ib id /r /r /r /r ib id /r /r /r /r ib id
/r /r
PUSH DS POP DS AND r/m8,r8 AND r/m32,r32 AND r8,r/m8 AND r32,r/m32 AND AL,imm8 AND EAX,imm32 ES: DAA SUB r/m8,r8 SUB r/m32,r32 SUB r8,r/m8 SUB r32,r/m32 SUB AL,imm8 SUB EAX,imm32 CS: DAS XOR r/m8,r8 XOR r/m32,r32 XOR r8,r/m8 XOR r32,r/m32 XOR AL,imm8 XOR EAX,imm32 SS: AAA CMP r/m8,r8 CMP r/m32,r32 CMP r8,r/m8 CMP r32,r/m32 CMP AL,imm8 CMP EAX,imm32 DS: AAS INC r32 DEC r32 PUSH r32 POP r32 PUSHAD POPAD BOUND r32,m32&32 ARPL r/m16,r16 FS: GS: Opsize: Address: PUSH imm32 IMUL r32,imm32 IMUL r32,r/m32,imm32 PUSH imm8 IMUL r32,imm8 IMUL r32,r/m32,imm8
Push DS Pop DS AND AND AND AND AND AND Segment overide prefix Decimal adjust AL after addition Subtract Subtract Subtract Subtract Subtract Subtract Segment overide prefix Decimal adjust AL after subtraction Logical Exclusive OR Logical Exclusive OR Logical Exclusive OR Logical Exclusive OR Logical Exclusive OR Logical Exclusive OR Segment overide prefix ASCII adjust AL after addition Compare Compare Compare Compare Compare Compare Segment overide prefix ASCII adjust AL after subtraction Increment register by 1 Decrement r32 by 1 Push r32 Pop r32 Push All g-regs Pop EDI,... and EAX Check Array Index Against Bounds Adjust Request Privilege Level of Segment overide prefix Segment overide prefix Operand size overide prefix Address size overide prefix Push imm32 Multiply Multiply Push imm8 Multiply Multiply
id /r id /r id ib /r ib /r ib
6C ES:(E)DI 6D 6E 6F (DX) 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 /0 80 /1 80 /2 80 /3 80 /4 80 /5 80 /6 80 /7 81 /0 81 /1 81 /2 81 /3 81 /4 81 /5 81 /6 81 /7 83 /0 83 /1 83 /2 83 /3 83 /4 83 /5 83 /6 83 /7 84 /r 85 /r 85 /r 86 /r 86 /r 87 /r 87 /r 88 /r
INS m8 INS m32 OUTS DX,m8 OUTS DX,m32 cb cb cb cb cb cb cb cb cb cb cb cb cb cb cb cb ib ib ib ib ib ib ib ib id id id id id id id id ib ib ib ib ib ib ib ib JO rel8 JNO rel8 JC rel8 JAE rel8 JE rel8 JNE rel8 JBE rel8 JA rel8 JS rel8 JNS rel8 JPE rel8 JPO rel8 JL rel8 JGE rel8 JLE rel8 JG rel8 ADD r/m8,imm8 OR r/m8,imm8 ADC r/m8,imm8 SBB r/m8,imm8 AND r/m8,imm8 SUB r/m8,imm8 XOR r/m8,imm8 CMP r/m8,imm8 ADD r/m32,imm32 OR r/m32,imm32 ADC r/m32,imm32 SBB r/m32,imm32 AND r/m32,imm32 SUB r/m32,imm32 XOR r/m32,imm32 CMP r/m32,imm32 ADD r/m32,imm8 OR r/m32,imm8 ADC r/m32,imm8 SBB r/m32,imm8 AND r/m32,imm8 SUB r/m32,imm8 XOR r/m32,imm8 CMP r/m32,imm8 TEST r/m8,r8 TEST r/m16,r16 TEST r/m32,r32 XCHG r/m8,r8 XCHG r8,r/m8 XCHG r/m32,r32 XCHG r32,r/m32 MOV r/m8,r8
Input byte from I/O(DX) into Input dw from I/O(DX) into ES:(E)DI Output byte from DS:(E)SI to I/O(DX) Output dword from DS:(E)SI to I/O Jump short if overflow Jump short if not overflow Jump short if carry Jump short if above or equal Jump short if equal Jump short if not equal Jump short if below or equal Jump short if above Jump short if sign Jump short if not sign Jump short if parity even Jump short if parity odd Jump short if less Jump short if greater or equal Jump short if less or equal Jump short if greater Add OR Add with carry Subtract with borrow AND Subtract Logical Exclusive OR Compare Add OR Add with carry Subtract with borrow AND Subtract Logical Exclusive OR Compare Add OR Add with carry Subtract with borrow AND Subtract Logical Exclusive OR Compare Logical Compare Logical Compare Logical Compare Exchange byte Exchange byte Exchange doubleword Exchange doubleword Move
89 /r 8A /r 8B /r 8C /r 8D /r 8E /r 8F /0 90 90+rd 90+rd 98 99 99 9A 9B 9B 9B D9 /6 9B D9 /7 9B DB E2 9B DB E3 9B DD /6 9B DD /7 after 9B DF E0 9C 9D 9E 9F A0 A1 A1 A2 A3 A3 A4 A5 A6 ES:(E)DI A7 ES:(E)DI A8 A9 AA AB AC AL AD EAX AE AF B0+rb B8+rd C0 /0 C0 /1
cp
MOV r/m32,r32 MOV r8,r/m8 MOV r32,r/m32 MOV r/m16,Sreg** LEA r32,m MOV Sreg,r/m16** POP m32 NOP XCHG EAX,r32 XCHG r32,EAX CBW CDQ CWD CALL ptr16:32 FWAIT WAIT FSTENV m14/28byte FSTCW m2byte FCLEX FINIT FSAVE m94/108byte FSTSW m2byte FSTSW AX PUSHFD POPFD SAHF LAHF MOV AL, moffs8* MOV AX, moffs16* MOV EAX, moffs32* MOV moffs8*,AL MOV moffs16*,AX MOV moffs32*,EAX MOVS m8,m8 MOVS m32,m32 CMPSB CMPSD
Move Move Move Move segment register to r/m16 Load effective address Move r/m16 to segment register Pop m32 No operation Exchange r32 with EAX Exchange EAX with r32 Convert Byte to Word Convert Doubleword to Quadword Convert Word to Doubleword Call far, abs.add. given in operand Wait Wait Store FPU environment Store FPU control word Clear f.e.f. after checking for .. Initialize FPU after ... Store FPU status to m94 or m108 Store FPU status word at m2byte Store FPU status word in AX after Push EFLAGS Pop Stack into EFLAGS Register Store AH into Flags Load Status Flags into AH Move byte at ( seg:offset) to AL Move word at ( seg:offset) to AX Move dword at ( seg:offset) to EAX Move AL to ( seg:offset) Move AX to ( seg:offset) Move EAX to ( seg:offset) Move byte at DS:(E)SI to ES:(E)DI Move dword at DS:(E)SI to ES:(E)DI Compare byte at DS:(E)SI with Compare dw at DS:(E)SI with
ib id
TEST TEST STOS STOS LODS
AL,imm8 EAX,imm32 m8 m32 m8
Logical Compare Logical Compare Store String Store String Load byte at address DS:(E)SI into Load dword at address DS:(E)SI into Scan String Scan String Move imm8 to r8 Move imm32 to r32 Rotate 8 bits r/m8 left imm8 times Rotate 8 bits r/m16 right imm8 times
LODS m32 SCAS m8 SCAS m32 MOV r8,imm8 MOV r32,imm32 ROL r/m8,imm8 ROR r/m8,imm8
ib ib
C0 C0 C0 C0 C0 C0 C1 C1 times C1 C1 C1 C1 C1 C1 C2 stack C3 C4 C5 C6 C7 C8 C8 proc. C8 proc. C9 CA stack CB CC CD CE CF D0 D0 D0 D0 D0 D0 D0 D0 D1 D1 D1 D1 D1 D1 D1 D1 D2 D2 D2
/2 /3 /4 /4 /5 /7 /0 /1 /2 /3 /4 /4 /5 /7
ib ib ib ib ib ib ib ib ib ib ib ib ib ib iw
RCL RCR SAL SHL SHR SAR ROL ROR RCL RCR SAL SHL SHR SAR RET
r/m8,imm8 r/m8,imm8 r/m8,imm8 r/m8,imm8 r/m8,imm8 r/m8,imm8 r/m32,imm8 r/m32,imm8 r/m32,imm8 r/m32,imm8 r/m32,imm8 r/m32,imm8 r/m32,imm8 r/m32,imm8 imm16
Rotate 9 bits left imm8 times Rotate 9 bits right imm8 times Shift Arithmetic Left Shift Logical Left Shift Logical Right Shift Arithmetic Right Rotate 32 bits r/m32 left imm8 times Rotate 32 bits r/m32 right imm8 Rotate 33 bits left imm8 times Rotate 33 bits right imm8 times Shift Arithmetic Left Shift Logical Left Shift Logical Right Shift Arithmetic Right Near return, pop imm16 bytes from Near return Load ES:r32 with far ptr Load DS:r32 with far ptr Move imm8 to r/m8 Move imm32 to r/m32 Create a stack frame for a procedure Create a nested stack frame for a Create a nested stack frame for a Set ESP to EBP, then pop EBP Far return, pop imm16 bytes from Far return Interrupt 3--trap to debugger Interrupt vector number (imm8) Interrupt 4--if overflow flag is 1 Interrupt return(32) Rotate 8 bits r/m8 left once Rotate 8 bits r/m8 right once Rotate 9 bits left once Rotate 9 bits right once Shift Arithmetic Left Shift Logical Left Shift Logical Right Shift Arithmetic Right Rotate 32 bits r/m32 left once Rotate 32 bits r/m32 right once Rotate 33 bits left once Rotate 33 bits right once Shift Arithmetic Left Shift Logical Left Shift Logical Right Shift Arithmetic Right Rotate 8 bits r/m8 left CL times Rotate 8 bits r/m8 right CL times Rotate 9 bits left CL times
/r /r /0 ib /0 id iw 00 iw 01
RET LES r32,m16:32 LDS r32,m16:32 MOV r/m8,imm8 MOV r/m32,imm32 ENTER imm16,0 ENTER imm16,1
iw ib ENTER imm16,imm8 iw LEAVE RET imm16 RET INT 3 INT imm8 INTO IRETD ROL r/m8,1 ROR r/m8,1 RCL r/m8,1 RCR r/m8,1 SAL r/m8,1 SHL r/m8,1 SHR r/m8,1 SAR r/m8,1 ROL r/m32,1 ROR r/m32,1 RCL r/m32,1 RCR r/m32,1 SAL r/m32,1 SHL r/m32,1 SHR r/m32,1 SAR r/m32,1 ROL r/m8,CL ROR r/m8,CL RCL r/m8,CL
ib /0 /1 /2 /3 /4 /4 /5 /7 /0 /1 /2 /3 /4 /4 /5 /7 /0 /1 /2
D2 /3 D2 /4 D2 /4 D2 /5 D2 /7 D3 /0 D3 /1 D3 /2 D3 /3 D3 /4 D3 /4 D3 /5 D3 /7 D4 0A D5 0A D6 D7 D8 /0 ST(0) D8 /1 ST(0) D8 /2 D8 /3 r.stack. D8 /4 ST(0) D8 /5 ST(0) D8 /6 ST(0) D8 /7 ST(0) D8 C0+i D8 C8+i ST(0) D8 D0+i D8 D1 D8 D8+i D8 D9 D8 E0+i ST(0) D8 E8+i ST(0) D8 F0+i ST(0) D8 F8+i ST(0) D9 /0 D9 /2 D9 /3 D9 /4 D9 /5 D9 /6 D9 /7
RCR r/m8,CL SAL r/m8,CL SHL r/m8,CL SHR r/m8,CL SAR r/m8,CL ROL r/m32,CL ROR r/m32,CL RCL r/m32,CL RCR r/m32,CL SAL r/m32,CL SHL r/m32,CL SHR r/m32,CL SAR r/m32,CL AAM AAD SETALC XLAT m8 FADD m32real FMUL m32real FCOM m32real FCOMP m32real FSUB m32real FSUBR m32real FDIV m32real FDIVR m32real FADD ST(0),ST(i) FMUL ST(0),ST(i) FCOM ST(i) FCOM FCOMP ST(i) FCOMP FSUB ST(0),ST(i) FSUBR ST(0),ST(i) FDIV ST(0),ST(i) FDIVR ST(0),ST(i) FLD m32real FST m32real FSTP m32real FLDENV m14/28byte FLDCW m2byte FNSTENV m14/28byte FNSTCW m2byte
Rotate 9 bits right CL times Shift Arithmetic Left Shift Logical Left Shift Logical Right Shift Arithmetic Right Rotate 32 bits r/m32 left CL times Rotate 32 bits r/m32 right CL times Rotate 33 bits left CL times Rotate 33 bits right CL times Shift Arithmetic Left Shift Logical Left Shift Logical Right Shift Arithmetic Right ASCII adjust AX after multiplication ASCII adjust AX before division Set ALC: undocumented Table Look-up Translation Add m32real to ST(0) and s.r. in Multiply ST(0) by m32real and s.r.in Compare ST(0) with m32real. Compare ST(0) with m32real,pop Sub m32real from ST(0) and s.r.in Sub ST(0) from m32real and s.r.in Divide ST(0) by m32real and s.r.in Divide m32real by ST(0) and s.r.in Add ST(0) to ST(i) and s.r.in ST(0) Multiply ST(0) by ST(i) and s.r.in Compare ST(0) with ST(i). Compare ST(0) with ST(1). Compare ST(0) with ST(i), pop Compare ST(0) with ST(1), pop Sub ST(i) from ST(0) and s.r.in Sub ST(0) from ST(i) and s.r.in Divide ST(0) by ST(i) and s.r.in Divide ST(i) by ST(0) and s.r.in Push m32real Copy ST(0) to m32real Copy ST(0) to m32real and pop Load FPU environment from m14/m28 Load FPU control word from m2byte Store FPU env without Store FPU control word without
D9 C0+i FLD ST(i) D9 C8+i FXCH ST(i) D9 C9 FXCH D9 D0 FNOP D9 E0 FCHS D9 E1 FABS value D9 E4 FTST D9 E5 FXAM D9 E8 FLD1 D9 E9 FLDL2T D9 EA FLDL2E D9 EB FLDPI D9 EC FLDLG2 D9 ED FLDLN2 D9 EE FLDZ D9 F0 F2XM1 D9 F1 FYL2X and pop D9 F2 FPTAN 1.0 D9 F3 FPATAN arctan(ST(1)/ST(0)) pop D9 F4 FXTRACT sig. D9 F5 FPREM1 rem(ST(0)/ST(1)) D9 F6 FDECSTP word. D9 F7 FINCSTP r. D9 F8 FPREM (ST(0)/ST(1)) D9 F9 FYL2XP1 ST(1)*log2(ST(0)+1) pop D9 FA FSQRT D9 FB FSINCOS push c D9 FC FRNDINT D9 FD FSCALE D9 FE FSIN D9 FF FCOS DA /0 FIADD m32int DA /1 FIMUL m32int ST(0) DA /2 FICOM m32int DA /3 FICOMP m32int DA /4 FISUB m32int ST(0) DA /5 FISUBR m32int ST(0) DA /6 FIDIV m32int ST(0)
Push ST(i) Exchange ST(0) and ST(i) Exchange ST(0) and ST(1) No operation is performed Complements sign of ST(0) Replace ST(0) with its absolute Compare ST(0) with 0.0 Classify value or number in ST(0) Push +1.0 Push log2 10 Push log2 e Push pi Push log10 2 Push loge 2 Push +0.0 Replace ST(0) with 2**ST(0) - 1 Replace ST(1) with ST(1)*log2ST(0) Replaces ST(0) with its tangent push Repalces ST(1) with Seperate value in ST(0) exp. and Replaces ST(0) with IEEE Decrement TOP field in FPU status Increment the TOP field FPU status Replaces ST(0) with rem Replace ST(1) with square root of ST(0) Compute sine and consine of ST(0) s Round ST(0) to an integer Scale ST(0) by ST(1) Replace ST(0) with its sine Replace ST(0) with its cosine Add m32int to ST(0) and s.r.in ST(0) Multiply ST(0) by m32int and s.r.in Compare ST(0) with m32int Compare ST(0) with m32int and pop Sub m32int from ST(0) and s.r.in Sub ST(0) from m32int and s.r.in Divide ST(0) by m32int and s.r.in
DA /7 ST(0) DA C0+i DA C8+i DA D0+i DA D8+i DA E9 DB /0 DB /2 DB /3 DB /5 DB /7 DB C0+i DB C8+i DB D0+i DB D8+i DB E2 DB E3 DB E8+i o.v.set s.f. DB F0+i flags DC /0 ST(0) DC /1 ST(0) DC /2 DC /3 r.stack. DC /4 ST(0) DC /5 ST(0) DC /6 ST(0) DC /7 ST(0) DC C0+i DC C8+i ST(i) DC D0+i ST(i) DC D8+i DC E0+i ST(i) DC E8+i ST(i) DC F0+i ST(i) DC F8+i ST(i) DD /0 DD /2 DD /3
FIDIVR m32int FCMOVB ST(0),ST(i) FCMOVE ST(0),ST(i) FCMOVBE ST(0),ST(i) FCMOVU ST(0),ST(i) FUCOMPP FILD m32int FIST m32int FISTP m32int FLD m80real FSTP m80real FCMOVNB ST(0),ST(i) FCMOVNE ST(0),ST(i) FCMOVNBE ST(0),ST(i) FCMOVNU ST(0),ST(i) FNCLEX FNINIT FUCOMI ST,ST(i) FCOMI ST,ST(i) FADD m64real FMUL m64real FCOM m64real FCOMP m64real FSUB m64real FSUBR m64real FDIV m64real FDIVR m64real FADD ST(i),ST(0) FMUL ST(i),ST(0) FCOM ST(i),ST(0) FCOMP ST(i),ST(0) FSUBR ST(i),ST(0) FSUB ST(i),ST(0) FDIVR ST(i),ST(0) FDIV ST(i),ST(0) FLD m64real FST m64real FSTP m64real
Divide m32int by ST(0) and s.r.in Move if below Move if equal Move if below or equal Move if unordered Compare ST(0) with ST(1) and pop pop Push m32int Store ST(0) in m32int Store ST(0) in m32int and pop Push m80real Copy ST(0) to m80real and pop Move if not below Move if not equal Move if not below or equal Move if not unordered Clear f.e.f. without checking for .. Initialize FPU without ... Compare ST(0) with ST(i), check Compare ST(0) with ST(i), set status Add m64real to ST(0) and s.r.in Multiply ST(0) by m64real and s.r.in Compare ST(0) with m64real. Compare ST(0) with m64real,pop Sub m64real from ST(0) and s.r.in Sub ST(0) from m64real and s.r.in Divide ST(0) by m64real and s.r.in Divide m64real by ST(0) and s.r.in Add ST(i) to ST(0) and s.r. in ST(i) Multiply ST(i) by ST(0) and s.r.in Compare ST(i) with ST(0) and s.r.in Compare .. pop Sub ST(i) from ST(0) and s.r.in Sub ST(0) from ST(i) and s.r.in Divide ST(0) by ST(i) and s.r.in Divide ST(i) by ST(0) and s.r.in Push m64real Copy ST(0) to m64real Copy ST(0) to m64real and pop
DD /4 byte DD /6 DD /7 without DD C0+i DD D0+i DD D8+i DD E0+i DD E1 DD E8+i DD E9 DE /0 DE /1 ST(0) DE /2 DE /3 DE /4 ST(0) DE /5 ST(0) DE /6 ST(0) DE /7 ST(0) DE C0+i r.stack DE C1 r.stack DE C8+i ST(i) pop DE C9 ST(1) pop DE D9 DE E0+i pop DE E1 pop DE E8+i pop DE E9 pop DE F0+i pop DE F1 pop DE F8+i pop DE F9 pop DF /0 DF /2 DF /3 DF /4
FRSTOR m94/108byte FNSAVE m94/108byte FNSTSW m2byte FFREE ST(i) FST ST(i) FSTP ST(i) FUCOM ST(i) FUCOM FUCOMP ST(i) FUCOMP FIADD m16int FIMUL m16int FICOM m16int FICOMP m16int FISUB m16int FISUBR m16int FIDIV m16int FIDIVR m16int FADDP ST(i),ST(0) FADDP FMULP ST(i),ST(0) FMULP FCOMPP FSUBRP ST(i),ST(0) FSUBRP FSUBP ST(i),ST(0) FSUBP FDIVRP ST(i),ST(0) FDIVRP FDIVP ST(i),ST(0) FDIVP FILD m16int FIST m16int FISTP m16int FBLD m80bcd
Load FPU status from m94 or m108 Store FPU environment to m94 or m108 Store FPU status word at m2byte Sets tag for ST(i) to empty Copy ST(0) to ST(i) Copy ST(0) to ST(i) and pop Compare ST(0) with ST(i) Compare ST(0) with ST(1) Compare ST(0) with ST(i) and pop Compare ST(0) with ST(1) and pop Add m16int to ST(0) and s.r.in ST(0) Multiply ST(0) by m16int and s.r.in Compare ST(0) with m16int Compare ST(0) with m16int and pop Sub m16int from ST(0) and s.r.in Sub ST(0) from m16int and s.r.in Divide ST(0) by m64int and s.r.in Divide m64int by ST(0) and s.r.in Add ST(0) to ST(i), s.r.in ST(i),pop Add ST(0) to ST(1), s.r.in ST(1),pop Multiply ST(i) by ST(0), s.r.in Multiply ST(1) by ST(0), s.r.in Compare ST(0) with ST(1), pop pop Sub ST(i) from ST(0), s.r. in ST(i) Sub ST(1) from ST(0), s.r.in ST(1) Sub ST(0) from ST(i), s.r.in ST(i) Sub ST(0) from ST(1), s.r.in ST(1) Divide ST(0) by ST(i), s.r.in ST(i) Divide ST(0) by ST(1), s.r.in ST(1) Divide ST(i) by ST(0), s.r.in ST(i) Divide ST(1) by ST(0), s.r.in ST(1) Push m16int Store ST(0) in m16int Store ST(0) in m16int and pop Convert m80BCD to real and push
DF /5 DF /6 DF /7 DF E0 DF E8+i ovssf pop DF F0+i ,pop E0 cb E0 cb E1 cb E1 cb E2 cb E3 cb E4 ib address into E5 ib address into E6 ib E7 ib E8 cd E9 cd EA cp EB cb EC AL ED into EAX EE EF F0 F1 F2 A6 F2 A7 F2 AE F2 AF F3 6C ES:[(E)DI] F3 6D ES:[(E)DI] F3 6E port DX F3 6F port DX F3 A4 ES:[(E)DI] F3 A5 ES:[(E)DI] F3 A6 F3 A7 F3 AA F3 AB EAX F3 AC
FILD m64int FBSTP m80bcd FISTP m64int FNSTSW AX FUCOMIP ST,ST(i) FCOMIP ST,ST(i) LOOPNE rel8 LOOPNZ rel8 LOOPE rel8 LOOPZ rel8 LOOP rel8 JECXZ rel8 IN AL,imm8 AL IN EAX,imm8 EAX OUT imm8,AL OUT imm8,EAX CALL rel32 JMP rel32 JMP ptr16:32 JMP rel8 IN AL,DX IN EAX,DX OUT DX,AL OUT DX,EAX LOCK INT1 REPNE CMPS m8,m8 REPNE CMPS m32,m32 REPNE SCAS m8 REPNE SCAS m32 REP INS m8,DX REP INS m32,DX REP OUTS DX,m8 REP OUTS DX,m32 REP MOVS m8,m8 REP MOVS m32,m32 REPE CMPS m8,m8 REPE CMPS m32,m32 REP STOS m8 REP STOS m32 REP LODS AL
Push m64int Store ST(0) in m80bcd and pop ST(0) Store ST(0) in m64int and pop Store FPU status word in AX without Compare ST(0) with ST(i), check Compare ST(0) with ST(i), set s.f. Dec count;jump if count # 0 and Dec count;jump if count # 0 and Dec count;jump if count # 0 and Dec count;jump if count # 0 and Dec count;jump if count # 0 Jump short if ECX register is 0 Input byte from imm8 I/O port Input byte from imm8 I/O port Output byte in AL to I/O(imm8) Output dword in EAX to I/O(imm8) Call near, rel to n.inst Jump near, relative, Jump far, abs.add given in operand Jump short, relative, Input byte from I/O port in DX into Input doubleword from I/O port in DX Output byte in AL to I/O(DX) Output dword in EAX to I/O(DX) Asserts LOCK signal for duration .. ICEBP Find matching bytes in m and m Find matching dwords in m and m Find AL, starting at ES:[(E)DI] Find EAX, starting at ES:[(E)DI] Input ECX bytes from port DX into Input ECX dwords from port DX into Output ECX bytes from DS:[(E)SI] to Output ECX dwords from DS:[(E)SI] to Move ECX bytes from DS:[(E)SI] to Move ECX dwords from DS:[(E)SI] to Find Find Fill Fill nonmatching bytes in m and m nonmatching dwords in m and m ECX bytes at ES:[(E)DI] with AL ECX dwords at ES:[(E)DI] with ZF=0 ZF=0 ZF=1 ZF=1
Load ECX bytes from DS:[(E)SI] to AL
F3 AD REP LODS EAX Load ECX dwords from DS:[(E)SI] to EAX F3 AE REPE SCAS m8 Find non-AL byte starting at F3 AF REPE SCAS m32 Find non-EAX dword starting at F4 HLT Halt F5 CMC Complement CF flag F6 /2 NOT r/m8 Reverse each bit of r/m8 F6 /3 NEG r/m8 Two's complement negate r/m8 F6 /4 MUL r/m8 Unsigned multiply F6 /5 IMUL r/m8 Multiply F6 /6 DIV r/m8 Unsigned divide AX by r/m8 F6 /7 IDIV r/m8 Divide F6 /0 ib TEST r/m8,imm8 Logical Compare F7 /2 NOT r/m32 Reverse each bit of r/m32 F7 /3 NEG r/m32 Two's complement negate r/m32 F7 /4 MUL r/m32 Unsigned multiply F7 /5 IMUL r/m32 Multiply F7 /6 DIV r/m16 Unsigned divide DX:AX by r/m16 F7 /6 DIV r/m32 Unsigned divide EDX:EAX by r/m32 F7 /7 IDIV r/m32 Divide F7 /0 id TEST r/m32,imm32 Logical Compare F8 CLC Clear CF flag F9 STC Set Carry Flag FA CLI Clear interrupt flag FB STI Set Interrup Flag FC CLD Clear DF flag FD STD Set Direction Flag FE /0 INC r/m8 Increment 1 FE /1 DEC r/m8 Decrement r/m8 by 1 FF /0 INC r/m32 Increment 1 FF /1 DEC r/m32 Decrement r/m32 by 1 FF /2 CALL r/m32 Call near, abs.ind.add. given in r/m32 FF /3 CALL m16:32 Call far, abs.ind.add. given in m16:32 FF /4 JMP r/m32 Jump near, abs.ind.in r/m32 FF /6 PUSH r/m32 Push r/m32 FF /r JMP m16:32 Jump far, abs.ind.in m16:32 ========================================================================= ======