Exam Review by liaoqinmei

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									        Midterm 2 Review (1)

             Chapters 5, 6, 7, and 8 from
     “Digital Design --- Principles and Practices”
                 by John F. Wakerly

Topics from Midterm 1 are not explicitly asked, but
the much of that material will be needed to complete
answers here

          Open book, notes, & calculators
                                                       1
 Topics to be Reviewed Today

• Latches & Flip-Flops

• Registers and Counters

• State Machine Analysis




                               2
      Latches & Flip-Flops

• Circuits with feedback
  – Latches: R-S, D
  – Flip-flops: D, J-K, & T
  – Terms: set-up time, hold time, positive/negative edge
   triggered




                                                        3
Prob. 1. A NAND latch is constructed as shown below.
Each gate has a unit delay.




(a) Suppose m = n = y = 1 for a long time. Determine the
steady-state value of z. (z=0)
(b) Given input waveforms m and n, determine the waveforms
for y and z.




                                                           4
Prob. 2. The above D-Latch is constructed with four NAND
gates and an inverter. Suppose use NOR gates for the SR latch
part and AND gates substitute the other two NAND gates.
Write the function table.                S     R     Q     QN
                R                                  Last   Last
                                       0      0
                                                    Q     QN
                                       0      1     0      1
                                       1      0     1      0
                 S                     1      1     0      0
                                                            5
Prob. 3. Given the following sequential logic circuit, where the
D Flip-Flops have worst-case setup times of 10 ns, hold times
of 5 ns, and propagation delays of 15 ns. Assuming 0 ns
propagation delay through the combinational logic block, what
is the maximum allowable frequency of the clock?

                                        10 ns + 15 ns = 25 ns
                                          40 MHz




                                                              6
Prob. 4. Imagine we build up a flip-flop called PN flip-flop with
the operations: clear to 0, no change, complement, and set to 1,
when inputs P and N are 00, 01 , 10 , and 11, respectively.
a. Derive the characteristic equation.
b. Show how the PN flip-flop can be converted to a D flip-flop.

            P         N         Q*

            0         0         0          Clear

            0         1         Q        No change

            1         0       Not(Q)     Complement

            1         1         1           Set



                                                                  7
          P        N        Q         Q*
          0        0        X          0
          0        1        0          0
          0        1        1          1       Function table
          1        0        0          1
          1        0        1          0
          1        1        X          1
          Q*= QN + Q’P
b. Show how the PN flip-flop can be converted to a D flip-flop.
              Q     Q*     N      P        D
              0     0      X      0        0
              0     1      X      1        1
              1     0      0      X        0
              1     1      1      X        1
           P=D, N=D                                             8
          Registers and Counters
• Registers
   – storage registers
   – shift registers
• Counters
   – binary, decade, Gray code
   – complex (skipped states)




                                   9
                        Prob. 5. The left figure shows a 3-bit
                        ripple up-count.




How about the right figure:

                                                                 10
Prob. 6. Given a 60 MHz clock
signal, design a circuit using the
counter 74x163 to generate a
clock with a cycle time of 100 ns.




                                     11
Prob. 7. Show how to configure the shift
register 74x194 to realize:
a. Logic shift right, b. Logic shift left,
c. Arithmetic shift right, d. Arithmetic shift left.
Note:
Logic shift  fill the shifted positions with 0’s.
Arithmetic shift  propagate the high-order
sign bit to the right or shift in 0’s to the left.




                                                     12
      State Machine Analysis
• Moore machine configuration
   – output depends only on state
• Mealy machine configuration
   – output depends on state & inputs
• State machine analysis




                                        13
Prob. 8. Let’s consider the implementations of a bit-serial
adder. There are two inputs x1 and x0 and one output z. The
inputs represent two binary numbers, inputted bit-by-bit, with
the least significant bits presented first. The output is their
sum, as each pair of input bits is seen. For example,

                                          X0    01011010
                                          X1    10111010

                                           Z    11101101

                                        Left is the state diagram
                                        with the ½ transitions
                                        filled.
 a. Is this a Mealy machine or Moore machine? (Moore)
 b. Fill out the above state diagram.                               14
Prob. 9. Analyze the clocked synchronous state machine as
shown below. Input  X, Output  Z. State  AB. Write
excitation equations, transition equations, transition/output
table, and state/output table.
       :

         X       J  Q        A
                 C
 X
                 KR Q        A’
B’
               FFa
                     Reset

         Clk
                                   1. Excitation equations
         X       J  Q        B=Z
 X               C
                             B’
                                     Ja = X   Ka = X ·B’    Z=B
A’               KR Q
               FFb
                                     Jb = X   Kb = X xor A’
                     Reset


     2. Transition equations
     A* = Ja · A’ + Ka’ · A = X · A’ + (X’ + B) · A
     B* = Jb · B’ + Kb’ · B = X · B’ + (X · A’ + X’ · A) · B
                                                                  15
  2. Transition equations
 A* = Ja · A’ + Ka’ · A = X · A’ + (X’ + B) · A
 B* = Jb · B’ + Kb’ · B = X · B’ + (X · A’ + X’ · A) · B

3. Transition/Output table      4. State/Output table

               X                              X
 AB      0           1           State    0       1
 00      00          11    0      S0      S0     S3     0
 01      00          11    1      S1      S0     S3     1
 10      10          01    0      S2      S2     S1     0
 11      11          10    1      S3      S3     S2     1
              A*B*        Z=B             Next state    Z



                                                            16

								
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