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Trigger System

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					DAQ+trigger operation
  during 2008 run


            D. Nicolò
 University of Pisa & INFN, Pisa
                      Outlook
• DAQ
     – Data throughput & storage
     – Additional features
     – The slow control & alarms
• Trigger
     – Selection criteria
     – Efficiency & background rejection
     – Rates & Livetime
• DRS system
     – DRS2/3 performances
     – DRS4 design
• Improvements for 2009 run



October 19, 2011        DAQ+Trigger operation   2
DAQ
    Data throughput and storage
• Event & data rate
   – 6.5 ev/s, ~9 MB/s (@normal run)
   – max. 30 ev/s (limited by VME readout & DRS2 calibration)
     current %Live ~ 80%
• Data write to online disk
   – 2000 events/run        ~3 GB file size (smaller for calibration runs)
   – occupancy ~ 1 TB/d        100 TB/y
     (to be offline suppressed x3)
   – Disk available with 2TB capability
        • buffer for 2 days
• Data storage & monitoring
   – Lazy Logger process to
        • automatic copy to offline cluster ( total 100 TB HD)
   – gzip Midas data files (x0.5 compression)
   – Offline histos available soon afterwards (~ 10 min after Run stop)

 October 19, 2011             DAQ+Trigger operation                          4
      Offlinecheck: an example




October 19, 2011   DAQ+Trigger operation   5
                   DAQ features
• Automatic stop
    – Maximum event number completion       data size
• Run batch to be started from shell
    – Runsubmit xml script
    – Run parameters (#events, trigger operation, …) loaded to
      the online database (ODB)
• System running
  smoothly
• Major troubles
    – Event “mismatch”
    – FE hangs up
    – FE still busy at
      run start

October 19, 2011         DAQ+Trigger operation              6
              MSCB slow control

                               • 13 Ethernet “Submasters”
                               • 8 SCS-2000 units each with up to
                                 64 I/O
                               • Control of detector behaviour
                               • Newly added features
                                    • Separator HV
                                    • Beam shutter (beam on-off)
                               • Data recorder in the MIDAS
                                 history files available through the
                                 WEB page
                               • Alarm generation in the case of
                                 failures




October 19, 2011    DAQ+Trigger operation                    7
Trigger
                       Selection criteria
  QTL    QTH                           DWW


                           DWN




                     MeV

  g -energy                  e+-g direction              e+-g timing
trig.#         name               conditions
  0            MEG                QSUM > QTH && D < DN && |T| < TWN
  1        MEG-Q                  QSUM > QTL && D < DN && |T| < TWN
  2         MEG-D                 QSUM > QTH && D < DW && |T| < TWN
  3         MEG-T                 QSUM > QTH && D < DN && |T| < TWW
  4       RD-narrow                     QSUM > QTL   && |T| < TWN
           RD-wide
  5PSI - Jul. 18th, 2007                QSUM > QTL   && |T| < TWW
                                                                 9
              On-line Eγ resolution
        55 MeV γ-line from π0-decay




                                      σ = 3.8%

           45 MeV threshold
           (@4s from signal)




October 19, 2011                                 11
                                      Eγ efficiency
                   • Obtained from the ratio SH(Eγ)/SL(Eγ)
                     off-line energy spectra normalizated by using proton
                     current info


                                                     FWHM = 9,4%
0.5 counts/s/MeV




                                                      at 45 MeV




                        Threshold smearing mainly due to on-line energy resolution

                                               ε  99%
                   October 19, 2011        DAQ+Trigger operation                 12
                      Δteγ efficiency
|ΔT (LXe-TC)| < 10 ns
Spectrum expected to be flat (accidental background)
σ(ΔT) = (3.8±0.1) ns       εΔT ~ 99% (σt = 2.5 ns on each)



                    TRG type 0

                             B(p,g)C
                        (background free!)
                                   signal

                                 –online
                                 –offline

                                                 Δt (ns)

 October 19, 2011           DAQ+Trigger operation            13
                     e+-γ direction
       -    γ-position by max PMT in LXe
       - e+-position by charge asymmetry in TC
            (TC fibers not included yet)
       – association LUT based on MC

    Cross-check with the data (Radiative Decay sample)
    a) Search for e+ “good quality” track candidates
           (χ2, matched extrapolation to TC)
    b) Track a backward hypothetical γ from decay vertex;
    c) γ hit position  LXe PMT index;
    d) LXe PMT index  search for e+-hit on TC in the LUT
                           Work in progress
October 19, 2011           DAQ+Trigger operation            14
DRS
                     DRS in 2008
• DRS2
    – All analog channels equipped
         •   848 LXe PMTs
         •   60 TC PMTs
         •   1728 DC (anode + vernier)
         •   0.5 – 1.6 GHz sampling speed
    – Voltage non-linearity calibration in FE
    – Temperature dependence 1.4%/oC
• DRS3
    – 4 cards available
         • NIM TC DTD outputs
    – Voltage linearity (0 : 1 V)
    – Ghost pulse problem to be fixed in DRS4

October 19, 2011             DAQ+Trigger operation   16
                      DRS2 linearity
• Cell-dependent non-linear response function applied
• Differential linearity restored at 2%
      DRS amplitude




                                     TRG amplitude
October 19, 2011          DAQ+Trigger operation         17
                         Timing
• Test done by splitting the same TC pulse to 2 channels of
  the same chip
• Plot of (t0-t1)/2

              DRS2                                     DRS3




rms = 9.4 ps                              rms = 6.6 ps




             negligible with respect to detector resolution
Different domino waves running on different chips
       chip-to-chip timing needs calibration        critical issue
October 19, 2011           DAQ+Trigger operation                     18
                    DRS4 design
• Same VME board as former versions
• New mezzanine card
    – Single ended          differential input (common-noise suppression)
    – Memory doubled
         • (up to 3.2 GHz sampling or 2x wider time window)
    – All domino waves running synchronously (ref. CLK jitter < 10 ps)
    – New DC supply at 2.5 V
         • compatibility with FPGA LVDS ref. CLK




October 19, 2011             DAQ+Trigger operation                    19
                  DRS4 Schedule
• Add special clock chip for in-situ calibration
• First prototype DRS4 mezzanine board end of February
• Extend mezzanine firmware: Store calibration in EEPROM,
  channel cascading (needed for 3.2 GSPS operation), in-situ
  timing calibration
• Test in area (March) with cosmics
• Start mass production: 5-6 weeks           ( end of May)
• Deploy DRS4 boards in area: June
• Use July as contingency




Sept. 9th, 2008          MEG weekly meeting                    20
 Further improvements in 2009
• Hardware
    – Test of the electronics chain by injecting a test pulse
      from splitter output
• DAQ
    – No calibration needed for DRS4            DAQ speed-up
         • Max. rate 30      50 ev/s,    %Live 80%       90%
    – Reduce dead time (6.5%) due to Start/Stop procedure
         • Subrun
    – Fix residual troubles
• Trigger
    – Optimization of dynamic range
         • might be a concern if LXe light yield increases
• DRS4
October 19, 2011           DAQ+Trigger operation                21
Backup slides
                         System overview
                                                                             „cave‟
                         pE5 area
                                                 Ancillary
                                   Trigger        system
clock
start                                                                     Front-End PCs
stop                                                                        PC (Linux)     Master
sync             Trigger
                  Trigger                                                   PC (Linux)
                    Trigger                                                 PC (Linux)
                                                     Run start
                                                     Run stop               PC (Linux)
              4 crates                               Trigger config         PC (Linux)
                                             Busy                           PC (Linux)
                                             Error                          PC (Linux)
                 DRS                                                        PC (Linux)
20 MHz            DRS                                                       PC (Linux)
 clock             DRS
                     DRS                                              Gigabit
                      DRS                                             Ethernet
                       DRS
                                                                                           Event
                                                                            PC (Linux)
                                                                                           builder
                                       Trigger signal                       PC (Linux)
                         Hit           Event number                         PC (Linux)
                       registers       Trigger type                         PC (Linux)

              5 crates                                                      On-line farm
                                                                storage
    October 19, 2011                DAQ+Trigger operation                                  23
                            DAQ scheme
                              trigger & trigger type & event # LSB
                              busy

     TRG1 TRG2 TRG3 TRG9 DRS4 DRS5 DRS6 DRS7 DRS8

            internal trigger & busy


      SYSTEM01   SYSTEM02   SYSTEM03   SYSTEM04   SYSTEM05   SYSTEM06   SYSTEM07   SYSTEM08   SYSTEM09




                                           Event Builder                            stop sequence
                                                                                    start sequence
                                                   SYSTEM




                                                  Logger


October 19, 2011                         DAQ+Trigger operation                                           24
                                Event “mismatch”
              TRG1 TRG2 TRG3 TRG9 DRS4 DRS5 DRS6 DRS7 DRS8


HW event #         52        52        52          52           52        52          52          52        52
SW serial #        52        52        52          52           52        51          52          52        52

HW event #          51        51       51         51           51                      51         51        51
SW serial #         51        51       51         51           51                      51         51        51


HW event #         50        50        50          50          50         50         50           50        50
SW serial #        50        50        50          50          50         50         50           50        50

              SYSTEM01   SYSTEM02   SYSTEM03   SYSTEM04   SYSTEM05   SYSTEM06   SYSTEM07    SYSTEM08   SYSTEM09




          Run stopped, error message returned by Event Builder

     25
                         The trigger tree
                                                                      2 boards
                                                     14 boards
           Inner face                        Type1        14 x 48
                               16          Type1                                   2 x48
          (216 PMTs)                     Type1                          Type2
                                   4
                                                                     Type2
LXe          Side faces                      Type1
                                                     5+4+2 boards
                                                                      1 board
      lat. (144x2 PMTs) 4x1    16          Type1
                                         Type1                                             1 board
                                                            9 x 48
       back (216 PMTs) 4x1         4
                                                                                2 x48                START
       u/d (54x2 PMTs) 4x1                                           Type2                           STOP
                                                                                            Type2    CLK
                                                                       1 board                       SYNC
                                                     8 boards
              Bars                           Type1         9 x 48
          (30x2 PMTs)          16          Type1
TC
                                         Type1                                  2 x48
             Fibers                4
                                                                     Type2
        (512 APDs) 8x1
                                                     4 boards         1 board
                                   16
            Wires
DC                                        Type1            4 x 48
                              16
                                        Type1
         64 channels          4                                                 1 x 48
                                                                     Type2
        NaI+pre-shower             16             1 board

Aux                                       Type1
                                                                         Synchronous operation
         16 channels

                                                                              at 100 MHz
         CR counters               16             2 boards
                              16
                                          Type1
         32 channels                    Type1
                   Rate monitor




October 19, 2011      DAQ+Trigger operation   27

				
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posted:10/19/2011
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